X-Git-Url: http://mj.ucw.cz/gitweb/?a=blobdiff_plain;ds=sidebyside;f=lib%2Fi386-ports.c;h=5f8aea437a1f2d0ff7849f6dafd26839f1e0191b;hb=7d23054d18402b1891343f090d3cd37d7e83c82f;hp=0b1677a236c7320139f1dafb2f3f2959a0bace47;hpb=5c5ce19215cdfa54c878e09211e3cd3bc8344b82;p=pciutils.git diff --git a/lib/i386-ports.c b/lib/i386-ports.c index 0b1677a..5f8aea4 100644 --- a/lib/i386-ports.c +++ b/lib/i386-ports.c @@ -3,14 +3,16 @@ * * Copyright (c) 1997--2006 Martin Mares * - * Can be freely distributed and used under the terms of the GNU GPL. + * Can be freely distributed and used under the terms of the GNU GPL v2+. + * + * SPDX-License-Identifier: GPL-2.0-or-later */ #define _GNU_SOURCE #include "internal.h" -#include +#include #if defined(PCI_OS_LINUX) #include "i386-io-linux.h" @@ -28,6 +30,8 @@ #include "i386-io-beos.h" #elif defined(PCI_OS_DJGPP) #include "i386-io-djgpp.h" +#elif defined(PCI_OS_OPENBSD) +#include "i386-io-openbsd.h" #else #error Do not know how to access I/O ports on this OS. #endif @@ -50,10 +54,13 @@ conf12_init(struct pci_access *a) } static void -conf12_cleanup(struct pci_access *a UNUSED) +conf12_cleanup(struct pci_access *a) { if (conf12_io_enabled > 0) - conf12_io_enabled = intel_cleanup_io(a); + { + intel_cleanup_io(a); + conf12_io_enabled = -1; + } } /* @@ -72,6 +79,7 @@ intel_sanity_check(struct pci_access *a, struct pci_methods *m) { struct pci_dev d; + memset(&d, 0, sizeof(d)); a->debug("...sanity check"); d.bus = 0; d.func = 0; @@ -110,12 +118,12 @@ conf1_detect(struct pci_access *a) } intel_io_lock(); - outb (0x01, 0xCFB); - tmp = inl (0xCF8); - outl (0x80000000, 0xCF8); - if (inl (0xCF8) == 0x80000000) + intel_outb (0x01, 0xCFB); + tmp = intel_inl (0xCF8); + intel_outl (0x80000000, 0xCF8); + if (intel_inl (0xCF8) == 0x80000000) res = 1; - outl (tmp, 0xCF8); + intel_outl (tmp, 0xCF8); intel_io_unlock(); if (res) @@ -129,25 +137,26 @@ conf1_read(struct pci_dev *d, int pos, byte *buf, int len) int addr = 0xcfc + (pos&3); int res = 1; - if (pos >= 256) + if (d->domain || pos >= 256) return 0; + if (len != 1 && len != 2 && len != 4) + return pci_generic_block_read(d, pos, buf, len); + intel_io_lock(); - outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8); + intel_outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8); switch (len) { case 1: - buf[0] = inb(addr); + buf[0] = intel_inb(addr); break; case 2: - ((u16 *) buf)[0] = cpu_to_le16(inw(addr)); + ((u16 *) buf)[0] = cpu_to_le16(intel_inw(addr)); break; case 4: - ((u32 *) buf)[0] = cpu_to_le32(inl(addr)); + ((u32 *) buf)[0] = cpu_to_le32(intel_inl(addr)); break; - default: - res = pci_generic_block_read(d, pos, buf, len); } intel_io_unlock(); @@ -160,25 +169,26 @@ conf1_write(struct pci_dev *d, int pos, byte *buf, int len) int addr = 0xcfc + (pos&3); int res = 1; - if (pos >= 256) + if (d->domain || pos >= 256) return 0; + if (len != 1 && len != 2 && len != 4) + return pci_generic_block_write(d, pos, buf, len); + intel_io_lock(); - outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8); + intel_outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8); switch (len) { case 1: - outb(buf[0], addr); + intel_outb(buf[0], addr); break; case 2: - outw(le16_to_cpu(((u16 *) buf)[0]), addr); + intel_outw(le16_to_cpu(((u16 *) buf)[0]), addr); break; case 4: - outl(le32_to_cpu(((u32 *) buf)[0]), addr); + intel_outl(le32_to_cpu(((u32 *) buf)[0]), addr); break; - default: - res = pci_generic_block_write(d, pos, buf, len); } intel_io_unlock(); return res; @@ -202,10 +212,10 @@ conf2_detect(struct pci_access *a) /* This is ugly and tends to produce false positives. Beware. */ intel_io_lock(); - outb(0x00, 0xCFB); - outb(0x00, 0xCF8); - outb(0x00, 0xCFA); - if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00) + intel_outb(0x00, 0xCFB); + intel_outb(0x00, 0xCF8); + intel_outb(0x00, 0xCFA); + if (intel_inb(0xCF8) == 0x00 && intel_inb(0xCFA) == 0x00) res = intel_sanity_check(a, &pm_intel_conf2); intel_io_unlock(); return res; @@ -217,31 +227,32 @@ conf2_read(struct pci_dev *d, int pos, byte *buf, int len) int res = 1; int addr = 0xc000 | (d->dev << 8) | pos; - if (pos >= 256) + if (d->domain || pos >= 256) return 0; if (d->dev >= 16) /* conf2 supports only 16 devices per bus */ return 0; + if (len != 1 && len != 2 && len != 4) + return pci_generic_block_read(d, pos, buf, len); + intel_io_lock(); - outb((d->func << 1) | 0xf0, 0xcf8); - outb(d->bus, 0xcfa); + intel_outb((d->func << 1) | 0xf0, 0xcf8); + intel_outb(d->bus, 0xcfa); switch (len) { case 1: - buf[0] = inb(addr); + buf[0] = intel_inb(addr); break; case 2: - ((u16 *) buf)[0] = cpu_to_le16(inw(addr)); + ((u16 *) buf)[0] = cpu_to_le16(intel_inw(addr)); break; case 4: - ((u32 *) buf)[0] = cpu_to_le32(inl(addr)); + ((u32 *) buf)[0] = cpu_to_le32(intel_inl(addr)); break; - default: - res = pci_generic_block_read(d, pos, buf, len); } - outb(0, 0xcf8); + intel_outb(0, 0xcf8); intel_io_unlock(); return res; } @@ -252,31 +263,33 @@ conf2_write(struct pci_dev *d, int pos, byte *buf, int len) int res = 1; int addr = 0xc000 | (d->dev << 8) | pos; - if (pos >= 256) + if (d->domain || pos >= 256) return 0; if (d->dev >= 16) - d->access->error("conf2_write: only first 16 devices exist."); + /* conf2 supports only 16 devices per bus */ + return 0; + + if (len != 1 && len != 2 && len != 4) + return pci_generic_block_write(d, pos, buf, len); intel_io_lock(); - outb((d->func << 1) | 0xf0, 0xcf8); - outb(d->bus, 0xcfa); + intel_outb((d->func << 1) | 0xf0, 0xcf8); + intel_outb(d->bus, 0xcfa); switch (len) { case 1: - outb(buf[0], addr); + intel_outb(buf[0], addr); break; case 2: - outw(le16_to_cpu(* (u16 *) buf), addr); + intel_outw(le16_to_cpu(* (u16 *) buf), addr); break; case 4: - outl(le32_to_cpu(* (u32 *) buf), addr); + intel_outl(le32_to_cpu(* (u32 *) buf), addr); break; - default: - res = pci_generic_block_write(d, pos, buf, len); } - outb(0, 0xcf8); + intel_outb(0, 0xcf8); intel_io_unlock(); return res; }