X-Git-Url: http://mj.ucw.cz/gitweb/?a=blobdiff_plain;ds=sidebyside;f=lib%2Fi386-ports.c;h=1e2c4028e08dca240bee387c9b0d0e443cf76f5f;hb=6182921907ef3cc31be3394eb468b24bcd3955a8;hp=ce5d35f68d314000b8f5f5d856e8dfa4d811bdd3;hpb=a27a33dde338ab9d809bebbade328559eaae733b;p=pciutils.git diff --git a/lib/i386-ports.c b/lib/i386-ports.c index ce5d35f..1e2c402 100644 --- a/lib/i386-ports.c +++ b/lib/i386-ports.c @@ -1,45 +1,64 @@ /* - * $Id: i386-ports.c,v 1.3 2002/03/30 15:39:25 mj Exp $ - * * The PCI Library -- Direct Configuration access via i386 Ports * - * Copyright (c) 1997--1999 Martin Mares + * Copyright (c) 1997--2006 Martin Mares + * + * Can be freely distributed and used under the terms of the GNU GPL v2+. * - * Can be freely distributed and used under the terms of the GNU GPL. + * SPDX-License-Identifier: GPL-2.0-or-later */ -#include +#define _GNU_SOURCE + +#include "internal.h" + +#include -#ifdef __GLIBC__ -#include +#if defined(PCI_OS_LINUX) +#include "i386-io-linux.h" +#elif defined(PCI_OS_GNU) +#include "i386-io-hurd.h" +#elif defined(PCI_OS_SUNOS) +#include "i386-io-sunos.h" +#elif defined(PCI_OS_WINDOWS) +#include "i386-io-windows.h" +#elif defined(PCI_OS_CYGWIN) +#include "i386-io-cygwin.h" +#elif defined(PCI_OS_HAIKU) +#include "i386-io-haiku.h" +#elif defined(PCI_OS_BEOS) +#include "i386-io-beos.h" +#elif defined(PCI_OS_DJGPP) +#include "i386-io-djgpp.h" #else -#include +#error Do not know how to access I/O ports on this OS. #endif -#include "internal.h" - -static int intel_iopl_set = -1; +static int conf12_io_enabled = -1; /* -1=haven't tried, 0=failed, 1=succeeded */ static int -intel_setup_io(void) +conf12_setup_io(struct pci_access *a) { - if (intel_iopl_set < 0) - intel_iopl_set = (iopl(3) < 0) ? 0 : 1; - return intel_iopl_set; + if (conf12_io_enabled < 0) + conf12_io_enabled = intel_setup_io(a); + return conf12_io_enabled; } static void conf12_init(struct pci_access *a) { - if (!intel_setup_io()) - a->error("You need to be root to have access to I/O ports."); + if (!conf12_setup_io(a)) + a->error("No permission to access I/O ports (you probably have to be root)."); } static void -conf12_cleanup(struct pci_access * UNUSED a) +conf12_cleanup(struct pci_access *a) { - iopl(3); - intel_iopl_set = -1; + if (conf12_io_enabled > 0) + { + intel_cleanup_io(a); + conf12_io_enabled = -1; + } } /* @@ -58,10 +77,11 @@ intel_sanity_check(struct pci_access *a, struct pci_methods *m) { struct pci_dev d; + memset(&d, 0, sizeof(d)); a->debug("...sanity check"); d.bus = 0; d.func = 0; - for(d.dev = 0; d.dev < 32; d.dev++) + for (d.dev = 0; d.dev < 32; d.dev++) { u16 class, vendor; if (m->read(&d, PCI_CLASS_DEVICE, (byte *) &class, sizeof(class)) && @@ -89,17 +109,21 @@ conf1_detect(struct pci_access *a) unsigned int tmp; int res = 0; - if (!intel_setup_io()) + if (!conf12_setup_io(a)) { a->debug("...no I/O permission"); return 0; } + + intel_io_lock(); outb (0x01, 0xCFB); tmp = inl (0xCF8); outl (0x80000000, 0xCF8); if (inl (0xCF8) == 0x80000000) res = 1; outl (tmp, 0xCF8); + intel_io_unlock(); + if (res) res = intel_sanity_check(a, &pm_intel_conf1); return res; @@ -109,6 +133,15 @@ static int conf1_read(struct pci_dev *d, int pos, byte *buf, int len) { int addr = 0xcfc + (pos&3); + int res = 1; + + if (d->domain || pos >= 256) + return 0; + + if (len != 1 && len != 2 && len != 4) + return pci_generic_block_read(d, pos, buf, len); + + intel_io_lock(); outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8); switch (len) @@ -122,16 +155,25 @@ conf1_read(struct pci_dev *d, int pos, byte *buf, int len) case 4: ((u32 *) buf)[0] = cpu_to_le32(inl(addr)); break; - default: - return pci_generic_block_read(d, pos, buf, len); } - return 1; + + intel_io_unlock(); + return res; } static int conf1_write(struct pci_dev *d, int pos, byte *buf, int len) { int addr = 0xcfc + (pos&3); + int res = 1; + + if (d->domain || pos >= 256) + return 0; + + if (len != 1 && len != 2 && len != 4) + return pci_generic_block_write(d, pos, buf, len); + + intel_io_lock(); outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8); switch (len) @@ -145,10 +187,9 @@ conf1_write(struct pci_dev *d, int pos, byte *buf, int len) case 4: outl(le32_to_cpu(((u32 *) buf)[0]), addr); break; - default: - return pci_generic_block_write(d, pos, buf, len); } - return 1; + intel_io_unlock(); + return res; } /* @@ -158,7 +199,9 @@ conf1_write(struct pci_dev *d, int pos, byte *buf, int len) static int conf2_detect(struct pci_access *a) { - if (!intel_setup_io()) + int res = 0; + + if (!conf12_setup_io(a)) { a->debug("...no I/O permission"); return 0; @@ -166,23 +209,33 @@ conf2_detect(struct pci_access *a) /* This is ugly and tends to produce false positives. Beware. */ + intel_io_lock(); outb(0x00, 0xCFB); outb(0x00, 0xCF8); outb(0x00, 0xCFA); if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00) - return intel_sanity_check(a, &pm_intel_conf2); - else - return 0; + res = intel_sanity_check(a, &pm_intel_conf2); + intel_io_unlock(); + return res; } static int conf2_read(struct pci_dev *d, int pos, byte *buf, int len) { + int res = 1; int addr = 0xc000 | (d->dev << 8) | pos; + if (d->domain || pos >= 256) + return 0; + if (d->dev >= 16) /* conf2 supports only 16 devices per bus */ return 0; + + if (len != 1 && len != 2 && len != 4) + return pci_generic_block_read(d, pos, buf, len); + + intel_io_lock(); outb((d->func << 1) | 0xf0, 0xcf8); outb(d->bus, 0xcfa); switch (len) @@ -196,21 +249,29 @@ conf2_read(struct pci_dev *d, int pos, byte *buf, int len) case 4: ((u32 *) buf)[0] = cpu_to_le32(inl(addr)); break; - default: - outb(0, 0xcf8); - return pci_generic_block_read(d, pos, buf, len); } outb(0, 0xcf8); - return 1; + intel_io_unlock(); + return res; } static int conf2_write(struct pci_dev *d, int pos, byte *buf, int len) { + int res = 1; int addr = 0xc000 | (d->dev << 8) | pos; + if (d->domain || pos >= 256) + return 0; + if (d->dev >= 16) - d->access->error("conf2_write: only first 16 devices exist."); + /* conf2 supports only 16 devices per bus */ + return 0; + + if (len != 1 && len != 2 && len != 4) + return pci_generic_block_write(d, pos, buf, len); + + intel_io_lock(); outb((d->func << 1) | 0xf0, 0xcf8); outb(d->bus, 0xcfa); switch (len) @@ -224,16 +285,16 @@ conf2_write(struct pci_dev *d, int pos, byte *buf, int len) case 4: outl(le32_to_cpu(* (u32 *) buf), addr); break; - default: - outb(0, 0xcf8); - return pci_generic_block_write(d, pos, buf, len); } + outb(0, 0xcf8); - return 1; + intel_io_unlock(); + return res; } struct pci_methods pm_intel_conf1 = { - "Intel-conf1", + "intel-conf1", + "Raw I/O port access using Intel conf1 interface", NULL, /* config */ conf1_detect, conf12_init, @@ -242,12 +303,14 @@ struct pci_methods pm_intel_conf1 = { pci_generic_fill_info, conf1_read, conf1_write, + NULL, /* read_vpd */ NULL, /* init_dev */ NULL /* cleanup_dev */ }; struct pci_methods pm_intel_conf2 = { - "Intel-conf2", + "intel-conf2", + "Raw I/O port access using Intel conf2 interface", NULL, /* config */ conf2_detect, conf12_init, @@ -256,6 +319,7 @@ struct pci_methods pm_intel_conf2 = { pci_generic_fill_info, conf2_read, conf2_write, + NULL, /* read_vpd */ NULL, /* init_dev */ NULL /* cleanup_dev */ };