X-Git-Url: http://mj.ucw.cz/gitweb/?a=blobdiff_plain;ds=inline;f=lib%2Fheader.h;h=aa163a0a5ebbcd1096f75b246750cc72199e3bbd;hb=d45531756b426fb883e78deb412be3c031bb7675;hp=ef4b8fb3f42b37c34fc138c034b73d8ed152f4de;hpb=06cb86c3839ba50106fb578c815733a7d2d94b04;p=pciutils.git diff --git a/lib/header.h b/lib/header.h index ef4b8fb..aa163a0 100644 --- a/lib/header.h +++ b/lib/header.h @@ -187,7 +187,7 @@ #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ -#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ +#define PCI_CAP_ID_MSI 0x05 /* Message Signaled Interrupts */ #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ @@ -219,6 +219,8 @@ #define PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */ #define PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */ #define PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */ +#define PCI_EXT_CAP_ID_ARI 0x0e /* Alternative Routing-ID Interpretation */ +#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ /* Power Management Registers */ @@ -285,7 +287,7 @@ #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ -/* Message Signalled Interrupts registers */ +/* Message Signaled Interrupts registers */ #define PCI_MSI_FLAGS 2 /* Various flags */ #define PCI_MSI_FLAGS_MASK_BIT 0x100 /* interrupt masking & reporting supported */ @@ -921,6 +923,63 @@ #define PCI_PWR_CAP 12 /* Capability */ #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ +/* Access Control Services */ +#define PCI_ACS_CAP 0x04 /* ACS Capability Register */ +#define PCI_ACS_CAP_VALID 0x0001 /* ACS Source Validation */ +#define PCI_ACS_CAP_BLOCK 0x0002 /* ACS Translation Blocking */ +#define PCI_ACS_CAP_REQ_RED 0x0004 /* ACS P2P Request Redirect */ +#define PCI_ACS_CAP_CMPLT_RED 0x0008 /* ACS P2P Completion Redirect */ +#define PCI_ACS_CAP_FORWARD 0x0010 /* ACS Upstream Forwarding */ +#define PCI_ACS_CAP_EGRESS 0x0020 /* ACS P2P Egress Control */ +#define PCI_ACS_CAP_TRANS 0x0040 /* ACS Direct Translated P2P */ +#define PCI_ACS_CAP_VECTOR(x) (((x) >> 8) & 0xff) /* Egress Control Vector Size */ +#define PCI_ACS_CTRL 0x06 /* ACS Control Register */ +#define PCI_ACS_CTRL_VALID 0x0001 /* ACS Source Validation Enable */ +#define PCI_ACS_CTRL_BLOCK 0x0002 /* ACS Translation Blocking Enable */ +#define PCI_ACS_CTRL_REQ_RED 0x0004 /* ACS P2P Request Redirect Enable */ +#define PCI_ACS_CTRL_CMPLT_RED 0x0008 /* ACS P2P Completion Redirect Enable */ +#define PCI_ACS_CTRL_FORWARD 0x0010 /* ACS Upstream Forwarding Enable */ +#define PCI_ACS_CTRL_EGRESS 0x0020 /* ACS P2P Egress Control Enable */ +#define PCI_ACS_CTRL_TRANS 0x0040 /* ACS Direct Translated P2P Enable */ +#define PCI_ACS_EGRESS_CTRL 0x08 /* Egress Control Vector */ + +/* Alternative Routing-ID Interpretation */ +#define PCI_ARI_CAP 0x04 /* ARI Capability Register */ +#define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */ +#define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */ +#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */ +#define PCI_ARI_CTRL 0x06 /* ARI Control Register */ +#define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */ +#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ +#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ + +/* Single Root I/O Virtualization */ +#define PCI_IOV_CAP 0x04 /* SR-IOV Capability Register */ +#define PCI_IOV_CAP_VFM 0x00000001 /* VF Migration Capable */ +#define PCI_IOV_CAP_IMN(x) ((x) >> 21) /* VF Migration Interrupt Message Number */ +#define PCI_IOV_CTRL 0x08 /* SR-IOV Control Register */ +#define PCI_IOV_CTRL_VFE 0x0001 /* VF Enable */ +#define PCI_IOV_CTRL_VFME 0x0002 /* VF Migration Enable */ +#define PCI_IOV_CTRL_VFMIE 0x0004 /* VF Migration Interrupt Enable */ +#define PCI_IOV_CTRL_MSE 0x0008 /* VF MSE */ +#define PCI_IOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */ +#define PCI_IOV_STATUS 0x0a /* SR-IOV Status Register */ +#define PCI_IOV_STATUS_MS 0x0001 /* VF Migration Status */ +#define PCI_IOV_INITIALVF 0x0c /* Number of VFs that are initially associated */ +#define PCI_IOV_TOTALVF 0x0e /* Maximum number of VFs that could be associated */ +#define PCI_IOV_NUMVF 0x10 /* Number of VFs that are available */ +#define PCI_IOV_FDL 0x12 /* Function Dependency Link */ +#define PCI_IOV_OFFSET 0x14 /* First VF Offset */ +#define PCI_IOV_STRIDE 0x16 /* Routing ID offset from one VF to the next one */ +#define PCI_IOV_DID 0x1a /* VF Device ID */ +#define PCI_IOV_SUPPS 0x1c /* Supported Page Sizes */ +#define PCI_IOV_SYSPS 0x20 /* System Page Size */ +#define PCI_IOV_BAR_BASE 0x24 /* VF BAR0, VF BAR1, ... VF BAR5 */ +#define PCI_IOV_NUM_BAR 6 /* Number of VF BARs */ +#define PCI_IOV_MSAO 0x3c /* VF Migration State Array Offset */ +#define PCI_IOV_MSA_BIR(x) ((x) & 7) /* VF Migration State BIR */ +#define PCI_IOV_MSA_OFFSET(x) ((x) & 0xfffffff8) /* VF Migration State Offset */ + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded