lspci: Add support for CXL MLD DVSEC

[pciutils.git] / tests / cap-pcie-2

diff --git a/tests/cap-pcie-2 b/tests/cap-pcie-2
index b7944a3f01a61d81852efe1caf73f3164f8d3e58..9bde139861666cd624473a31a3d3b5d13352ed0a 100644 (file)
--- a/tests/cap-pcie-2
+++ b/tests/cap-pcie-2
@@ -26,7 +26,7 @@
                        MaxPayload 256 bytes, MaxReadReq 512 bytes
                DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend-
                LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s L1, Latency L0 <4us, L1 <64us
-                       ClockPM- Suprise- LLActRep- BwNot-
+                       ClockPM- Surprise- LLActRep- BwNot-
                LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
@@ -48,8 +48,8 @@
                ARICap: MFVC- ACS-, Next Function: 1
                ARICtl: MFVC- ACS-, Function Group: 0
        Capabilities: [160] Single Root I/O Virtualization (SR-IOV)
-               IOVCap: Migration-, Interrupt Message Number: 000
-               IOVCtl: Enable+ Migration- Interrupt- MSE+ ARIHierarchy-
+               IOVCap: Migration- 10BitTagReq- Interrupt Message Number: 000
+               IOVCtl: Enable+ Migration- Interrupt- MSE+ ARIHierarchy- 10BitTagReq-
                IOVSta: Migration-
                Initial VFs: 8, Total VFs: 8, Number of VFs: 1, Function Dependency Link: 00
                VF offset: 384, stride: 2, Device ID: 10ca