Fix stripping in cross-compiling mode

[pciutils.git] / tests / cap-pcie-1

diff --git a/tests/cap-pcie-1 b/tests/cap-pcie-1
index f82b71d4cee51c443ef54efa34dbace679d691d3..b69184fb8735b8641017b0951527a27dc75a5e73 100644 (file)
--- a/tests/cap-pcie-1
+++ b/tests/cap-pcie-1
@@ -21,11 +21,11 @@
                        MaxPayload 256 bytes, MaxReadReq 128 bytes
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
                LnkCap: Port #1, Speed 5GT/s, Width x4, ASPM L0s L1, Latency L0 <512ns, L1 <4us
-                       ClockPM- Suprise+ LLActRep+ BwNot+
+                       ClockPM- Surprise+ LLActRep+ BwNot+
                LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
-               SltCap: AttnBtn+ PwrCtrl+ MRL+ AttnInd+ PwrInd+ HotPlug- Surpise-
+               SltCap: AttnBtn+ PwrCtrl+ MRL+ AttnInd+ PwrInd+ HotPlug- Surprise-
                        Slot # 40, PowerLimit 0.000000; Interlock+ NoCompl-
                SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
                        Control: AttnInd Off, PwrInd Off, Power+ Interlock-