#include <stdarg.h>
#include <unistd.h>
+#define PCIUTILS_LSPCI
#include "pciutils.h"
/* Options */
static char help_msg[] =
"Usage: lspci [<switches>]\n"
"\n"
-"-v\t\tBe verbose\n"
+"Basic display modes:\n"
+"-mm\t\tProduce machine-readable output (single -m for an obsolete format)\n"
+"-t\t\tShow bus tree\n"
+"\n"
+"Display options:\n"
+"-v\t\tBe verbose (-vv for very verbose)\n"
+#ifdef PCI_OS_LINUX
+"-k\t\tShow kernel drivers handling each device\n"
+#endif
+"-x\t\tShow hex-dump of the standard part of the config space\n"
+"-xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n"
+"-xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n"
+"-b\t\tBus-centric view (addresses and IRQ's as seen by the bus)\n"
+"-D\t\tAlways show domain numbers\n"
+"\n"
+"Resolving of device ID's to names:\n"
"-n\t\tShow numeric ID's\n"
"-nn\t\tShow both textual and numeric ID's (names & numbers)\n"
#ifdef PCI_USE_DNS
"-qq\t\tAs above, but re-query locally cached entries\n"
"-Q\t\tQuery the PCI ID database for all ID's via DNS\n"
#endif
-"-b\t\tBus-centric view (PCI addresses and IRQ's instead of those seen by the CPU)\n"
-"-x\t\tShow hex-dump of the standard portion of config space\n"
-"-xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n"
-"-xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n"
+"\n"
+"Selection of devices:\n"
"-s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n"
-"-d [<vendor>]:[<device>]\tShow only selected devices\n"
-"-t\t\tShow bus tree\n"
-"-m\t\tProduce machine-readable output\n"
+"-d [<vendor>]:[<device>]\t\t\tShow only devices with specified ID's\n"
+"\n"
+"Other options:\n"
"-i <file>\tUse specified ID database instead of %s\n"
#ifdef PCI_OS_LINUX
-"-k\t\tShow kernel drivers handling each device\n"
"-p <file>\tLook up kernel modules in a given file instead of default modules.pcimap\n"
#endif
-"-D\t\tAlways show domain numbers\n"
"-M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
+"\n"
+"PCI access options:\n"
GENERIC_HELP
;
if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
return;
rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
- if (rid < 0x23 && rid > 0x11)
+ if (rid < 0x22 && rid > 0x11)
printf("\t\t!!! Possibly incomplete decoding\n");
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
else
fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
FLAG(cmd, PCI_HT_PRI_CMD_DD),
FLAG(cmd, PCI_HT_PRI_CMD_DUL));
lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
else
fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
FLAG(lctr0, PCI_HT_LCTR_64B));
lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
else
fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
FLAG(lcnf0, PCI_HT_LCNF_DFIE),
FLAG(lcnf0, PCI_HT_LCNF_DFOE));
lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
else
fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
FLAG(lctr1, PCI_HT_LCTR_64B));
lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
else
fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
FLAG(lcnf1, PCI_HT_LCNF_DFOE));
printf("\t\tRevision ID: %u.%02u\n",
(rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
- if (rid < 0x23)
+ if (rid < 0x22)
return;
lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
return;
rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
- if (rid < 0x23 && rid > 0x11)
+ if (rid < 0x22 && rid > 0x11)
printf("\t\t!!! Possibly incomplete decoding\n");
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
else
fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
FLAG(cmd, PCI_HT_SEC_CMD_DUL));
lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
else
fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
FLAG(lctr, PCI_HT_LCTR_EXTCTL),
FLAG(lctr, PCI_HT_LCTR_64B));
lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
else
fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
FLAG(lcnf, PCI_HT_LCNF_DFOE));
printf("\t\tRevision ID: %u.%02u\n",
(rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
- if (rid < 0x23)
+ if (rid < 0x22)
return;
lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
u32 t;
u16 w;
- printf("Message Signalled Interrupts: Mask%c 64bit%c Queue=%d/%d Enable%c\n",
+ printf("MSI: Mask%c 64bit%c Count=%d/%d Enable%c\n",
FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
FLAG(cap, PCI_MSI_FLAGS_64BIT),
- (cap & PCI_MSI_FLAGS_QSIZE) >> 4,
- (cap & PCI_MSI_FLAGS_QMASK) >> 1,
+ 1 << ((cap & PCI_MSI_FLAGS_QSIZE) >> 4),
+ 1 << ((cap & PCI_MSI_FLAGS_QMASK) >> 1),
FLAG(cap, PCI_MSI_FLAGS_ENABLE));
if (verbose < 2)
return;
FLAG(w, PCI_EXP_DEVSTA_URD),
FLAG(w, PCI_EXP_DEVSTA_AUXPD),
FLAG(w, PCI_EXP_DEVSTA_TRPND));
-
- /* FIXME: Second set of control/status registers is not supported yet. */
}
static char *link_speed(int speed)
FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
}
+static const char *cap_express_dev2_timeout_range(int type)
+{
+ /* Decode Completion Timeout Ranges. */
+ switch (type)
+ {
+ case 0:
+ return "Not Supported";
+ case 1:
+ return "Range A";
+ case 2:
+ return "Range B";
+ case 3:
+ return "Range AB";
+ case 6:
+ return "Range BC";
+ case 7:
+ return "Range ABC";
+ case 14:
+ return "Range BCD";
+ case 15:
+ return "Range ABCD";
+ default:
+ return "Unknown";
+ }
+}
+
+static const char *cap_express_dev2_timeout_value(int type)
+{
+ /* Decode Completion Timeout Value. */
+ switch (type)
+ {
+ case 0:
+ return "50us to 50ms";
+ case 1:
+ return "50us to 100us";
+ case 2:
+ return "1ms to 10ms";
+ case 5:
+ return "16ms to 55ms";
+ case 6:
+ return "65ms to 210ms";
+ case 9:
+ return "260ms to 900ms";
+ case 10:
+ return "1s to 3.5s";
+ case 13:
+ return "4s to 13s";
+ case 14:
+ return "17s to 64s";
+ default:
+ return "Unknown";
+ }
+}
+
+static void cap_express_dev2(struct device *d, int where, int type)
+{
+ u32 l;
+ u16 w;
+
+ l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
+ printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c",
+ cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)),
+ FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS));
+ if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
+ printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEV2_ARI));
+ else
+ printf("\n");
+
+ w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
+ printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c",
+ cap_express_dev2_timeout_value(PCI_EXP_DEV2_TIMEOUT_VALUE(w)),
+ FLAG(w, PCI_EXP_DEV2_TIMEOUT_DIS));
+ if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
+ printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEV2_ARI));
+ else
+ printf("\n");
+}
+
+static const char *cap_express_link2_speed(int type)
+{
+ switch (type)
+ {
+ case 0: /* hardwire to 0 means only the 2.5GT/s is supported */
+ case 1:
+ return "2.5GT/s";
+ case 2:
+ return "5GT/s";
+ default:
+ return "Unknown";
+ }
+}
+
+static const char *cap_express_link2_deemphasis(int type)
+{
+ switch (type)
+ {
+ case 0:
+ return "-6dB";
+ case 1:
+ return "-3.5dB";
+ default:
+ return "Unknown";
+ }
+}
+
+static const char *cap_express_link2_transmargin(int type)
+{
+ switch (type)
+ {
+ case 0:
+ return "Normal Operating Range";
+ case 1:
+ return "800-1200mV(full-swing)/400-700mV(half-swing)";
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ return "200-400mV(full-swing)/100-200mV(half-swing)";
+ default:
+ return "Unknown";
+ }
+}
+
+static void cap_express_link2(struct device *d, int where, int type UNUSED)
+{
+ u16 w;
+
+ w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
+ printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c, Selectable De-emphasis: %s\n"
+ "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
+ "\t\t\t Compliance De-emphasis: %s\n",
+ cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)),
+ FLAG(w, PCI_EXP_LNKCTL2_CMPLNC),
+ FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS),
+ cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)),
+ cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)),
+ FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC),
+ FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS),
+ cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w)));
+
+ w = get_conf_word(d, where + PCI_EXP_LNKSTA2);
+ printf("\t\tLnkSta2: Current De-emphasis Level: %s\n",
+ cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)));
+}
+
+static void cap_express_slot2(struct device *d UNUSED, int where UNUSED)
+{
+ /* No capabilities that require this field in PCIe rev2.0 spec. */
+}
+
static void
cap_express(struct device *d, int where, int cap)
{
cap_express_slot(d, where);
if (type == PCI_EXP_TYPE_ROOT_PORT)
cap_express_root(d, where);
+
+ if ((cap & PCI_EXP_FLAGS_VERS) < 2)
+ return;
+
+ size = 16;
+ if (slot)
+ size = 24;
+ if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size))
+ return;
+
+ cap_express_dev2(d, where, type);
+ cap_express_link2(d, where, type);
+ if (slot)
+ cap_express_slot2(d, where);
}
static void
printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
}
+static void
+cap_aer(struct device *d, int where)
+{
+ u32 l;
+
+ printf("Advanced Error Reporting\n");
+ if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 24))
+ return;
+
+ l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS);
+ printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
+ "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
+ FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
+ FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
+ FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
+ FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
+ l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK);
+ printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
+ "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
+ FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
+ FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
+ FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
+ FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
+ l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER);
+ printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
+ "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
+ FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
+ FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
+ FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
+ FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
+ l = get_conf_long(d, where + PCI_ERR_COR_STATUS);
+ printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n",
+ FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
+ FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
+ l = get_conf_long(d, where + PCI_ERR_COR_MASK);
+ printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n",
+ FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
+ FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
+ l = get_conf_long(d, where + PCI_ERR_CAP);
+ printf("\t\tAERCap:\tFirst Error Pointer: %02x, GenCap%c CGenEn%c ChkCap%c ChkEn%c\n",
+ PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE),
+ FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE));
+
+}
+
+static void
+cap_acs(struct device *d, int where)
+{
+ u16 w;
+
+ printf("Access Control Services\n");
+ if (!config_fetch(d, where + PCI_ACS_CAP, 4))
+ return;
+
+ w = get_conf_word(d, where + PCI_ACS_CAP);
+ printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
+ "DirectTrans%c\n",
+ FLAG(w, PCI_ACS_CAP_VALID), FLAG(w, PCI_ACS_CAP_BLOCK), FLAG(w, PCI_ACS_CAP_REQ_RED),
+ FLAG(w, PCI_ACS_CAP_CMPLT_RED), FLAG(w, PCI_ACS_CAP_FORWARD), FLAG(w, PCI_ACS_CAP_EGRESS),
+ FLAG(w, PCI_ACS_CAP_TRANS));
+ w = get_conf_word(d, where + PCI_ACS_CTRL);
+ printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
+ "DirectTrans%c\n",
+ FLAG(w, PCI_ACS_CTRL_VALID), FLAG(w, PCI_ACS_CTRL_BLOCK), FLAG(w, PCI_ACS_CTRL_REQ_RED),
+ FLAG(w, PCI_ACS_CTRL_CMPLT_RED), FLAG(w, PCI_ACS_CTRL_FORWARD), FLAG(w, PCI_ACS_CTRL_EGRESS),
+ FLAG(w, PCI_ACS_CTRL_TRANS));
+}
+
+static void
+cap_ari(struct device *d, int where)
+{
+ u16 w;
+
+ printf("Alternative Routing-ID Interpretation (ARI)\n");
+ if (!config_fetch(d, where + PCI_ARI_CAP, 4))
+ return;
+
+ w = get_conf_word(d, where + PCI_ARI_CAP);
+ printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n",
+ FLAG(w, PCI_ARI_CAP_MFVC), FLAG(w, PCI_ARI_CAP_ACS),
+ PCI_ARI_CAP_NFN(w));
+ w = get_conf_word(d, where + PCI_ARI_CTRL);
+ printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n",
+ FLAG(w, PCI_ARI_CTRL_MFVC), FLAG(w, PCI_ARI_CTRL_ACS),
+ PCI_ARI_CTRL_FG(w));
+}
+
+static void
+cap_sriov(struct device *d, int where)
+{
+ u16 b;
+ u16 w;
+ u32 l;
+
+ printf("Single Root I/O Virtualization (SR-IOV)\n");
+ if (!config_fetch(d, where + PCI_IOV_CAP, 0x3c))
+ return;
+
+ l = get_conf_long(d, where + PCI_IOV_CAP);
+ printf("\t\tIOVCap:\tMigration%c, Interrupt Message Number: %03x\n",
+ FLAG(l, PCI_IOV_CAP_VFM), PCI_IOV_CAP_IMN(l));
+ w = get_conf_word(d, where + PCI_IOV_CTRL);
+ printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c\n",
+ FLAG(w, PCI_IOV_CTRL_VFE), FLAG(w, PCI_IOV_CTRL_VFME),
+ FLAG(w, PCI_IOV_CTRL_VFMIE), FLAG(w, PCI_IOV_CTRL_MSE),
+ FLAG(w, PCI_IOV_CTRL_ARI));
+ w = get_conf_word(d, where + PCI_IOV_STATUS);
+ printf("\t\tIOVSta:\tMigration%c\n", FLAG(w, PCI_IOV_STATUS_MS));
+ w = get_conf_word(d, where + PCI_IOV_INITIALVF);
+ printf("\t\tInitial VFs: %d, ", w);
+ w = get_conf_word(d, where + PCI_IOV_TOTALVF);
+ printf("Total VFs: %d, ", w);
+ w = get_conf_word(d, where + PCI_IOV_NUMVF);
+ printf("Number of VFs: %d, ", w);
+ b = get_conf_byte(d, where + PCI_IOV_FDL);
+ printf("Function Dependency Link: %02x\n", b);
+ w = get_conf_word(d, where + PCI_IOV_OFFSET);
+ printf("\t\tVF offset: %d, ", w);
+ w = get_conf_word(d, where + PCI_IOV_STRIDE);
+ printf("stride: %d, ", w);
+ w = get_conf_word(d, where + PCI_IOV_DID);
+ printf("Device ID: %04x\n", w);
+ l = get_conf_long(d, where + PCI_IOV_SUPPS);
+ printf("\t\tSupported Page Size: %08x, ", l);
+ l = get_conf_long(d, where + PCI_IOV_SYSPS);
+ printf("System Page Size: %08x\n", l);
+ printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l),
+ PCI_IOV_MSA_BIR(l));
+}
+
static void
show_ext_caps(struct device *d)
{
switch (id)
{
case PCI_EXT_CAP_ID_AER:
- printf("Advanced Error Reporting <?>\n");
+ cap_aer(d, where);
break;
case PCI_EXT_CAP_ID_VC:
printf("Virtual Channel <?>\n");
printf("Vendor Specific Information <?>\n");
break;
case PCI_EXT_CAP_ID_ACS:
- printf("Access Controls <?>\n");
+ cap_acs(d, where);
+ break;
+ case PCI_EXT_CAP_ID_ARI:
+ cap_ari(d, where);
+ break;
+ case PCI_EXT_CAP_ID_SRIOV:
+ cap_sriov(d, where);
break;
default:
printf("#%02x\n", id);
find_driver(struct device *d, char *buf)
{
struct pci_dev *dev = d->dev;
- char *base = dev->access->method_params[PCI_ACCESS_SYS_BUS_PCI];
- char name[1024], *drv;
+ char name[1024], *drv, *base;
int n;
if (dev->access->method != PCI_ACCESS_SYS_BUS_PCI)
return NULL;
+ base = pci_get_param(dev->access, "sysfs.path");
+ if (!base || !base[0])
+ return NULL;
+
n = snprintf(name, sizeof(name), "%s/devices/%04x:%02x:%02x.%d/driver",
base, dev->domain, dev->bus, dev->dev, dev->func);
if (n < 0 || n >= (int)sizeof(name))
case 'p':
opt_pcimap = optarg;
break;
+#ifdef PCI_OS_LINUX
case 'k':
opt_kernel++;
break;
+#endif
case 'M':
opt_map_mode++;
break;
case 'D':
opt_domains = 2;
break;
+#ifdef PCI_USE_DNS
case 'q':
opt_query_dns++;
break;
case 'Q':
opt_query_all = 1;
break;
+#else
+ case 'q':
+ case 'Q':
+ die("DNS queries are not available in this version");
+#endif
default:
if (parse_generic_option(i, pacc, optarg))
break;
projects / pciutils.git / blobdiff