*
* Copyright (c) 1997--2022 Martin Mares <mj@ucw.cz>
*
- * Can be freely distributed and used under the terms of the GNU GPL.
+ * Can be freely distributed and used under the terms of the GNU GPL v2+.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <stdio.h>
l = get_conf_long(d, where + PCI_ERR_ROOT_STATUS);
printf("\t\tRootSta: CERcvd%c MultCERcvd%c UERcvd%c MultUERcvd%c\n"
- "\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsg %d\n",
+ "\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsgNum %d\n",
FLAG(l, PCI_ERR_ROOT_COR_RCV),
FLAG(l, PCI_ERR_ROOT_MULTI_COR_RCV),
FLAG(l, PCI_ERR_ROOT_UNCOR_RCV),
return;
l = get_conf_word(d, where + PCI_DPC_CAP);
- printf("\t\tDpcCap:\tINT Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
+ printf("\t\tDpcCap:\tIntMsgNum %d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
PCI_DPC_CAP_INT_MSG(l), FLAG(l, PCI_DPC_CAP_RP_EXT), FLAG(l, PCI_DPC_CAP_TLP_BLOCK),
FLAG(l, PCI_DPC_CAP_SW_TRIGGER), PCI_DPC_CAP_RP_LOG(l), FLAG(l, PCI_DPC_CAP_DL_ACT_ERR));
printf("\t\tPRICtl: Enable%c Reset%c\n",
FLAG(w, PCI_PRI_CTRL_ENABLE), FLAG(w, PCI_PRI_CTRL_RESET));
w = get_conf_word(d, where + PCI_PRI_STATUS);
- printf("\t\tPRISta: RF%c UPRGI%c Stopped%c\n",
+ printf("\t\tPRISta: RF%c UPRGI%c Stopped%c PASID%c\n",
FLAG(w, PCI_PRI_STATUS_RF), FLAG(w, PCI_PRI_STATUS_UPRGI),
- FLAG(w, PCI_PRI_STATUS_STOPPED));
+ FLAG(w, PCI_PRI_STATUS_STOPPED), FLAG(w, PCI_PRI_STATUS_PASID));
l = get_conf_long(d, where + PCI_PRI_MAX_REQ);
printf("\t\tPage Request Capacity: %08x, ", l);
l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ);
return;
l = get_conf_long(d, where + PCI_IOV_CAP);
- printf("\t\tIOVCap:\tMigration%c 10BitTagReq%c Interrupt Message Number: %03x\n",
+ printf("\t\tIOVCap:\tMigration%c 10BitTagReq%c IntMsgNum %d\n",
FLAG(l, PCI_IOV_CAP_VFM), FLAG(l, PCI_IOV_CAP_VF_10BIT_TAG_REQ), PCI_IOV_CAP_IMN(l));
w = get_conf_word(d, where + PCI_IOV_CTRL);
printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c 10BitTagReq%c\n",
printf("\t\tAssociatedBusNumbers: %02x-%02x\n", nextbusn, lastbusn );
}
+static void
+cap_lmr(struct device *d, int where)
+{
+ printf("Lane Margining at the Receiver\n");
+
+ if (verbose < 2)
+ return;
+
+ if (!config_fetch(d, where, 8))
+ return;
+
+ u16 port_caps = get_conf_word(d, where + PCI_LMR_CAPS);
+ u16 port_status = get_conf_word(d, where + PCI_LMR_PORT_STS);
+
+ printf("\t\tPortCap: Uses Driver%c\n", FLAG(port_caps, PCI_LMR_CAPS_DRVR));
+ printf("\t\tPortSta: MargReady%c MargSoftReady%c\n",
+ FLAG(port_status, PCI_LMR_PORT_STS_READY),
+ FLAG(port_status, PCI_LMR_PORT_STS_SOFT_READY));
+}
+
static void
cxl_range(u64 base, u64 size, int n)
{
u64 range_base, range_size;
u16 w;
- if (len < 0x38)
- return;
-
/* Legacy 1.1 revs aren't handled */
if (rev == 0)
return;
- if (rev >= 1) {
- w = get_conf_word(d, where + PCI_CXL_DEV_CAP);
- printf("\t\tCXLCap:\tCache%c IO%c Mem%c MemHWInit%c HDMCount %d Viral%c\n",
- FLAG(w, PCI_CXL_DEV_CAP_CACHE), FLAG(w, PCI_CXL_DEV_CAP_IO), FLAG(w, PCI_CXL_DEV_CAP_MEM),
- FLAG(w, PCI_CXL_DEV_CAP_MEM_HWINIT), PCI_CXL_DEV_CAP_HDM_CNT(w), FLAG(w, PCI_CXL_DEV_CAP_VIRAL));
-
- w = get_conf_word(d, where + PCI_CXL_DEV_CTRL);
- printf("\t\tCXLCtl:\tCache%c IO%c Mem%c CacheSFCov %d CacheSFGran %d CacheClean%c Viral%c\n",
- FLAG(w, PCI_CXL_DEV_CTRL_CACHE), FLAG(w, PCI_CXL_DEV_CTRL_IO), FLAG(w, PCI_CXL_DEV_CTRL_MEM),
- PCI_CXL_DEV_CTRL_CACHE_SF_COV(w), PCI_CXL_DEV_CTRL_CACHE_SF_GRAN(w), FLAG(w, PCI_CXL_DEV_CTRL_CACHE_CLN),
- FLAG(w, PCI_CXL_DEV_CTRL_VIRAL));
-
- w = get_conf_word(d, where + PCI_CXL_DEV_STATUS);
- printf("\t\tCXLSta:\tViral%c\n", FLAG(w, PCI_CXL_DEV_STATUS_VIRAL));
-
- w = get_conf_word(d, where + PCI_CXL_DEV_CTRL2);
- printf("\t\tCXLCtl2:\tDisableCaching%c InitCacheWB&Inval%c InitRst%c RstMemClrEn%c",
- FLAG(w, PCI_CXL_DEV_CTRL2_DISABLE_CACHING),
- FLAG(w, PCI_CXL_DEV_CTRL2_INIT_WB_INVAL),
- FLAG(w, PCI_CXL_DEV_CTRL2_INIT_CXL_RST),
- FLAG(w, PCI_CXL_DEV_CTRL2_INIT_CXL_RST_CLR_EN));
- if (rev >= 2) {
- printf(" DesiredVolatileHDMStateAfterHotReset%c", FLAG(w, PCI_CXL_DEV_CTRL2_INIT_CXL_HDM_STATE_HOTRST));
+ if (rev >= 1 && len >= PCI_CXL_DEV_LEN)
+ {
+ w = get_conf_word(d, where + PCI_CXL_DEV_CAP);
+ printf("\t\tCXLCap:\tCache%c IO%c Mem%c MemHWInit%c HDMCount %d Viral%c\n",
+ FLAG(w, PCI_CXL_DEV_CAP_CACHE), FLAG(w, PCI_CXL_DEV_CAP_IO), FLAG(w, PCI_CXL_DEV_CAP_MEM),
+ FLAG(w, PCI_CXL_DEV_CAP_MEM_HWINIT), PCI_CXL_DEV_CAP_HDM_CNT(w), FLAG(w, PCI_CXL_DEV_CAP_VIRAL));
+
+ w = get_conf_word(d, where + PCI_CXL_DEV_CTRL);
+ printf("\t\tCXLCtl:\tCache%c IO%c Mem%c CacheSFCov %d CacheSFGran %d CacheClean%c Viral%c\n",
+ FLAG(w, PCI_CXL_DEV_CTRL_CACHE), FLAG(w, PCI_CXL_DEV_CTRL_IO), FLAG(w, PCI_CXL_DEV_CTRL_MEM),
+ PCI_CXL_DEV_CTRL_CACHE_SF_COV(w), PCI_CXL_DEV_CTRL_CACHE_SF_GRAN(w), FLAG(w, PCI_CXL_DEV_CTRL_CACHE_CLN),
+ FLAG(w, PCI_CXL_DEV_CTRL_VIRAL));
+
+ w = get_conf_word(d, where + PCI_CXL_DEV_STATUS);
+ printf("\t\tCXLSta:\tViral%c\n", FLAG(w, PCI_CXL_DEV_STATUS_VIRAL));
+
+ w = get_conf_word(d, where + PCI_CXL_DEV_CTRL2);
+ printf("\t\tCXLCtl2:\tDisableCaching%c InitCacheWB&Inval%c InitRst%c RstMemClrEn%c",
+ FLAG(w, PCI_CXL_DEV_CTRL2_DISABLE_CACHING),
+ FLAG(w, PCI_CXL_DEV_CTRL2_INIT_WB_INVAL),
+ FLAG(w, PCI_CXL_DEV_CTRL2_INIT_CXL_RST),
+ FLAG(w, PCI_CXL_DEV_CTRL2_INIT_CXL_RST_CLR_EN));
+ if (rev >= 2)
+ printf(" DesiredVolatileHDMStateAfterHotReset%c", FLAG(w, PCI_CXL_DEV_CTRL2_INIT_CXL_HDM_STATE_HOTRST));
+ printf("\n");
+
+ w = get_conf_word(d, where + PCI_CXL_DEV_STATUS2);
+ printf("\t\tCXLSta2:\tResetComplete%c ResetError%c PMComplete%c\n",
+ FLAG(w, PCI_CXL_DEV_STATUS_RC), FLAG(w,PCI_CXL_DEV_STATUS_RE), FLAG(w, PCI_CXL_DEV_STATUS_PMC));
+
+ w = get_conf_word(d, where + PCI_CXL_DEV_CAP2);
+ printf("\t\tCXLCap2:\t");
+ cache_unit_size = BITS(w, 0, 4);
+ cache_size = BITS(w, 8, 8);
+ switch (cache_unit_size)
+ {
+ case PCI_CXL_DEV_CAP2_CACHE_1M:
+ printf("Cache Size: %08x\n", cache_size * (1<<20));
+ break;
+ case PCI_CXL_DEV_CAP2_CACHE_64K:
+ printf("Cache Size: %08x\n", cache_size * (64<<10));
+ break;
+ case PCI_CXL_DEV_CAP2_CACHE_UNK:
+ printf("Cache Size Not Reported\n");
+ break;
+ default:
+ printf("Cache Size: %d of unknown unit size (%d)\n", cache_size, cache_unit_size);
+ break;
+ }
+
+ range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_HI) << 32;
+ range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_LO);
+ range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_HI) << 32;
+ range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_LO);
+ cxl_range(range_base, range_size, 1);
+
+ range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_HI) << 32;
+ range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_LO);
+ range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_HI) << 32;
+ range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_LO);
+ cxl_range(range_base, range_size, 2);
}
- printf("\n");
-
- w = get_conf_word(d, where + PCI_CXL_DEV_STATUS2);
- printf("\t\tCXLSta2:\tResetComplete%c ResetError%c PMComplete%c\n",
- FLAG(w, PCI_CXL_DEV_STATUS_RC), FLAG(w,PCI_CXL_DEV_STATUS_RE), FLAG(w, PCI_CXL_DEV_STATUS_PMC));
-
- w = get_conf_word(d, where + PCI_CXL_DEV_CAP2);
- printf("\t\tCXLCap2:\t");
- cache_unit_size = BITS(w, 0, 4);
- cache_size = BITS(w, 8, 8);
- switch (cache_unit_size)
- {
- case PCI_CXL_DEV_CAP2_CACHE_1M:
- printf("Cache Size: %08x\n", cache_size * (1<<20));
- break;
- case PCI_CXL_DEV_CAP2_CACHE_64K:
- printf("Cache Size: %08x\n", cache_size * (64<<10));
- break;
- case PCI_CXL_DEV_CAP2_CACHE_UNK:
- printf("Cache Size Not Reported\n");
- break;
- default:
- printf("Cache Size: %d of unknown unit size (%d)\n", cache_size, cache_unit_size);
- break;
- }
-
- range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_HI) << 32;
- range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_LO);
- range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_HI) << 32;
- range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_LO);
- cxl_range(range_base, range_size, 1);
-
- range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_HI) << 32;
- range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_LO);
- range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_HI) << 32;
- range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_LO);
- cxl_range(range_base, range_size, 2);
- }
- if (rev >= 2) {
- w = get_conf_word(d, where + PCI_CXL_DEV_CAP3);
- printf("\t\tCXLCap3:\tDefaultVolatile HDM State After:\tColdReset%c WarmReset%c HotReset%c HotResetConfigurability%c\n",
- FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_COLD),
- FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_WARM),
- FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT),
- FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT_CFG));
- }
+ if (rev >= 2 && len >= PCI_CXL_DEV_LEN_REV2)
+ {
+ w = get_conf_word(d, where + PCI_CXL_DEV_CAP3);
+ printf("\t\tCXLCap3:\tDefaultVolatile HDM State After:\tColdReset%c WarmReset%c HotReset%c HotResetConfigurability%c\n",
+ FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_COLD),
+ FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_WARM),
+ FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT),
+ FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT_CFG));
+ }
// Unparsed data
- if (len > PCI_CXL_DEV_LEN) {
+ if (len > PCI_CXL_DEV_LEN_REV2)
printf("\t\t<?>\n");
- }
-
}
static void
// Sanity check: Does the length correspond to its revision?
switch (rev) {
case 0:
- if (len != PCI_CXL_FB_MOD_TS_DATA) {
+ if (len != PCI_CXL_FB_MOD_TS_DATA)
printf("\t\t<Wrong length for Revision %d>\n", rev);
- }
break;
case 1:
- if (len != PCI_CXL_FB_PORT_CAP2) {
+ if (len != PCI_CXL_FB_PORT_CAP2)
printf("\t\t<Wrong length for Revision %d>\n", rev);
- }
break;
case 2:
- if (len != PCI_CXL_FB_NEXT_UNSUPPORTED) {
+ if (len != PCI_CXL_FB_NEXT_UNSUPPORTED)
printf("\t\t<Wrong length for Revision %d>\n", rev);
- }
break;
default:
break;
// From Rev 1
if (rev >= 1)
- {
- l = get_conf_long(d, where + PCI_CXL_FB_MOD_TS_DATA);
- data = BITS(l, 0, 24);
- printf("\t\tFBModTS:\tReceived FB Data: %06x\n", (unsigned int)data);
- }
+ {
+ l = get_conf_long(d, where + PCI_CXL_FB_MOD_TS_DATA);
+ data = BITS(l, 0, 24);
+ printf("\t\tFBModTS:\tReceived FB Data: %06x\n", (unsigned int)data);
+ }
// From Rev 2
if (rev >= 2)
- {
- u8 nop;
+ {
+ u8 nop;
- l = get_conf_long(d, where + PCI_CXL_FB_PORT_CAP2);
- printf("\t\tFBCap2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CAP2_NOP_HINT));
+ l = get_conf_long(d, where + PCI_CXL_FB_PORT_CAP2);
+ printf("\t\tFBCap2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CAP2_NOP_HINT));
- l = get_conf_long(d, where + PCI_CXL_FB_PORT_CTRL2);
- printf("\t\tFBCtl2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CTRL2_NOP_HINT));
+ l = get_conf_long(d, where + PCI_CXL_FB_PORT_CTRL2);
+ printf("\t\tFBCtl2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CTRL2_NOP_HINT));
- l = get_conf_long(d, where + PCI_CXL_FB_PORT_STATUS2);
- nop = BITS(l, 0, 2);
- printf("\t\tFBSta2:\tNOPHintInfo: %x\n", nop);
- }
+ l = get_conf_long(d, where + PCI_CXL_FB_PORT_STATUS2);
+ nop = BITS(l, 0, 2);
+ printf("\t\tFBSta2:\tNOPHintInfo: %x\n", nop);
+ }
// Unparsed data
- if (len > PCI_CXL_FB_LEN) {
+ if (len > PCI_CXL_FB_LEN)
printf("\t\t<?>\n");
- }
}
static void
buff = get_conf_long(d, where + 4);
printf("\t\tPTMCap: ");
- printf("Requester:%c Responder:%c Root:%c\n",
+ printf("Requester%c Responder%c Root%c\n",
FLAG(buff, 0x1),
FLAG(buff, 0x2),
FLAG(buff, 0x4));
buff = get_conf_long(d, where + 8);
printf("\t\tPTMControl: ");
- printf("Enabled:%c RootSelected:%c\n",
+ printf("Enabled%c RootSelected%c\n",
FLAG(buff, 0x1),
FLAG(buff, 0x2));
printf("\t\tDOECap: IntSup%c\n",
FLAG(l, PCI_DOE_CAP_INT_SUPP));
if (l & PCI_DOE_CAP_INT_SUPP)
- printf("\t\t\tInterrupt Message Number %03x\n",
+ printf("\t\t\tIntMsgNum %d\n",
PCI_DOE_CAP_INT_MSG(l));
l = get_conf_long(d, where + PCI_DOE_CTL);
printf("Physical Layer 16.0 GT/s <?>\n");
break;
case PCI_EXT_CAP_ID_LMR:
- printf("Lane Margining at the Receiver <?>\n");
+ cap_lmr(d, where);
break;
case PCI_EXT_CAP_ID_HIER_ID:
printf("Hierarchy ID <?>\n");
case PCI_EXT_CAP_ID_NPEM:
printf("Native PCIe Enclosure Management <?>\n");
break;
+ case PCI_EXT_CAP_ID_32GT:
+ printf("Physical Layer 32.0 GT/s <?>\n");
+ break;
case PCI_EXT_CAP_ID_DOE:
cap_doe(d, where);
break;
projects / pciutils.git / blobdiff