printf("\t\tAssociatedBusNumbers: %02x-%02x\n", nextbusn, lastbusn );
}
+static void
+cap_lmr(struct device *d, int where)
+{
+ printf("Lane Margining at the Receiver\n");
+
+ if (verbose < 2)
+ return;
+
+ if (!config_fetch(d, where, 8))
+ return;
+
+ u16 port_caps = get_conf_word(d, where + PCI_LMR_CAPS);
+ u16 port_status = get_conf_word(d, where + PCI_LMR_PORT_STS);
+
+ printf("\t\tPortCap: Uses Driver%c\n", FLAG(port_caps, PCI_LMR_CAPS_DRVR));
+ printf("\t\tPortSta: MargReady%c MargSoftReady%c\n",
+ FLAG(port_status, PCI_LMR_PORT_STS_READY),
+ FLAG(port_status, PCI_LMR_PORT_STS_SOFT_READY));
+}
+
static void
cxl_range(u64 base, u64 size, int n)
{
u64 range_base, range_size;
u16 w;
- if (len < 0x38)
- return;
-
/* Legacy 1.1 revs aren't handled */
if (rev == 0)
return;
- if (rev >= 1)
+ if (rev >= 1 && len >= PCI_CXL_DEV_LEN)
{
w = get_conf_word(d, where + PCI_CXL_DEV_CAP);
printf("\t\tCXLCap:\tCache%c IO%c Mem%c MemHWInit%c HDMCount %d Viral%c\n",
cxl_range(range_base, range_size, 2);
}
- if (rev >= 2)
+ if (rev >= 2 && len >= PCI_CXL_DEV_LEN_REV2)
{
w = get_conf_word(d, where + PCI_CXL_DEV_CAP3);
printf("\t\tCXLCap3:\tDefaultVolatile HDM State After:\tColdReset%c WarmReset%c HotReset%c HotResetConfigurability%c\n",
}
// Unparsed data
- if (len > PCI_CXL_DEV_LEN)
+ if (len > PCI_CXL_DEV_LEN_REV2)
printf("\t\t<?>\n");
}
printf("Physical Layer 16.0 GT/s <?>\n");
break;
case PCI_EXT_CAP_ID_LMR:
- printf("Lane Margining at the Receiver <?>\n");
+ cap_lmr(d, where);
break;
case PCI_EXT_CAP_ID_HIER_ID:
printf("Hierarchy ID <?>\n");