/*
* The PCI Utilities -- Show Extended Capabilities
*
- * Copyright (c) 1997--2020 Martin Mares <mj@ucw.cz>
+ * Copyright (c) 1997--2022 Martin Mares <mj@ucw.cz>
*
* Can be freely distributed and used under the terms of the GNU GPL.
*/
pat_pos = BITS(rcap, 24, 8);
printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n",
pat_pos,
- BITS(rcap, 16, 6) + 1,
+ BITS(rcap, 16, 7) + 1,
FLAG(rcap, 1 << 15));
printf("\t\t\tArb:");
}
static void
-dvsec_cxl_device(struct device *d, int where, int rev)
+dvsec_cxl_device(struct device *d, int rev, int where, int len)
{
- u32 cache_size, cache_unit_size, l;
+ u32 cache_size, cache_unit_size;
u64 range_base, range_size;
u16 w;
+ if (len < PCI_CXL_DEV_LEN)
+ return;
+
/* Legacy 1.1 revs aren't handled */
if (rev < 1)
return;
break;
}
- l = get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_HI);
- range_size = (u64) l << 32;
- l = get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_LO);
- range_size |= l;
- l = get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_HI);
- range_base = (u64) l << 32;
- l = get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_LO);
- range_base |= l;
+ range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_HI) << 32;
+ range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_LO);
+ range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_HI) << 32;
+ range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_LO);
cxl_range(range_base, range_size, 1);
- l = get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_HI);
- range_size = (u64) l << 32;
- l = get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_LO);
- range_size |= l;
- l = get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_HI);
- range_base = (u64) l << 32;
- l = get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_LO);
- range_base |= l;
+ range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_HI) << 32;
+ range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_LO);
+ range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_HI) << 32;
+ range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_LO);
cxl_range(range_base, range_size, 2);
}
static void
-cap_dvsec_cxl(struct device *d, int id, int where)
+dvsec_cxl_port(struct device *d, int where, int len)
{
- u8 rev;
+ u16 w, m1, m2;
+ u8 b1, b2;
- printf(": CXL\n");
- if (verbose < 2)
+ if (len < PCI_CXL_PORT_EXT_LEN)
return;
- if (id != 0)
- return;
+ w = get_conf_word(d, where + PCI_CXL_PORT_EXT_STATUS);
+ printf("\t\tCXLPortSta:\tPMComplete%c\n", FLAG(w, PCI_CXL_PORT_EXT_STATUS));
+
+ w = get_conf_word(d, where + PCI_CXL_PORT_CTRL);
+ printf("\t\tCXLPortCtl:\tUnmaskSBR%c UnmaskLinkDisable%c AltMem%c AltBME%c ViralEnable%c\n",
+ FLAG(w, PCI_CXL_PORT_UNMASK_SBR), FLAG(w, PCI_CXL_PORT_UNMASK_LINK),
+ FLAG(w, PCI_CXL_PORT_ALT_MEMORY), FLAG(w, PCI_CXL_PORT_ALT_BME),
+ FLAG(w, PCI_CXL_PORT_VIRAL_EN));
+
+ b1 = get_conf_byte(d, where + PCI_CXL_PORT_ALT_BUS_BASE);
+ b2 = get_conf_byte(d, where + PCI_CXL_PORT_ALT_BUS_LIMIT);
+ printf("\t\tAlternateBus:\t%02x-%02x\n", b1, b2);
+ m1 = get_conf_word(d, where + PCI_CXL_PORT_ALT_MEM_BASE);
+ m2 = get_conf_word(d, where + PCI_CXL_PORT_ALT_MEM_LIMIT);
+ printf("\t\tAlternateBus:\t%04x-%04x\n", m1, m2);
+}
+
+static void
+dvsec_cxl_register_locator(struct device *d, int where, int len)
+{
+ static const char * const id_names[] = {
+ "empty",
+ "component registers",
+ "BAR virtualization",
+ "CXL device registers",
+ "CPMU registers",
+ };
+
+ for (int i=0; ; i++)
+ {
+ int pos = where + PCI_CXL_RL_BLOCK1_LO + 8*i;
+ if (pos + 7 >= where + len)
+ break;
- rev = BITS(get_conf_byte(d, where + 0x6), 0, 4);
+ u32 lo = get_conf_long(d, pos);
+ u32 hi = get_conf_long(d, pos + 4);
+
+ unsigned int bir = BITS(lo, 0, 3);
+ unsigned int block_id = BITS(lo, 8, 8);
+ u64 base = (BITS(lo, 16, 16) << 16) | ((u64) hi << 32);
+
+ if (!block_id)
+ continue;
- if (!config_fetch(d, where, PCI_CXL_DEV_LEN))
+ const char *id_name;
+ if (block_id < sizeof(id_names) / sizeof(*id_names))
+ id_name = id_names[block_id];
+ else if (block_id == 0xff)
+ id_name = "vendor-specific";
+ else
+ id_name = "<?>";
+
+ printf("\t\tBlock%d: BIR: bar%d, ID: %s, offset: %016" PCI_U64_FMT_X "\n", i + 1, bir, id_name, base);
+ }
+}
+
+static void
+cap_dvsec_cxl(struct device *d, int id, int rev, int where, int len)
+{
+ printf(": CXL\n");
+ if (verbose < 2)
+ return;
+
+ if (!config_fetch(d, where, len))
return;
- dvsec_cxl_device(d, where, rev);
+ switch (id)
+ {
+ case 0:
+ dvsec_cxl_device(d, rev, where, len);
+ break;
+ case 2:
+ printf("\t\tNon-CXL Function Map DVSEC\n");
+ break;
+ case 3:
+ dvsec_cxl_port(d, where, len);
+ break;
+ case 4:
+ printf("\t\tGPF DVSEC for Port\n");
+ break;
+ case 5:
+ printf("\t\tGPF DVSEC for Device\n");
+ break;
+ case 7:
+ printf("\t\tPCIe DVSEC Flex Bus Port\n");
+ break;
+ case 8:
+ dvsec_cxl_register_locator(d, where, len);
+ break;
+ case 9:
+ printf("\t\tMLD DVSEC\n");
+ break;
+ default:
+ printf("\t\tUnknown ID %04x\n", id);
+ }
}
static void
printf("Vendor=%04x ID=%04x Rev=%d Len=%d", vendor, id, rev, len);
if (vendor == PCI_DVSEC_VENDOR_ID_CXL && len >= 16)
- cap_dvsec_cxl(d, id, where);
+ cap_dvsec_cxl(d, id, rev, where, len);
else
printf(" <?>\n");
}