/*
* The PCI Utilities -- Show Capabilities
*
- * Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz>
+ * Copyright (c) 1997--2018 Martin Mares <mj@ucw.cz>
*
* Can be freely distributed and used under the terms of the GNU GPL.
*/
FLAG(cap, PCI_PM_CAP_DSI),
FLAG(cap, PCI_PM_CAP_D1),
FLAG(cap, PCI_PM_CAP_D2),
- pm_aux_current[(cap >> 6) & 7],
+ pm_aux_current[(cap & PCI_PM_CAP_AUX_C_MASK) >> 6],
FLAG(cap, PCI_PM_CAP_PME_D0),
FLAG(cap, PCI_PM_CAP_PME_D1),
FLAG(cap, PCI_PM_CAP_PME_D2),
1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
- ((status >> 8) & 0xff),
- ((status >> 3) & 0x1f),
+ (status & PCI_PCIX_STATUS_BUS) >> 8,
+ (status & PCI_PCIX_STATUS_DEVICE) >> 3,
(status & PCI_PCIX_STATUS_FUNCTION),
FLAG(status, PCI_PCIX_STATUS_64BIT),
FLAG(status, PCI_PCIX_STATUS_133MHZ),
FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
- 1 << (9 + ((status >> 21) & 3U)),
- max_outstanding[(status >> 23) & 7U],
- 1 << (3 + ((status >> 26) & 7U)),
+ 1 << (9 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT) >> 21)),
+ max_outstanding[(status & PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS) >> 23],
+ 1 << (3 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE) >> 26)),
FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
FLAG(status, PCI_PCIX_STATUS_266MHZ),
FLAG(status, PCI_PCIX_STATUS_533MHZ));
FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
- sec_clock_freq[(secstatus >> 6) & 7]);
+ sec_clock_freq[(secstatus & PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ) >> 6]);
status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
- ((status >> 8) & 0xff),
- ((status >> 3) & 0x1f),
+ (status & PCI_PCIX_BRIDGE_STATUS_BUS) >> 8,
+ (status & PCI_PCIX_BRIDGE_STATUS_DEVICE) >> 3,
(status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
printf("\n");
w = get_conf_word(d, where + PCI_EXP_DEVCTL);
- printf("\t\tDevCtl:\tReport errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
+ printf("\t\tDevCtl:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c\n",
FLAG(w, PCI_EXP_DEVCTL_CERE),
FLAG(w, PCI_EXP_DEVCTL_NFERE),
FLAG(w, PCI_EXP_DEVCTL_FERE),
128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
w = get_conf_word(d, where + PCI_EXP_DEVSTA);
- printf("\t\tDevSta:\tCorrErr%c UncorrErr%c FatalErr%c UnsuppReq%c AuxPwr%c TransPend%c\n",
+ printf("\t\tDevSta:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c AuxPwr%c TransPend%c\n",
FLAG(w, PCI_EXP_DEVSTA_CED),
FLAG(w, PCI_EXP_DEVSTA_NFED),
FLAG(w, PCI_EXP_DEVSTA_FED),
}
}
+static char *link_compare(int sta, int cap)
+{
+ if (sta < cap)
+ return "downgraded";
+ if (sta > cap)
+ return "strange";
+ return "ok";
+}
+
static char *aspm_support(int code)
{
switch (code)
static void cap_express_link(struct device *d, int where, int type)
{
- u32 t;
+ u32 t, aspm, cap_speed, cap_width, sta_speed, sta_width;
u16 w;
t = get_conf_long(d, where + PCI_EXP_LNKCAP);
- printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s, Exit Latency L0s %s, L1 %s\n",
+ aspm = (t & PCI_EXP_LNKCAP_ASPM) >> 10;
+ cap_speed = t & PCI_EXP_LNKCAP_SPEED;
+ cap_width = (t & PCI_EXP_LNKCAP_WIDTH) >> 4;
+ printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s",
t >> 24,
- link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
- aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
- latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
- latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
+ link_speed(cap_speed), cap_width,
+ aspm_support(aspm));
+ if (aspm)
+ {
+ printf(", Exit Latency ");
+ if (aspm & 1)
+ printf("L0s %s", latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12));
+ if (aspm & 2)
+ printf("%sL1 %s", (aspm & 1) ? ", " : "",
+ latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
+ }
+ printf("\n");
printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c\n",
FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
w = get_conf_word(d, where + PCI_EXP_LNKSTA);
- printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
- link_speed(w & PCI_EXP_LNKSTA_SPEED),
- (w & PCI_EXP_LNKSTA_WIDTH) >> 4,
+ sta_speed = w & PCI_EXP_LNKSTA_SPEED;
+ sta_width = (w & PCI_EXP_LNKSTA_WIDTH) >> 4;
+ printf("\t\tLnkSta:\tSpeed %s (%s), Width x%d (%s)\n",
+ link_speed(sta_speed),
+ link_compare(sta_speed, cap_speed),
+ sta_width,
+ link_compare(sta_width, cap_width));
+ printf("\t\t\tTrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
FLAG(w, PCI_EXP_LNKSTA_TRAIN),
FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
FLAG(t, PCI_EXP_SLTCAP_HPC),
FLAG(t, PCI_EXP_SLTCAP_HPS));
printf("\t\t\tSlot #%d, PowerLimit %.3fW; Interlock%c NoCompl%c\n",
- t >> 19,
+ (t & PCI_EXP_SLTCAP_PSN) >> 19,
power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
printf("\t\tRootCap: CRSVisible%c\n",
FLAG(w, PCI_EXP_RTCAP_CRSVIS));
- w = get_conf_word(d, where + PCI_EXP_RTSTA);
+ w = get_conf_long(d, where + PCI_EXP_RTSTA);
printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
w & PCI_EXP_RTSTA_PME_REQID,
FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
{
u32 l;
u16 w;
- int has_mem_bar = 0;
+ int has_mem_bar = device_has_memory_space_bar(d);
- has_mem_bar = device_has_memory_space_bar(d);
l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s",
cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)),
if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
type == PCI_EXP_TYPE_DOWNSTREAM || has_mem_bar)
{
- printf("\t\tAtomicOpsCap:");
+ printf("\t\t\t AtomicOpsCap:");
if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
type == PCI_EXP_TYPE_DOWNSTREAM)
printf(" Routing%c", FLAG(l, PCI_EXP_DEVCAP2_ATOMICOP_ROUTING));
type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ENDPOINT ||
type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
{
- printf("\t\tAtomicOpsCtl:");
+ printf("\t\t\t AtomicOpsCtl:");
if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT ||
type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
printf(" ReqEn%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_REQUESTER_EN));
/* No capabilities that require this field in PCIe rev2.0 spec. */
}
-static void
+static int
cap_express(struct device *d, int where, int cap)
{
int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
printf("PCI-Express to PCI/PCI-X Bridge");
break;
case PCI_EXP_TYPE_PCIE_BRIDGE:
- printf("PCI/PCI-X to PCI-Express Bridge");
+ slot = cap & PCI_EXP_FLAGS_SLOT;
+ printf("PCI/PCI-X to PCI-Express Bridge (Slot%c)",
+ FLAG(cap, PCI_EXP_FLAGS_SLOT));
break;
case PCI_EXP_TYPE_ROOT_INT_EP:
link = 0;
}
printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
if (verbose < 2)
- return;
+ return type;
size = 16;
if (slot)
if (type == PCI_EXP_TYPE_ROOT_PORT)
size = 32;
if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
- return;
+ return type;
cap_express_dev(d, where, type);
if (link)
cap_express_root(d, where);
if ((cap & PCI_EXP_FLAGS_VERS) < 2)
- return;
+ return type;
size = 16;
if (slot)
size = 24;
if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size))
- return;
+ return type;
cap_express_dev2(d, where, type);
if (link)
cap_express_link2(d, where, type);
if (slot)
cap_express_slot2(d, where);
+ return type;
}
static void
show_caps(struct device *d, int where)
{
int can_have_ext_caps = 0;
+ int type = -1;
if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
{
printf("Secure device <?>\n");
break;
case PCI_CAP_ID_EXP:
- cap_express(d, where, cap);
+ type = cap_express(d, where, cap);
can_have_ext_caps = 1;
break;
case PCI_CAP_ID_MSIX:
}
}
if (can_have_ext_caps)
- show_ext_caps(d);
+ show_ext_caps(d, type);
}
projects / pciutils.git / blobdiff