Released 3.1.7.

[pciutils.git] / ls-caps.c

diff --git a/ls-caps.c b/ls-caps.c
index 8b0f8204d4ec52dd230aaf56fb01d650d301014f..a4bf713cac7b8e1a12e75fcfc88768c5a400ed3e 100644 (file)
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -1,7 +1,7 @@
 /*
  *     The PCI Utilities -- Show Capabilities
  *
- *     Copyright (c) 1997--2008 Martin Mares <mj@ucw.cz>
+ *     Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz>
  *
  *     Can be freely distributed and used under the terms of the GNU GPL.
  */
@@ -34,8 +34,9 @@ cap_pm(struct device *d, int where, int cap)
   if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
     return;
   t = get_conf_word(d, where + PCI_PM_CTRL);
-  printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
+  printf("\t\tStatus: D%d NoSoftRst%c PME-Enable%c DSel=%d DScale=%d PME%c\n",
         t & PCI_PM_CTRL_STATE_MASK,
+        FLAG(t, PCI_PM_CTRL_NO_SOFT_RST),
         FLAG(t, PCI_PM_CTRL_PME_ENABLE),
         (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
         (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
@@ -590,12 +591,12 @@ cap_msi(struct device *d, int where, int cap)
   u32 t;
   u16 w;
 
-  printf("MSI: Mask%c 64bit%c Count=%d/%d Enable%c\n",
-         FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
-        FLAG(cap, PCI_MSI_FLAGS_64BIT),
+  printf("MSI: Enable%c Count=%d/%d Maskable%c 64bit%c\n",
+        FLAG(cap, PCI_MSI_FLAGS_ENABLE),
         1 << ((cap & PCI_MSI_FLAGS_QSIZE) >> 4),
         1 << ((cap & PCI_MSI_FLAGS_QMASK) >> 1),
-        FLAG(cap, PCI_MSI_FLAGS_ENABLE));
+        FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
+        FLAG(cap, PCI_MSI_FLAGS_64BIT));
   if (verbose < 2)
     return;
   is64 = cap & PCI_MSI_FLAGS_64BIT;
@@ -673,7 +674,7 @@ static void cap_express_dev(struct device *d, int where, int type)
        FLAG(t, PCI_EXP_DEVCAP_RBE),
        FLAG(t, PCI_EXP_DEVCAP_FLRESET));
   if (type == PCI_EXP_TYPE_UPSTREAM)
-    printf("SlotPowerLimit %fW",
+    printf("SlotPowerLimit %.3fW",
        power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
                    (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
   printf("\n");
@@ -797,7 +798,7 @@ static void cap_express_slot(struct device *d, int where)
   u16 w;
 
   t = get_conf_long(d, where + PCI_EXP_SLTCAP);
-  printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surpise%c\n",
+  printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c\n",
        FLAG(t, PCI_EXP_SLTCAP_ATNB),
        FLAG(t, PCI_EXP_SLTCAP_PWRC),
        FLAG(t, PCI_EXP_SLTCAP_MRL),
@@ -805,7 +806,7 @@ static void cap_express_slot(struct device *d, int where)
        FLAG(t, PCI_EXP_SLTCAP_PWRI),
        FLAG(t, PCI_EXP_SLTCAP_HPC),
        FLAG(t, PCI_EXP_SLTCAP_HPS));
-  printf("\t\t\tSlot #%3x, PowerLimit %f; Interlock%c NoCompl%c\n",
+  printf("\t\t\tSlot #%d, PowerLimit %.3fW; Interlock%c NoCompl%c\n",
        t >> 19,
        power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
        FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
@@ -1094,10 +1095,10 @@ cap_msix(struct device *d, int where, int cap)
 {
   u32 off;
 
-  printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
+  printf("MSI-X: Enable%c Count=%d Masked%c\n",
         FLAG(cap, PCI_MSIX_ENABLE),
-        FLAG(cap, PCI_MSIX_MASK),
-        (cap & PCI_MSIX_TABSIZE) + 1);
+        (cap & PCI_MSIX_TABSIZE) + 1,
+        FLAG(cap, PCI_MSIX_MASK));
   if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
     return;
 
@@ -1145,6 +1146,47 @@ cap_debug_port(int cap)
   printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
 }
 
+static void
+cap_af(struct device *d, int where)
+{
+  u8 reg;
+
+  printf("PCI Advanced Features\n");
+  if (verbose < 2 || !config_fetch(d, where + PCI_AF_CAP, 3))
+    return;
+
+  reg = get_conf_byte(d, where + PCI_AF_CAP);
+  printf("\t\tAFCap: TP%c FLR%c\n", FLAG(reg, PCI_AF_CAP_TP),
+        FLAG(reg, PCI_AF_CAP_FLR));
+  reg = get_conf_byte(d, where + PCI_AF_CTRL);
+  printf("\t\tAFCtrl: FLR%c\n", FLAG(reg, PCI_AF_CTRL_FLR));
+  reg = get_conf_byte(d, where + PCI_AF_STATUS);
+  printf("\t\tAFStatus: TP%c\n", FLAG(reg, PCI_AF_STATUS_TP));
+}
+
+static void
+cap_sata_hba(struct device *d, int where, int cap)
+{
+  u32 bars;
+  int bar;
+
+  printf("SATA HBA v%d.%d", BITS(cap, 4, 4), BITS(cap, 0, 4));
+  if (verbose < 2 || !config_fetch(d, where + PCI_SATA_HBA_BARS, 4))
+    {
+      printf("\n");
+      return;
+    }
+
+  bars = get_conf_long(d, where + PCI_SATA_HBA_BARS);
+  bar = BITS(bars, 0, 4);
+  if (bar >= 4 && bar <= 9)
+    printf(" BAR%d Offset=%08x\n", bar - 4, BITS(bars, 4, 20));
+  else if (bar == 15)
+    printf(" InCfgSpace\n");
+  else
+    printf(" BAR??%d\n", bar);
+}
+
 void
 show_caps(struct device *d)
 {
@@ -1206,7 +1248,7 @@ show_caps(struct device *d)
              cap_ht(d, where, cap);
              break;
            case PCI_CAP_ID_VNDR:
-             printf("Vendor Specific Information <?>\n");
+             printf("Vendor Specific Information: Len=%02x <?>\n", BITS(cap, 0, 8));
              break;
            case PCI_CAP_ID_DBG:
              cap_debug_port(cap);
@@ -1234,10 +1276,10 @@ show_caps(struct device *d)
              cap_msix(d, where, cap);
              break;
            case PCI_CAP_ID_SATA:
-             printf("SATA HBA <?>\n");
+             cap_sata_hba(d, where, cap);
              break;
            case PCI_CAP_ID_AF:
-             printf("PCIe advanced features <?>\n");
+             cap_af(d, where);
              break;
            default:
              printf("#%02x [%04x]\n", id, cap);