CXL: Fix Flex Bus DVSEC cap

[pciutils.git] / ls-caps.c

diff --git a/ls-caps.c b/ls-caps.c
index b0caa50943d69619a2b9e000e692661112a9b03b..a481b16b8578a9e717954be8629c07244d15e04b 100644 (file)
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -44,8 +44,8 @@ cap_pm(struct device *d, int where, int cap)
   b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
   if (b)
     printf("\t\tBridge: PM%c B3%c\n",
-          FLAG(t, PCI_PM_BPCC_ENABLE),
-          FLAG(~t, PCI_PM_PPB_B2_B3));
+          FLAG(b, PCI_PM_BPCC_ENABLE),
+          FLAG(~b, PCI_PM_PPB_B2_B3));
 }
 
 static void
@@ -659,18 +659,16 @@ static int exp_downstream_port(int type)
 static void show_power_limit(int value, int scale)
 {
   static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
-  static const int scale0_values[3] = { 250, 275, 300 };
 
-  if (scale == 0 && value >= 0xF0)
+  if (scale == 0 && value == 0xFF)
     {
-      /* F3h to FFh = Reserved for Slot Power Limit values above 300 W */
-      if (value >= 0xF3)
-        {
-          printf(">300W");
-          return;
-        }
-      value = scale0_values[value - 0xF0];
+      printf(">600W");
+      return;
     }
+
+  if (scale == 0 && value >= 0xF0 && value <= 0xFE)
+    value = 250 + 25 * (value - 0xF0);
+
   printf("%gW", value * scales[scale]);
 }
 
@@ -1085,7 +1083,7 @@ device_has_memory_space_bar(struct device *d)
   int i, found = 0;
 
   for (i=0; i<6; i++)
-    if (p->base_addr[i] && p->size[i])
+    if (p->base_addr[i] || p->size[i])
       {
         if (!(p->base_addr[i] & PCI_BASE_ADDRESS_SPACE_IO))
           {