/*
* The PCI Utilities -- Show Capabilities
*
- * Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz>
+ * Copyright (c) 1997--2018 Martin Mares <mj@ucw.cz>
*
* Can be freely distributed and used under the terms of the GNU GPL.
*/
{
u16 lctr0, lcnf0, lctr1, lcnf1, eh;
u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
- char *fmt;
printf("HyperTransport: Slave or Primary Interface\n");
if (verbose < 2)
if (rid < 0x22 && rid > 0x11)
printf("\t\t!!! Possibly incomplete decoding\n");
- if (rid >= 0x22)
- fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
- else
- fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
- printf(fmt,
+ printf("\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c",
(cmd & PCI_HT_PRI_CMD_BUID),
(cmd & PCI_HT_PRI_CMD_UC) >> 5,
FLAG(cmd, PCI_HT_PRI_CMD_MH),
- FLAG(cmd, PCI_HT_PRI_CMD_DD),
- FLAG(cmd, PCI_HT_PRI_CMD_DUL));
- lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
+ FLAG(cmd, PCI_HT_PRI_CMD_DD));
if (rid >= 0x22)
- fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
- else
- fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
- printf(fmt,
+ printf(" DUL%c", FLAG(cmd, PCI_HT_PRI_CMD_DUL));
+ printf("\n");
+
+ lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
+ printf("\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x",
FLAG(lctr0, PCI_HT_LCTR_CFLE),
FLAG(lctr0, PCI_HT_LCTR_CST),
FLAG(lctr0, PCI_HT_LCTR_CFE),
FLAG(lctr0, PCI_HT_LCTR_INIT),
FLAG(lctr0, PCI_HT_LCTR_EOC),
FLAG(lctr0, PCI_HT_LCTR_TXO),
- (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
- FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
- FLAG(lctr0, PCI_HT_LCTR_LSEN),
- FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
- FLAG(lctr0, PCI_HT_LCTR_64B));
- lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
+ (lctr0 & PCI_HT_LCTR_CRCERR) >> 8);
if (rid >= 0x22)
- fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
+ printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c",
+ FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
+ FLAG(lctr0, PCI_HT_LCTR_LSEN),
+ FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
+ FLAG(lctr0, PCI_HT_LCTR_64B));
+ printf("\n");
+
+ lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
+ if (rid < 0x22)
+ printf("\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n",
+ ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
+ ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
+ ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
+ ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12));
else
- fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
- printf(fmt,
- ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
- ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
- ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
- ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
- FLAG(lcnf0, PCI_HT_LCNF_DFI),
- FLAG(lcnf0, PCI_HT_LCNF_DFO),
- FLAG(lcnf0, PCI_HT_LCNF_DFIE),
- FLAG(lcnf0, PCI_HT_LCNF_DFOE));
+ printf("\t\tLink Config 0: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
+ ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
+ FLAG(lcnf0, PCI_HT_LCNF_DFI),
+ ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
+ FLAG(lcnf0, PCI_HT_LCNF_DFO),
+ ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
+ FLAG(lcnf0, PCI_HT_LCNF_DFIE),
+ ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
+ FLAG(lcnf0, PCI_HT_LCNF_DFOE));
+
lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
- if (rid >= 0x22)
- fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
- else
- fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
- printf(fmt,
+ printf("\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x",
FLAG(lctr1, PCI_HT_LCTR_CFLE),
FLAG(lctr1, PCI_HT_LCTR_CST),
FLAG(lctr1, PCI_HT_LCTR_CFE),
FLAG(lctr1, PCI_HT_LCTR_INIT),
FLAG(lctr1, PCI_HT_LCTR_EOC),
FLAG(lctr1, PCI_HT_LCTR_TXO),
- (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
+ (lctr1 & PCI_HT_LCTR_CRCERR) >> 8);
+ if (rid >= 0x22)
+ printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c",
FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
FLAG(lctr1, PCI_HT_LCTR_LSEN),
FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
FLAG(lctr1, PCI_HT_LCTR_64B));
+ printf("\n");
+
lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
- if (rid >= 0x22)
- fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
+ if (rid < 0x22)
+ printf("\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n",
+ ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
+ ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
+ ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
+ ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12));
else
- fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
- printf(fmt,
- ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
- ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
- ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
- ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
- FLAG(lcnf1, PCI_HT_LCNF_DFI),
- FLAG(lcnf1, PCI_HT_LCNF_DFO),
- FLAG(lcnf1, PCI_HT_LCNF_DFIE),
- FLAG(lcnf1, PCI_HT_LCNF_DFOE));
+ printf("\t\tLink Config 1: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
+ ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
+ FLAG(lcnf1, PCI_HT_LCNF_DFI),
+ ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
+ FLAG(lcnf1, PCI_HT_LCNF_DFO),
+ ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
+ FLAG(lcnf1, PCI_HT_LCNF_DFIE),
+ ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
+ FLAG(lcnf1, PCI_HT_LCNF_DFOE));
+
printf("\t\tRevision ID: %u.%02u\n",
(rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
if (rid < 0x22)
return;
+
lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
FLAG(lfrer0, PCI_HT_LFRER_OV),
FLAG(lfrer0, PCI_HT_LFRER_EOC),
FLAG(lfrer0, PCI_HT_LFRER_CTLT));
+
lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
FLAG(lfcap0, PCI_HT_LFCAP_200),
FLAG(lfcap0, PCI_HT_LFCAP_1400),
FLAG(lfcap0, PCI_HT_LFCAP_1600),
FLAG(lfcap0, PCI_HT_LFCAP_VEND));
+
ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
FLAG(ftr, PCI_HT_FTR_ISOCFC),
FLAG(ftr, PCI_HT_FTR_ECTLT),
FLAG(ftr, PCI_HT_FTR_64BA),
FLAG(ftr, PCI_HT_FTR_UIDRD));
+
lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
FLAG(lfrer1, PCI_HT_LFRER_OV),
FLAG(lfrer1, PCI_HT_LFRER_EOC),
FLAG(lfrer1, PCI_HT_LFRER_CTLT));
+
lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
FLAG(lfcap1, PCI_HT_LFCAP_200),
FLAG(lfcap1, PCI_HT_LFCAP_1400),
FLAG(lfcap1, PCI_HT_LFCAP_1600),
FLAG(lfcap1, PCI_HT_LFCAP_VEND));
+
eh = get_conf_word(d, where + PCI_HT_PRI_EH);
printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
FLAG(eh, PCI_HT_EH_PFLE),
FLAG(eh, PCI_HT_EH_RNFE),
FLAG(eh, PCI_HT_EH_CRCNFE),
FLAG(eh, PCI_HT_EH_SERRNFE));
+
mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
+
bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
printf("\t\tBus Number: %02x\n", bn);
}
}
}
+static char *link_compare(int sta, int cap)
+{
+ if (sta < cap)
+ return "downgraded";
+ if (sta > cap)
+ return "strange";
+ return "ok";
+}
+
static char *aspm_support(int code)
{
switch (code)
static void cap_express_link(struct device *d, int where, int type)
{
- u32 t, aspm;
+ u32 t, aspm, cap_speed, cap_width, sta_speed, sta_width;
u16 w;
t = get_conf_long(d, where + PCI_EXP_LNKCAP);
aspm = (t & PCI_EXP_LNKCAP_ASPM) >> 10;
+ cap_speed = t & PCI_EXP_LNKCAP_SPEED;
+ cap_width = (t & PCI_EXP_LNKCAP_WIDTH) >> 4;
printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s",
t >> 24,
- link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
+ link_speed(cap_speed), cap_width,
aspm_support(aspm));
if (aspm)
{
FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
w = get_conf_word(d, where + PCI_EXP_LNKSTA);
- printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
- link_speed(w & PCI_EXP_LNKSTA_SPEED),
- (w & PCI_EXP_LNKSTA_WIDTH) >> 4,
+ sta_speed = w & PCI_EXP_LNKSTA_SPEED;
+ sta_width = (w & PCI_EXP_LNKSTA_WIDTH) >> 4;
+ printf("\t\tLnkSta:\tSpeed %s (%s), Width x%d (%s)\n",
+ link_speed(sta_speed),
+ link_compare(sta_speed, cap_speed),
+ sta_width,
+ link_compare(sta_width, cap_width));
+ printf("\t\t\tTrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
FLAG(w, PCI_EXP_LNKSTA_TRAIN),
FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
}
switch (id)
{
+ case PCI_CAP_ID_NULL:
+ printf("Null\n");
+ break;
case PCI_CAP_ID_PM:
cap_pm(d, where, cap);
break;
cap_ea(d, where, cap);
break;
default:
- printf("#%02x [%04x]\n", id, cap);
+ printf("Capability ID %#02x [%04x]\n", id, cap);
}
where = next;
}
projects / pciutils.git / blobdiff