Released as 3.1.4.

[pciutils.git] / ls-caps.c

diff --git a/ls-caps.c b/ls-caps.c
index 0a19d4773e7be9d0dc05f718519f5246038722da..634dadce4e84834c80cd6cecbb9fee4637439108 100644 (file)
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -34,8 +34,9 @@ cap_pm(struct device *d, int where, int cap)
   if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
     return;
   t = get_conf_word(d, where + PCI_PM_CTRL);
-  printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
+  printf("\t\tStatus: D%d NoSoftRst%c PME-Enable%c DSel=%d DScale=%d PME%c\n",
         t & PCI_PM_CTRL_STATE_MASK,
+        FLAG(t, PCI_PM_CTRL_NO_SOFT_RST),
         FLAG(t, PCI_PM_CTRL_PME_ENABLE),
         (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
         (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
@@ -590,12 +591,12 @@ cap_msi(struct device *d, int where, int cap)
   u32 t;
   u16 w;
 
-  printf("MSI: Mask%c 64bit%c Count=%d/%d Enable%c\n",
-         FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
-        FLAG(cap, PCI_MSI_FLAGS_64BIT),
+  printf("MSI: Enable%c Count=%d/%d Maskable%c 64bit%c\n",
+        FLAG(cap, PCI_MSI_FLAGS_ENABLE),
         1 << ((cap & PCI_MSI_FLAGS_QSIZE) >> 4),
         1 << ((cap & PCI_MSI_FLAGS_QMASK) >> 1),
-        FLAG(cap, PCI_MSI_FLAGS_ENABLE));
+        FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
+        FLAG(cap, PCI_MSI_FLAGS_64BIT));
   if (verbose < 2)
     return;
   is64 = cap & PCI_MSI_FLAGS_64BIT;
@@ -752,7 +753,7 @@ static void cap_express_link(struct device *d, int where, int type)
        aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
        latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
        latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
-  printf("\t\t\tClockPM%c Suprise%c LLActRep%c BwNot%c\n",
+  printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c\n",
        FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
        FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
        FLAG(t, PCI_EXP_LNKCAP_DLLA),
@@ -1094,10 +1095,10 @@ cap_msix(struct device *d, int where, int cap)
 {
   u32 off;
 
-  printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
+  printf("MSI-X: Enable%c Count=%d Masked%c\n",
         FLAG(cap, PCI_MSIX_ENABLE),
-        FLAG(cap, PCI_MSIX_MASK),
-        (cap & PCI_MSIX_TABSIZE) + 1);
+        (cap & PCI_MSIX_TABSIZE) + 1,
+        FLAG(cap, PCI_MSIX_MASK));
   if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
     return;
 
@@ -1145,6 +1146,24 @@ cap_debug_port(int cap)
   printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
 }
 
+static void
+cap_af(struct device *d, int where)
+{
+  u8 reg;
+
+  printf("PCI Advanced Features\n");
+  if (verbose < 2 || !config_fetch(d, where + PCI_AF_CAP, 3))
+    return;
+
+  reg = get_conf_byte(d, where + PCI_AF_CAP);
+  printf("\t\tAFCap: TP%c FLR%c\n", FLAG(reg, PCI_AF_CAP_TP),
+        FLAG(reg, PCI_AF_CAP_FLR));
+  reg = get_conf_byte(d, where + PCI_AF_CTRL);
+  printf("\t\tAFCtrl: FLR%c\n", FLAG(reg, PCI_AF_CTRL_FLR));
+  reg = get_conf_byte(d, where + PCI_AF_STATUS);
+  printf("\t\tAFStatus: TP%c\n", FLAG(reg, PCI_AF_STATUS_TP));
+}
+
 void
 show_caps(struct device *d)
 {
@@ -1237,7 +1256,7 @@ show_caps(struct device *d)
              printf("SATA HBA <?>\n");
              break;
            case PCI_CAP_ID_AF:
-             printf("PCIe advanced features <?>\n");
+             cap_af(d, where);
              break;
            default:
              printf("#%02x [%04x]\n", id, cap);