u32 t;
u16 w;
- printf("MSI: Mask%c 64bit%c Count=%d/%d Enable%c\n",
- FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
- FLAG(cap, PCI_MSI_FLAGS_64BIT),
+ printf("MSI: Enable%c Count=%d/%d Maskable%c 64bit%c\n",
+ FLAG(cap, PCI_MSI_FLAGS_ENABLE),
1 << ((cap & PCI_MSI_FLAGS_QSIZE) >> 4),
1 << ((cap & PCI_MSI_FLAGS_QMASK) >> 1),
- FLAG(cap, PCI_MSI_FLAGS_ENABLE));
+ FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
+ FLAG(cap, PCI_MSI_FLAGS_64BIT));
if (verbose < 2)
return;
is64 = cap & PCI_MSI_FLAGS_64BIT;
u16 w;
t = get_conf_long(d, where + PCI_EXP_SLTCAP);
- printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surpise%c\n",
+ printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c\n",
FLAG(t, PCI_EXP_SLTCAP_ATNB),
FLAG(t, PCI_EXP_SLTCAP_PWRC),
FLAG(t, PCI_EXP_SLTCAP_MRL),
{
u32 off;
- printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
+ printf("MSI-X: Enable%c Count=%d Masked%c\n",
FLAG(cap, PCI_MSIX_ENABLE),
- FLAG(cap, PCI_MSIX_MASK),
- (cap & PCI_MSIX_TABSIZE) + 1);
+ (cap & PCI_MSIX_TABSIZE) + 1,
+ FLAG(cap, PCI_MSIX_MASK));
if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
return;
printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
}
+static void
+cap_af(struct device *d, int where)
+{
+ u8 reg;
+
+ printf("PCI Advanced Features\n");
+ if (verbose < 2 || !config_fetch(d, where + PCI_AF_CAP, 3))
+ return;
+
+ reg = get_conf_byte(d, where + PCI_AF_CAP);
+ printf("\t\tAFCap: TP%c FLR%c\n", FLAG(reg, PCI_AF_CAP_TP),
+ FLAG(reg, PCI_AF_CAP_FLR));
+ reg = get_conf_byte(d, where + PCI_AF_CTRL);
+ printf("\t\tAFCtrl: FLR%c\n", FLAG(reg, PCI_AF_CTRL_FLR));
+ reg = get_conf_byte(d, where + PCI_AF_STATUS);
+ printf("\t\tAFStatus: TP%c\n", FLAG(reg, PCI_AF_STATUS_TP));
+}
+
void
show_caps(struct device *d)
{
printf("SATA HBA <?>\n");
break;
case PCI_CAP_ID_AF:
- printf("PCIe advanced features <?>\n");
+ cap_af(d, where);
break;
default:
printf("#%02x [%04x]\n", id, cap);