Merge remote-tracking branch 'pali/i386-io-windows'

[pciutils.git] / lib / header.h

diff --git a/lib/header.h b/lib/header.h
index 33ed2be7866690cde4f4ec5e6c321e4f75aa205f..e74f6d80e8c00c22b1636e50f7fd76aceb6bb8dd 100644 (file)
--- a/lib/header.h
+++ b/lib/header.h
@@ -537,7 +537,7 @@
 #define PCI_HT_SEC_CMD         2       /* Command Register */
 #define  PCI_HT_SEC_CMD_WR     0x0001  /* Warm Reset */
 #define  PCI_HT_SEC_CMD_DE     0x0002  /* Double-Ended */
-#define  PCI_HT_SEC_CMD_DN     0x0076  /* Device Number */
+#define  PCI_HT_SEC_CMD_DN     0x007c  /* Device Number */
 #define  PCI_HT_SEC_CMD_CS     0x0080  /* Chain Side */
 #define  PCI_HT_SEC_CMD_HH     0x0100  /* Host Hide */
 #define  PCI_HT_SEC_CMD_AS     0x0400  /* Act as Slave */
@@ -1127,12 +1127,7 @@
 #define PCI_CXL_PORT_ALT_MEM_LIMIT 0x12
 
 /* PCIe CXL 2.0 Designated Vendor-Specific Capabilities for Register Locator */
-#define PCI_CXL_RL_BASE0_LO 0x0c
-#define PCI_CXL_RL_BASE0_HI 0x10
-#define PCI_CXL_RL_BASE1_LO 0x14
-#define PCI_CXL_RL_BASE1_HI 0x18
-#define PCI_CXL_RL_BASE2_LO 0x1c
-#define PCI_CXL_RL_BASE2_HI 0x20
+#define PCI_CXL_RL_BLOCK1_LO 0x0c
 
 /* Access Control Services */
 #define PCI_ACS_CAP            0x04    /* ACS Capability Register */
@@ -1295,7 +1290,7 @@
 #define  PCI_L1PM_SUBSTAT_CAP_PM_L11   0x2     /* PCI-PM L1.1 Supported */
 #define  PCI_L1PM_SUBSTAT_CAP_ASPM_L12 0x4     /* ASPM L1.2 Supported */
 #define  PCI_L1PM_SUBSTAT_CAP_ASPM_L11 0x8     /* ASPM L1.1 Supported */
-#define  PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP        0x16    /* L1 PM Substates supported */
+#define  PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP        0x10    /* L1 PM Substates supported */
 #define PCI_L1PM_SUBSTAT_CTL1  0x8     /* L1 PM Substate Control 1 */
 #define  PCI_L1PM_SUBSTAT_CTL1_PM_L12  0x1     /* PCI-PM L1.2 Enable */
 #define  PCI_L1PM_SUBSTAT_CTL1_PM_L11  0x2     /* PCI-PM L1.1 Enable */