lspci: Decode PCIe DevCap/DevCtl FLReset only for Endpoints

[pciutils.git] / lib / header.h

diff --git a/lib/header.h b/lib/header.h
index d481f276919e6df1d3666625a60ded8a27343c2e..660800375fcbd539fc033161fd5ae29c9b792ef6 100644 (file)
--- a/lib/header.h
+++ b/lib/header.h
@@ -144,7 +144,8 @@
 #define  PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN 0x800    /* PCI-X? */
 
 /* Header type 2 (CardBus bridges) */
-/* 0x14-0x15 reserved */
+#define PCI_CB_CAPABILITY_LIST 0x14
+/* 0x15 reserved */
 #define PCI_CB_SEC_STATUS      0x16    /* Secondary status */
 #define PCI_CB_PRIMARY_BUS     0x18    /* PCI bus number */
 #define PCI_CB_CARD_BUS                0x19    /* CardBus bus number */
@@ -225,6 +226,7 @@
 #define PCI_EXT_CAP_ID_SRIOV   0x10    /* Single Root I/O Virtualization */
 #define PCI_EXT_CAP_ID_TPH     0x17    /* Transaction processing hints */
 #define PCI_EXT_CAP_ID_LTR     0x18    /* Latency Tolerance Reporting */
+#define PCI_EXT_CAP_ID_L1PM    0x1e    /* L1 PM Substates */
 
 /*** Definitions of capabilities ***/
 
@@ -845,11 +847,15 @@
 #define  PCI_EXP_RTSTA_PME_STATUS  0x00010000 /* PME Status */
 #define  PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
 #define PCI_EXP_DEVCAP2                        0x24    /* Device capabilities 2 */
+#define  PCI_EXP_DEVCAP2_LTR           0x0800  /* LTR supported */
+#define  PCI_EXP_DEVCAP2_OBFF(x)       (((x) >> 18) & 3) /* OBFF supported */
 #define PCI_EXP_DEVCTL2                        0x28    /* Device Control */
 #define  PCI_EXP_DEV2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ranges Supported */
 #define  PCI_EXP_DEV2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Value */
 #define  PCI_EXP_DEV2_TIMEOUT_DIS      0x0010  /* Completion Timeout Disable Supported */
 #define  PCI_EXP_DEV2_ARI              0x0020  /* ARI Forwarding */
+#define  PCI_EXP_DEV2_LTR              0x0400  /* LTR enabled */
+#define  PCI_EXP_DEV2_OBFF(x)          (((x) >> 13) & 3) /* OBFF enabled */
 #define PCI_EXP_DEVSTA2                        0x2a    /* Device Status */
 #define PCI_EXP_LNKCAP2                        0x2c    /* Link Capabilities */
 #define PCI_EXP_LNKCTL2                        0x30    /* Link Control */
@@ -860,9 +866,14 @@
 #define  PCI_EXP_LNKCTL2_MARGIN(x)     (((x) >> 7) & 7) /* Transmit Margin */
 #define  PCI_EXP_LNKCTL2_MOD_CMPLNC    0x0400  /* Enter Modified Compliance */
 #define  PCI_EXP_LNKCTL2_CMPLNC_SOS    0x0800  /* Compliance SOS */
-#define  PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 1) /* Compliance De-emphasis */
+#define  PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 0xf) /* Compliance De-emphasis */
 #define PCI_EXP_LNKSTA2                        0x32    /* Link Status */
 #define  PCI_EXP_LINKSTA2_DEEMPHASIS(x)        ((x) & 1)       /* Current De-emphasis Level */
+#define  PCI_EXP_LINKSTA2_EQU_COMP     0x02    /* Equalization Complete */
+#define  PCI_EXP_LINKSTA2_EQU_PHASE1   0x04    /* Equalization Phase 1 Successful */
+#define  PCI_EXP_LINKSTA2_EQU_PHASE2   0x08    /* Equalization Phase 2 Successful */
+#define  PCI_EXP_LINKSTA2_EQU_PHASE3   0x10    /* Equalization Phase 3 Successful */
+#define  PCI_EXP_LINKSTA2_EQU_REQ      0x20    /* Link Equalization Request */
 #define PCI_EXP_SLTCAP2                        0x34    /* Slot Capabilities */
 #define PCI_EXP_SLTCTL2                        0x38    /* Slot Control */
 #define PCI_EXP_SLTSTA2                        0x3a    /* Slot Status */