#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
#define PCI_EXT_CAP_ID_TPH 0x17 /* Transaction processing hints */
#define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */
+#define PCI_EXT_CAP_ID_L1PM 0x1e /* L1 PM Substates */
/*** Definitions of capabilities ***/