Avoid unsupported printf format attribute when building with gcc2 (required for BeOS).

[pciutils.git] / lib / header.h

diff --git a/lib/header.h b/lib/header.h
index 24b569e16c3e75deab4baa4a35b564253346cfd8..5d285c2385e886129e883e6a8c7f7d9224220605 100644 (file)
--- a/lib/header.h
+++ b/lib/header.h
@@ -1,7 +1,7 @@
 /*
  *     The PCI Library -- PCI Header Structure (based on <linux/pci.h>)
  *
- *     Copyright (c) 1997--2007 Martin Mares <mj@ucw.cz>
+ *     Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz>
  *
  *     Can be freely distributed and used under the terms of the GNU GPL.
  */
@@ -216,6 +216,7 @@
 #define PCI_EXT_CAP_ID_RCILINK 0x06    /* Root Complex Internal Link Declaration */
 #define PCI_EXT_CAP_ID_RCECOLL 0x07    /* Root Complex Event Collector */
 #define PCI_EXT_CAP_ID_MFVC    0x08    /* Multi-Function Virtual Channel */
+#define PCI_EXT_CAP_ID_VC2     0x09    /* Virtual Channel (2nd ID) */
 #define PCI_EXT_CAP_ID_RBCB    0x0a    /* Root Bridge Control Block */
 #define PCI_EXT_CAP_ID_VNDR    0x0b    /* Vendor specific */
 #define PCI_EXT_CAP_ID_ACS     0x0d    /* Access Controls */
@@ -223,6 +224,8 @@
 #define PCI_EXT_CAP_ID_ATS     0x0f    /* Address Translation Service */
 #define PCI_EXT_CAP_ID_SRIOV   0x10    /* Single Root I/O Virtualization */
 
+/*** Definitions of capabilities ***/
+
 /* Power Management Registers */
 
 #define  PCI_PM_CAP_VER_MASK   0x0007  /* Version (2=PM1.1) */
@@ -238,6 +241,7 @@
 #define  PCI_PM_CAP_PME_D3_COLD        0x8000  /* PME can be asserted from D3cold */
 #define PCI_PM_CTRL            4       /* PM control and status register */
 #define  PCI_PM_CTRL_STATE_MASK        0x0003  /* Current power state (D0 to D3) */
+#define  PCI_PM_CTRL_NO_SOFT_RST       0x0008  /* No Soft Reset from D3hot to D0 */
 #define  PCI_PM_CTRL_PME_ENABLE        0x0100  /* PME pin enable */
 #define  PCI_PM_CTRL_DATA_SEL_MASK     0x1e00  /* PM table data index */
 #define  PCI_PM_CTRL_DATA_SCALE_MASK   0x6000  /* PM table data scaling factor */
@@ -708,6 +712,9 @@
 #define PCI_HT_RM_CNT1         10      /* Retry Count 1 Register */
 #define PCI_HT_RM_SIZEOF       12
 
+/* Vendor-Specific Capability (see PCI_EVNDR_xxx for the PCIe version) */
+#define PCI_VNDR_LENGTH                2       /* Length byte */
+
 /* PCI Express */
 #define PCI_EXP_FLAGS          0x2     /* Capabilities register */
 #define PCI_EXP_FLAGS_VERS     0x000f  /* Capability version */
@@ -861,7 +868,7 @@
 /* MSI-X */
 #define  PCI_MSIX_ENABLE       0x8000
 #define  PCI_MSIX_MASK         0x4000
-#define  PCI_MSIX_TABSIZE      0x03ff
+#define  PCI_MSIX_TABSIZE      0x07ff
 #define PCI_MSIX_TABLE         4
 #define PCI_MSIX_PBA           8
 #define  PCI_MSIX_BIR          0x7
@@ -870,6 +877,21 @@
 #define PCI_SSVID_VENDOR       4
 #define PCI_SSVID_DEVICE       6
 
+/* PCI Advanced Features */
+#define PCI_AF_CAP             3
+#define  PCI_AF_CAP_TP         0x01
+#define  PCI_AF_CAP_FLR                0x02
+#define PCI_AF_CTRL            4
+#define  PCI_AF_CTRL_FLR       0x01
+#define PCI_AF_STATUS          5
+#define  PCI_AF_STATUS_TP      0x01
+
+/* SATA Host Bus Adapter */
+#define PCI_SATA_HBA_BARS      4
+#define PCI_SATA_HBA_REG0      8
+
+/*** Definitions of extended capabilities ***/
+
 /* Advanced Error Reporting */
 #define PCI_ERR_UNCOR_STATUS   4       /* Uncorrectable Error Status */
 #define  PCI_ERR_UNC_TRAIN     0x00000001      /* Undefined in PCIe rev1.1 & 2.0 spec */
@@ -931,6 +953,17 @@
 #define PCI_PWR_CAP            12      /* Capability */
 #define  PCI_PWR_CAP_BUDGET(x) ((x) & 1)       /* Included in system budget */
 
+/* Root Complex Link */
+#define PCI_RCLINK_ESD         4       /* Element Self Description */
+#define PCI_RCLINK_LINK1       16      /* First Link Entry */
+#define  PCI_RCLINK_LINK_DESC  0       /* Link Entry: Description */
+#define  PCI_RCLINK_LINK_ADDR  8       /* Link Entry: Address (64-bit) */
+#define  PCI_RCLINK_LINK_SIZE  16      /* Link Entry: sizeof */
+
+/* PCIe Vendor-Specific Capability */
+#define PCI_EVNDR_HEADER       4       /* Vendor-Specific Header */
+#define PCI_EVNDR_REGISTERS    8       /* Vendor-Specific Registers */
+
 /* Access Control Services */
 #define PCI_ACS_CAP            0x04    /* ACS Capability Register */
 #define PCI_ACS_CAP_VALID      0x0001  /* ACS Source Validation */