libpci: ecam: Fix big address range mappings

[pciutils.git] / lib / header.h

diff --git a/lib/header.h b/lib/header.h
index 57ef0ae8a31e9a7c521f7fc029981c2f52598a5f..2bace9357f3fea3e817c2f537b70c8f8cc0f6f67 100644 (file)
--- a/lib/header.h
+++ b/lib/header.h
@@ -903,9 +903,13 @@
 #define  PCI_EXP_DEVCTL2_ARI           0x0020  /* ARI Forwarding */
 #define  PCI_EXP_DEVCTL2_ATOMICOP_REQUESTER_EN 0x0040  /* AtomicOp RequesterEnable */
 #define  PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK 0x0080  /* AtomicOp Egress Blocking */
+#define  PCI_EXP_DEVCTL2_IDO_REQ_EN    0x0100  /* Allow IDO for requests */
+#define  PCI_EXP_DEVCTL2_IDO_CMP_EN    0x0200  /* Allow IDO for completions */
 #define  PCI_EXP_DEVCTL2_LTR           0x0400  /* LTR enabled */
+#define  PCI_EXP_DEVCTL2_EPR_REQ       0x0800  /* Emergency Power Reduction Request */
 #define  PCI_EXP_DEVCTL2_10BIT_TAG_REQ 0x1000 /* 10 Bit Tag Requester enabled */
 #define  PCI_EXP_DEVCTL2_OBFF(x)               (((x) >> 13) & 3) /* OBFF enabled */
+#define  PCI_EXP_DEVCTL2_EE_TLP_BLK    0x8000  /* End-End TLP Prefix Blocking */
 #define PCI_EXP_DEVSTA2                        0x2a    /* Device Status */
 #define PCI_EXP_LNKCAP2                        0x2c    /* Link Capabilities */
 #define  PCI_EXP_LNKCAP2_SPEED(x)      (((x) >> 1) & 0x7f)
@@ -1072,7 +1076,7 @@
 #define PCI_DVSEC_ID_CXL       0       /* Designated Vendor-Specific ID for Intel CXL */
 
 /* PCIe CXL Designated Vendor-Specific Capabilities for Devices: Control, Status */
-#define PCI_CXL_DEV_LEN 0x38 /* CXL Device DVSEC Length */
+#define PCI_CXL_DEV_LEN 0x3c /* CXL Device DVSEC Length */
 #define PCI_CXL_DEV_CAP                        0x0a    /* CXL Capability Register */
 #define  PCI_CXL_DEV_CAP_CACHE         0x0001  /* CXL.cache Protocol Support */
 #define  PCI_CXL_DEV_CAP_IO            0x0002  /* CXL.io Protocol Support */
@@ -1090,6 +1094,12 @@
 #define  PCI_CXL_DEV_CTRL_VIRAL                0x4000  /* CXL Viral Handling Enable */
 #define PCI_CXL_DEV_STATUS             0x0e    /* CXL Status Register */
 #define  PCI_CXL_DEV_STATUS_VIRAL      0x4000  /* CXL Viral Handling Status */
+#define PCI_CXL_DEV_CTRL2              0x10    /* CXL Control Register 2 */
+#define  PCI_CXL_DEV_CTRL2_DISABLE_CACHING            0x0001
+#define  PCI_CXL_DEV_CTRL2_INIT_WB_INVAL              0x0002
+#define  PCI_CXL_DEV_CTRL2_INIT_CXL_RST               0x0003
+#define  PCI_CXL_DEV_CTRL2_INIT_CXL_RST_CLR_EN        0x0004
+#define  PCI_CXL_DEV_CTRL2_INIT_CXL_HDM_STATE_HOTRST  0x0005
 #define PCI_CXL_DEV_STATUS2            0x12
 #define  PCI_CXL_DEV_STATUS_CACHE_INV  0x0001
 #define  PCI_CXL_DEV_STATUS_RC         0x0002  /* Device Reset Complete */
@@ -1113,6 +1123,13 @@
 #define PCI_CXL_DEV_RANGE2_SIZE_LO     0x2c
 #define PCI_CXL_DEV_RANGE2_BASE_HI     0x30
 #define PCI_CXL_DEV_RANGE2_BASE_LO     0x34
+/* From Rev2 */
+#define PCI_CXL_DEV_CAP3  0x38
+#define  PCI_CXL_DEV_CAP3_HDM_STATE_RST_COLD     0x0001
+#define  PCI_CXL_DEV_CAP3_HDM_STATE_RST_WARM     0x0002
+#define  PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT      0x0003
+#define  PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT_CFG  0x0004
+
 
 /* PCIe CXL 2.0 Designated Vendor-Specific Capabilities for Ports */
 #define PCI_CXL_PORT_EXT_LEN 0x28 /* CXL Extensions DVSEC for Ports Length */
@@ -1195,6 +1212,7 @@
 #define PCI_CXL_FB_PORT_CTRL2               0x18    /* CXL Flex Bus Port Control2 Register */
 #define  PCI_CXL_FB_CTRL2_NOP_HINT          0x01    /* NOP Hint Enable */
 #define PCI_CXL_FB_PORT_STATUS2             0x1c    /* CXL Flex Bus Port Status2 Register */
+#define PCI_CXL_FB_NEXT_UNSUPPORTED         0x20
 
 /* PCIe CXL Designated Vendor-Specific Capabilities for Multi-Logical Device */
 #define PCI_CXL_MLD_LEN     0x10
@@ -1301,9 +1319,10 @@
 #define  PCI_PRI_CTRL_ENABLE   0x01    /* Enable */
 #define  PCI_PRI_CTRL_RESET    0x02    /* Reset */
 #define PCI_PRI_STATUS         0x06    /* PRI status register */
-#define  PCI_PRI_STATUS_RF     0x001   /* Response Failure */
-#define  PCI_PRI_STATUS_UPRGI  0x002   /* Unexpected PRG index */
-#define  PCI_PRI_STATUS_STOPPED        0x100   /* PRI Stopped */
+#define  PCI_PRI_STATUS_RF     0x0001  /* Response Failure */
+#define  PCI_PRI_STATUS_UPRGI  0x0002  /* Unexpected PRG index */
+#define  PCI_PRI_STATUS_STOPPED        0x0100  /* PRI Stopped */
+#define  PCI_PRI_STATUS_PASID  0x8000  /* PASID required in PRG response */
 #define PCI_PRI_MAX_REQ                0x08    /* PRI max reqs supported */
 #define PCI_PRI_ALLOC_REQ      0x0c    /* PRI max reqs allowed */