#define PCI_EXT_CAP_ID_TPH 0x17 /* Transaction processing hints */
#define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */
#define PCI_EXT_CAP_ID_PASID 0x1b /* Process Address Space ID */
+#define PCI_EXT_CAP_ID_DPC 0x1d /* Downstream Port Containment */
#define PCI_EXT_CAP_ID_L1PM 0x1e /* L1 PM Substates */
+#define PCI_EXT_CAP_ID_PTM 0x1f /* Precision Time Measurement */
/*** Definitions of capabilities ***/
#define PCI_EXP_DEV2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ranges Supported */
#define PCI_EXP_DEV2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Value */
#define PCI_EXP_DEV2_TIMEOUT_DIS 0x0010 /* Completion Timeout Disable Supported */
+#define PCI_EXP_DEV2_ATOMICOP_REQUESTER_EN 0x0040 /* AtomicOp RequesterEnable */
+#define PCI_EXP_DEV2_ATOMICOP_EGRESS_BLOCK 0x0080 /* AtomicOp Egress Blocking */
#define PCI_EXP_DEV2_ARI 0x0020 /* ARI Forwarding */
+#define PCI_EXP_DEVCAP2_ATOMICOP_ROUTING 0x0040 /* AtomicOp Routing Supported */
+#define PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP 0x0080 /* 32bit AtomicOp Completer Supported */
+#define PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP 0x0100 /* 64bit AtomicOp Completer Supported */
+#define PCI_EXP_DEVCAP2_128BIT_CAS_COMP 0x0200 /* 128bit CAS Completer Supported */
#define PCI_EXP_DEV2_LTR 0x0400 /* LTR enabled */
#define PCI_EXP_DEV2_OBFF(x) (((x) >> 13) & 3) /* OBFF enabled */
#define PCI_EXP_DEVSTA2 0x2a /* Device Status */
#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
+#define PCI_ERR_CAP_MULT_HDRC 0x00000200 /* Multiple Header Capable */
+#define PCI_ERR_CAP_MULT_HDRE 0x00000400 /* Multiple Header Enable */
+#define PCI_ERR_CAP_TLP_PFX 0x00000800 /* TLP Prefix Log Present */
+#define PCI_ERR_CAP_HDR_LOG 0x00001000 /* Completion Timeout Prefix/Header Log Capable */
#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
-#define PCI_ERR_ROOT_STATUS 48
+#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Error Reporting Enable */
+#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Error Reporting Enable*/
+#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Error Reporting Enable */
+#define PCI_ERR_ROOT_STATUS 48 /* Root Error Status */
+#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */
+#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 /* Multiple ERR_COR Received */
+#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 /* ERR_FATAL/NONFATAL Received */
+#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 /* Multiple ERR_FATAL/NONFATAL Received */
+#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Uncorrectable Fatal */
+#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Error Messages Received */
+#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Error Messages Received */
+#define PCI_ERR_MSG_NUM(x) (((x) >> 27) & 0x1f) /* MSI/MSI-X vector */
#define PCI_ERR_ROOT_COR_SRC 52
#define PCI_ERR_ROOT_SRC 54
#define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */
#define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */
#define PCI_PASID_CTRL_PRIV 0x04 /* Privilege Mode Enable */
+
+#define PCI_DPC_CAP 4 /* DPC Capability */
+#define PCI_DPC_CAP_INT_MSG(x) ((x) & 0x1f) /* DPC Interrupt Message Number */
+#define PCI_DPC_CAP_RP_EXT 0x20 /* DPC Root Port Extentions */
+#define PCI_DPC_CAP_TLP_BLOCK 0x40 /* DPC Poisoned TLP Egress Blocking */
+#define PCI_DPC_CAP_SW_TRIGGER 0x80 /* DPC Software Trigger */
+#define PCI_DPC_CAP_RP_LOG(x) (((x) >> 8) & 0xf) /* DPC RP PIO Log Size */
+#define PCI_DPC_CAP_DL_ACT_ERR 0x1000 /* DPC DL_Active ERR_COR Signal */
+#define PCI_DPC_CTL 6 /* DPC Control */
+#define PCI_DPC_CTL_TRIGGER(x) ((x) & 0x3) /* DPC Trigger Enable */
+#define PCI_DPC_CTL_CMPL 0x4 /* DPC Completion Control */
+#define PCI_DPC_CTL_INT 0x8 /* DPC Interrupt Enabled */
+#define PCI_DPC_CTL_ERR_COR 0x10 /* DPC ERR_COR Enabled */
+#define PCI_DPC_CTL_TLP 0x20 /* DPC Poisoned TLP Egress Blocking Enabled */
+#define PCI_DPC_CTL_SW_TRIGGER 0x40 /* DPC Software Trigger */
+#define PCI_DPC_CTL_DL_ACTIVE 0x80 /* DPC DL_Active ERR_COR Enable */
+#define PCI_DPC_STATUS 8 /* DPC STATUS */
+#define PCI_DPC_STS_TRIGGER 0x01 /* DPC Trigger Status */
+#define PCI_DPC_STS_REASON(x) (((x) >> 1) & 0x3) /* DPC Trigger Reason */
+#define PCI_DPC_STS_INT 0x08 /* DPC Interrupt Status */
+#define PCI_DPC_STS_RP_BUSY 0x10 /* DPC Root Port Busy */
+#define PCI_DPC_STS_TRIGGER_EXT(x) (((x) >> 5) & 0x3) /* Trigger Reason Extention */
+#define PCI_DPC_STS_PIO_FEP(x) (((x) >> 8) & 0x1f) /* DPC PIO First Error Pointer */
+#define PCI_DPC_SOURCE 10 /* DPC Source ID */
+
+/* L1 PM Substates Extended Capability */
+#define PCI_L1PM_SUBSTAT_CAP 0x4 /* L1 PM Substate Capability */
+#define PCI_L1PM_SUBSTAT_CAP_PM_L12 0x1 /* PCI-PM L1.2 Supported */
+#define PCI_L1PM_SUBSTAT_CAP_PM_L11 0x2 /* PCI-PM L1.1 Supported */
+#define PCI_L1PM_SUBSTAT_CAP_ASPM_L12 0x4 /* ASPM L1.2 Supported */
+#define PCI_L1PM_SUBSTAT_CAP_ASPM_L11 0x8 /* ASPM L1.1 Supported */
+#define PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP 0x16 /* L1 PM Substates supported */
+#define PCI_L1PM_SUBSTAT_CTL1 0x8 /* L1 PM Substate Control 1 */
+#define PCI_L1PM_SUBSTAT_CTL1_PM_L12 0x1 /* PCI-PM L1.2 Enable */
+#define PCI_L1PM_SUBSTAT_CTL1_PM_L11 0x2 /* PCI-PM L1.1 Enable */
+#define PCI_L1PM_SUBSTAT_CTL1_ASPM_L12 0x4 /* ASPM L1.2 Enable */
+#define PCI_L1PM_SUBSTAT_CTL1_ASPM_L11 0x8 /* ASPM L1.1 Enable */
+#define PCI_L1PM_SUBSTAT_CTL2 0xC /* L1 PM Substate Control 2 */
+
/*
* The PCI interface treats multi-function devices as independent
* devices. The slot/function address of each device is encoded
#define PCI_VENDOR_ID_INTEL 0x8086
#define PCI_VENDOR_ID_COMPAQ 0x0e11
+
+/* I/O resource flags, compatible with <include/linux/ioport.h> */
+
+#define PCI_IORESOURCE_PCI_EA_BEI (1<<5)
projects / pciutils.git / blobdiff