lspci: Indent PCIe Capability DevCap2 & DevCtl2 correctly

[pciutils.git] / lib / header.h

diff --git a/lib/header.h b/lib/header.h
index a55663888e53ab1b68fe1ae902c3b2c49ee81b9d..03bbfa5ec16d18b58a346e83574e6b3f5bff3007 100644 (file)
--- a/lib/header.h
+++ b/lib/header.h
@@ -859,7 +859,13 @@
 #define  PCI_EXP_DEV2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ranges Supported */
 #define  PCI_EXP_DEV2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Value */
 #define  PCI_EXP_DEV2_TIMEOUT_DIS      0x0010  /* Completion Timeout Disable Supported */
+#define  PCI_EXP_DEV2_ATOMICOP_REQUESTER_EN    0x0040  /* AtomicOp RequesterEnable */
+#define  PCI_EXP_DEV2_ATOMICOP_EGRESS_BLOCK    0x0080  /* AtomicOp Egress Blocking */
 #define  PCI_EXP_DEV2_ARI              0x0020  /* ARI Forwarding */
+#define  PCI_EXP_DEVCAP2_ATOMICOP_ROUTING      0x0040  /* AtomicOp Routing Supported */
+#define  PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP   0x0080  /* 32bit AtomicOp Completer Supported */
+#define  PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP   0x0100  /* 64bit AtomicOp Completer Supported */
+#define  PCI_EXP_DEVCAP2_128BIT_CAS_COMP       0x0200  /* 128bit CAS Completer Supported */
 #define  PCI_EXP_DEV2_LTR              0x0400  /* LTR enabled */
 #define  PCI_EXP_DEV2_OBFF(x)          (((x) >> 13) & 3) /* OBFF enabled */
 #define PCI_EXP_DEVSTA2                        0x2a    /* Device Status */
@@ -952,9 +958,24 @@
 #define  PCI_ERR_CAP_ECRC_GENE 0x00000040      /* ECRC Generation Enable */
 #define  PCI_ERR_CAP_ECRC_CHKC 0x00000080      /* ECRC Check Capable */
 #define  PCI_ERR_CAP_ECRC_CHKE 0x00000100      /* ECRC Check Enable */
+#define  PCI_ERR_CAP_MULT_HDRC 0x00000200      /* Multiple Header Capable */
+#define  PCI_ERR_CAP_MULT_HDRE 0x00000400      /* Multiple Header Enable */
+#define  PCI_ERR_CAP_TLP_PFX   0x00000800      /* TLP Prefix Log Present */
+#define  PCI_ERR_CAP_HDR_LOG   0x00001000      /* Completion Timeout Prefix/Header Log Capable */
 #define PCI_ERR_HEADER_LOG     28      /* Header Log Register (16 bytes) */
 #define PCI_ERR_ROOT_COMMAND   44      /* Root Error Command */
-#define PCI_ERR_ROOT_STATUS    48
+#define  PCI_ERR_ROOT_CMD_COR_EN       0x00000001 /* Correctable Error Reporting Enable */
+#define  PCI_ERR_ROOT_CMD_NONFATAL_EN  0x00000002 /* Non-Fatal Error Reporting Enable*/
+#define  PCI_ERR_ROOT_CMD_FATAL_EN     0x00000004 /* Fatal Error Reporting Enable */
+#define PCI_ERR_ROOT_STATUS    48      /* Root Error Status */
+#define  PCI_ERR_ROOT_COR_RCV          0x00000001 /* ERR_COR Received */
+#define  PCI_ERR_ROOT_MULTI_COR_RCV    0x00000002 /* Multiple ERR_COR Received */
+#define  PCI_ERR_ROOT_UNCOR_RCV                0x00000004 /* ERR_FATAL/NONFATAL Received */
+#define  PCI_ERR_ROOT_MULTI_UNCOR_RCV  0x00000008 /* Multiple ERR_FATAL/NONFATAL Received */
+#define  PCI_ERR_ROOT_FIRST_FATAL      0x00000010 /* First Uncorrectable Fatal */
+#define  PCI_ERR_ROOT_NONFATAL_RCV     0x00000020 /* Non-Fatal Error Messages Received */
+#define  PCI_ERR_ROOT_FATAL_RCV                0x00000040 /* Fatal Error Messages Received */
+#define  PCI_ERR_MSG_NUM(x)    (((x) >> 27) & 0x1f) /* MSI/MSI-X vector */
 #define PCI_ERR_ROOT_COR_SRC   52
 #define PCI_ERR_ROOT_SRC       54