+scan_ops(struct op *op)
+{
+ while (op)
+ {
+ if (op->num_values >= 0)
+ pacc->writeable = 1;
+ op = op->next;
+ }
+}
+
+struct reg_name {
+ unsigned int offset;
+ unsigned int width;
+ const char *name;
+};
+
+static const struct reg_name pci_reg_names[] = {
+ { 0x00, 2, "VENDOR_ID", },
+ { 0x02, 2, "DEVICE_ID", },
+ { 0x04, 2, "COMMAND", },
+ { 0x06, 2, "STATUS", },
+ { 0x08, 1, "REVISION", },
+ { 0x09, 1, "CLASS_PROG", },
+ { 0x0a, 2, "CLASS_DEVICE", },
+ { 0x0c, 1, "CACHE_LINE_SIZE", },
+ { 0x0d, 1, "LATENCY_TIMER", },
+ { 0x0e, 1, "HEADER_TYPE", },
+ { 0x0f, 1, "BIST", },
+ { 0x10, 4, "BASE_ADDRESS_0", },
+ { 0x14, 4, "BASE_ADDRESS_1", },
+ { 0x18, 4, "BASE_ADDRESS_2", },
+ { 0x1c, 4, "BASE_ADDRESS_3", },
+ { 0x20, 4, "BASE_ADDRESS_4", },
+ { 0x24, 4, "BASE_ADDRESS_5", },
+ { 0x28, 4, "CARDBUS_CIS", },
+ { 0x2c, 4, "SUBSYSTEM_VENDOR_ID", },
+ { 0x2e, 2, "SUBSYSTEM_ID", },
+ { 0x30, 4, "ROM_ADDRESS", },
+ { 0x3c, 1, "INTERRUPT_LINE", },
+ { 0x3d, 1, "INTERRUPT_PIN", },
+ { 0x3e, 1, "MIN_GNT", },
+ { 0x3f, 1, "MAX_LAT", },
+ { 0x18, 1, "PRIMARY_BUS", },
+ { 0x19, 1, "SECONDARY_BUS", },
+ { 0x1a, 1, "SUBORDINATE_BUS", },
+ { 0x1b, 1, "SEC_LATENCY_TIMER", },
+ { 0x1c, 1, "IO_BASE", },
+ { 0x1d, 1, "IO_LIMIT", },
+ { 0x1e, 2, "SEC_STATUS", },
+ { 0x20, 2, "MEMORY_BASE", },
+ { 0x22, 2, "MEMORY_LIMIT", },
+ { 0x24, 2, "PREF_MEMORY_BASE", },
+ { 0x26, 2, "PREF_MEMORY_LIMIT", },
+ { 0x28, 4, "PREF_BASE_UPPER32", },
+ { 0x2c, 4, "PREF_LIMIT_UPPER32", },
+ { 0x30, 2, "IO_BASE_UPPER16", },
+ { 0x32, 2, "IO_LIMIT_UPPER16", },
+ { 0x38, 4, "BRIDGE_ROM_ADDRESS", },
+ { 0x3e, 2, "BRIDGE_CONTROL", },
+ { 0x10, 4, "CB_CARDBUS_BASE", },
+ { 0x14, 2, "CB_CAPABILITIES", },
+ { 0x16, 2, "CB_SEC_STATUS", },
+ { 0x18, 1, "CB_BUS_NUMBER", },
+ { 0x19, 1, "CB_CARDBUS_NUMBER", },
+ { 0x1a, 1, "CB_SUBORDINATE_BUS", },
+ { 0x1b, 1, "CB_CARDBUS_LATENCY", },
+ { 0x1c, 4, "CB_MEMORY_BASE_0", },
+ { 0x20, 4, "CB_MEMORY_LIMIT_0", },
+ { 0x24, 4, "CB_MEMORY_BASE_1", },
+ { 0x28, 4, "CB_MEMORY_LIMIT_1", },
+ { 0x2c, 2, "CB_IO_BASE_0", },
+ { 0x2e, 2, "CB_IO_BASE_0_HI", },
+ { 0x30, 2, "CB_IO_LIMIT_0", },
+ { 0x32, 2, "CB_IO_LIMIT_0_HI", },
+ { 0x34, 2, "CB_IO_BASE_1", },
+ { 0x36, 2, "CB_IO_BASE_1_HI", },
+ { 0x38, 2, "CB_IO_LIMIT_1", },
+ { 0x3a, 2, "CB_IO_LIMIT_1_HI", },
+ { 0x40, 2, "CB_SUBSYSTEM_VENDOR_ID", },
+ { 0x42, 2, "CB_SUBSYSTEM_ID", },
+ { 0x44, 4, "CB_LEGACY_MODE_BASE", },
+ { 0x00, 0, NULL }
+};
+
+static void NONRET PCI_PRINTF(1,2)
+usage(char *msg, ...)