- 2c01 Core i7 QuickPath Architecture System Address Decoder
- 2c10 Core i7 QPI Link 0
- 2c11 Core i7 QPI Physical 0
- 2c14 Core i7 QPI Link 1
- 2c15 Core i7 QPI Physical 1
- 2c18 Core i7 Integrated Memory Controller
- 2c19 Core i7 Integrated Memory Controller Target Address Decoder
- 2c1a Core i7 Integrated Memory Controller RAS Registers
- 2c1c Core i7 Integrated Memory Controller Test Registers
- 2c20 Core i7 Integrated Memory Controller Channel 0 Control Registers
- 2c21 Core i7 Integrated Memory Controller Channel 0 Address Registers
- 2c22 Core i7 Integrated Memory Controller Channel 0 Rank Registers
- 2c23 Core i7 Integrated Memory Controller Channel 0 Thermal Control Registers
- 2c28 Core i7 Integrated Memory Controller Channel 1 Control Registers
- 2c29 Core i7 Integrated Memory Controller Channel 1 Address Registers
- 2c2a Core i7 Integrated Memory Controller Channel 1 Rank Registers
- 2c2b Core i7 Integrated Memory Controller Channel 1 Thermal Control Registers
- 2c30 Core i7 Integrated Memory Controller Channel 2 Control Registers
- 2c31 Core i7 Integrated Memory Controller Channel 2 Address Registers
- 2c32 Core i7 Integrated Memory Controller Channel 2 Rank Registers
- 2c33 Core i7 Integrated Memory Controller Channel 2 Thermal Control Registers
- 2c40 Core i7 QuickPath Architecture Generic Non-Core Registers
- 2c41 QuickPath Architecture Generic Non-Core Registers
- 2c50 QuickPath Architecture Generic Non-Core Registers
- 2c51 QuickPath Architecture Generic Non-Core Registers
- 2c52 QuickPath Architecture Generic Non-Core Registers
- 2c53 QuickPath Architecture Generic Non-Core Registers
- 2c54 QuickPath Architecture Generic Non-Core Registers
- 2c55 QuickPath Architecture Generic Non-Core Registers
- 2c56 QuickPath Architecture Generic Non-Core Registers
- 2c57 QuickPath Architecture Generic Non-Core Registers
- 2c81 QuickPath Architecture System Address Decoder
- 2c90 QPI Link
- 2c91 QPI Physical 0
- 2c98 Lynnfield Integrated Memory Controller
- 2c99 Lynnfield Integrated Memory Controller Target Address Decoder
- 2c9c Lynnfield Integrated Memory Controller Test Registers
- 2ca0 Lynnfield Integrated Memory Controller Channel 0 Control Registers
- 2ca1 Lynnfield Integrated Memory Controller Channel 0 Address Registers
- 2ca2 Lynnfield Integrated Memory Controller Channel 0 Rank Registers
- 2ca3 Lynnfield Integrated Memory Controller Channel 0 Thermal Control Registers
- 2ca8 Lynnfield Integrated Memory Controller Channel 1 Control Registers
- 2ca9 Lynnfield Integrated Memory Controller Channel 1 Address Registers
- 2caa Lynnfield Integrated Memory Controller Channel 1 Rank Registers
- 2cab Lynnfield Integrated Memory Controller Channel 1 Thermal Control Registers
+ 2b00 Nehalem-EX System Configuration Controller 1
+ 2b02 Nehalem-EX System Configuration Controller 2
+ 2b04 Nehalem-EX Power Controller
+ 2b08 Nehalem-EX Caching Agent 0
+ 2b0c Nehalem-EX Caching Agent 1
+ 2b10 Nehalem-EX QPI Home Agent 0
+ 2b13 Nehalem-EX Memory Controller 0c
+ 2b14 Nehalem-EX Memory Controller 0a
+ 2b16 Nehalem-EX Memory Controller 0b
+ 2b18 Nehalem-EX QPI Home Agent 1
+ 2b1b Nehalem-EX Memory Controller 1c
+ 2b1c Nehalem-EX Memory Controller 1a
+ 2b1e Nehalem-EX Memory Controller 1b
+ 2b20 Nehalem-EX Last Level Cache Coherence Engine 0
+ 2b24 Nehalem-EX Last Level Cache Coherence Engine 1
+ 2b28 Nehalem-EX Last Level Cache Coherence Engine 2
+ 2b2c Nehalem-EX Last Level Cache Coherence Engine 3
+ 2b30 Nehalem-EX Last Level Cache Coherence Engine 4
+ 2b34 Nehalem-EX Last Level Cache Coherence Engine 5
+ 2b38 Nehalem-EX Last Level Cache Coherence Engine 6
+ 2b3c Nehalem-EX Last Level Cache Coherence Engine 7
+ 2b40 Nehalem-EX QPI Router Port 0-1
+ 2b42 Nehalem-EX QPI Router Port 2-3
+ 2b44 Nehalem-EX QPI Router Port 4-5
+ 2b46 Nehalem-EX QPI Router Port 6-7
+ 2b48 Nehalem-EX Test and Debug 0
+ 2b4c Nehalem-EX Test and Debug 1
+ 2b50 Nehalem-EX QPI Physical Port 0: REUT control/status
+ 2b52 Nehalem-EX QPI Physical Port 0: Misc. control/status
+ 2b54 Nehalem-EX QPI Physical Port 1: REUT control/status
+ 2b56 Nehalem-EX QPI Physical Port 1: Misc. control/status
+ 2b58 Nehalem-EX QPI Physical Port 2: REUT control/status
+ 2b5a Nehalem-EX QPI Physical Port 2: Misc. control/status
+ 2b5c Nehalem-EX QPI Physical Port 3: REUT control/status
+ 2b5e Nehalem-EX QPI Physical Port 3: Misc. control/status
+ 2b60 Nehalem-EX SMI Physical Port 0: REUT control/status
+ 2b62 Nehalem-EX SMI Physical Port 0: Misc control/status
+ 2b64 Nehalem-EX SMI Physical Port 0: REUT control/status
+ 2b66 Nehalem-EX SMI Physical Port 1: Misc control/status
+ 2b68 Nehalem-EX System Configuration Controller 3
+ 2b6a Nehalem-EX System Configuration Controller 4
+ 2c01 Xeon 5500/Core i7 QuickPath Architecture System Address Decoder
+ 2c10 Xeon 5500/Core i7 QPI Link 0
+ 2c11 Xeon 5500/Core i7 QPI Physical 0
+ 2c14 Xeon 5500/Core i7 QPI Link 1
+ 2c15 Xeon 5500/Core i7 QPI Physical 1
+ 2c18 Xeon 5500/Core i7 Integrated Memory Controller
+ 2c19 Xeon 5500/Core i7 Integrated Memory Controller Target Address Decoder
+ 2c1a Xeon 5500/Core i7 Integrated Memory Controller RAS Registers
+ 2c1c Xeon 5500/Core i7 Integrated Memory Controller Test Registers
+ 2c20 Xeon 5500/Core i7 Integrated Memory Controller Channel 0 Control Registers
+ 2c21 Xeon 5500/Core i7 Integrated Memory Controller Channel 0 Address Registers
+ 2c22 Xeon 5500/Core i7 Integrated Memory Controller Channel 0 Rank Registers
+ 2c23 Xeon 5500/Core i7 Integrated Memory Controller Channel 0 Thermal Control Registers
+ 2c28 Xeon 5500/Core i7 Integrated Memory Controller Channel 1 Control Registers
+ 2c29 Xeon 5500/Core i7 Integrated Memory Controller Channel 1 Address Registers
+ 2c2a Xeon 5500/Core i7 Integrated Memory Controller Channel 1 Rank Registers
+ 2c2b Xeon 5500/Core i7 Integrated Memory Controller Channel 1 Thermal Control Registers
+ 2c30 Xeon 5500/Core i7 Integrated Memory Controller Channel 2 Control Registers
+ 2c31 Xeon 5500/Core i7 Integrated Memory Controller Channel 2 Address Registers
+ 2c32 Xeon 5500/Core i7 Integrated Memory Controller Channel 2 Rank Registers
+ 2c33 Xeon 5500/Core i7 Integrated Memory Controller Channel 2 Thermal Control Registers
+ 2c40 Xeon 5500/Core i7 QuickPath Architecture Generic Non-Core Registers
+ 2c41 Xeon 5500/Core i7 QuickPath Architecture Generic Non-Core Registers
+ 2c50 Core Processor QuickPath Architecture Generic Non-Core Registers
+ 2c51 Core Processor QuickPath Architecture Generic Non-Core Registers
+ 2c52 Core Processor QuickPath Architecture Generic Non-Core Registers
+ 2c53 Core Processor QuickPath Architecture Generic Non-Core Registers
+ 2c54 Core Processor QuickPath Architecture Generic Non-Core Registers
+ 2c55 Core Processor QuickPath Architecture Generic Non-Core Registers
+ 2c56 Core Processor QuickPath Architecture Generic Non-Core Registers
+ 2c57 Core Processor QuickPath Architecture Generic Non-Core Registers
+ 2c58 Jasper Forest QPI Generic Non-core Registers
+ 2c59 Jasper Forest QPI Generic Non-core Registers
+ 2c5a Jasper Forest QPI Generic Non-core Registers
+ 2c5b Jasper Forest QPI Generic Non-core Registers
+ 2c5c Jasper Forest QPI Generic Non-core Registers
+ 2c5d Jasper Forest QPI Generic Non-core Registers
+ 2c5e Jasper Forest QPI Generic Non-core Registers
+ 2c5f Jasper Forest QPI Generic Non-core Registers
+ 2c61 Core Processor QuickPath Architecture Generic Non-core Registers
+ 2c62 Core Processor QuickPath Architecture Generic Non-core Registers
+ 2c70 QuickPath Architecture Generic Non-core Registers
+ 2c81 Core Processor QuickPath Architecture System Address Decoder
+ 2c90 Core Processor QPI Link 0
+ 2c91 Core Processor QPI Physical 0
+ 2c98 Core Processor Integrated Memory Controller
+ 2c99 Core Processor Integrated Memory Controller Target Address Decoder
+ 2c9c Core Processor Integrated Memory Controller Test Registers
+ 2ca0 Core Processor Integrated Memory Controller Channel 0 Control Registers
+ 2ca1 Core Processor Integrated Memory Controller Channel 0 Address Registers
+ 2ca2 Core Processor Integrated Memory Controller Channel 0 Rank Registers
+ 2ca3 Core Processor Integrated Memory Controller Channel 0 Thermal Control Registers
+ 2ca8 Core Processor Integrated Memory Controller Channel 1 Control Registers
+ 2ca9 Core Processor Integrated Memory Controller Channel 1 Address Registers
+ 2caa Core Processor Integrated Memory Controller Channel 1 Rank Registers
+ 2cab Core Processor Integrated Memory Controller Channel 1 Thermal Control Registers
+ 2cc1 Jasper Forest QPI System Address Decoder
+ 2cd0 Jasper Forest QPI Link 0
+ 2cd1 Jasper Forest QPI Physical 0
+ 2cd4 Jasper Forest QPI Link 1
+ 2cd5 Jasper Forest QPI Physical 1
+ 2cd8 Jasper Forest Integrated Memory Controller Registers
+ 2cd9 Jasper Forest Integrated Memory Controller Target Address Decoder
+ 2cda Jasper Forest Integrated Memory Controller RAS Registers
+ 2cdc Jasper Forest Integrated Memory Controller Test Registers
+ 2ce0 Jasper Forest Integrated Memory Controller Channel 0 Control
+ 2ce1 Jasper Forest Integrated Memory Controller Channel 0 Address
+ 2ce2 Jasper Forest Integrated Memory Controller Channel 0 Rank
+ 2ce3 Jasper Forest Integrated Memory Controller Channel 0 Thermal Control
+ 2ce8 Jasper Forest Integrated Memory Controller Channel 1 Control
+ 2ce9 Jasper Forest Integrated Memory Controller Channel 1 Address
+ 2cea Jasper Forest Integrated Memory Controller Channel 1 Rank
+ 2ceb Jasper Forest Integrated Memory Controller Channel 1 Thermal Control
+ 2cf0 Jasper Forest Integrated Memory Controller Channel 2 Control
+ 2cf1 Jasper Forest Integrated Memory Controller Channel 2 Address
+ 2cf2 Jasper Forest Integrated Memory Controller Channel 2 Rank
+ 2cf3 Jasper Forest Integrated Memory Controller Channel 2 Thermal Control
+ 2d01 Core Processor QuickPath Architecture System Address Decoder
+ 2d10 Core Processor QPI Link 0
+ 2d11 Core Processor QPI Physical 0
+ 2d12 Core Processor Reserved
+ 2d13 Core Processor Reserved
+ 2d81 QuickPath Architecture System Address Decoder
+ 2d90 QPI Link 0
+ 2d91 QPI Physical 0
+ 2d92 Mirror Port Link 0
+ 2d93 Mirror Port Link 1
+ 2d94 QPI Link 1
+ 2d95 QPI Physical 1
+ 2d98 Integrated Memory Controller Registers
+ 2d99 Integrated Memory Controller Target Address Decoder
+ 2d9a Integrated Memory Controller RAS Registers
+ 2d9c Integrated Memory Controller Test Registers
+ 2da0 Integrated Memory Controller Channel 0 Control
+ 2da1 Integrated Memory Controller Channel 0 Address
+ 2da2 Integrated Memory Controller Channel 0 Rank
+ 2da3 Integrated Memory Controller Channel 0 Thermal Control
+ 2da8 Integrated Memory Controller Channel 1 Control
+ 2da9 Integrated Memory Controller Channel 1 Address
+ 2daa Integrated Memory Controller Channel 1 Rank
+ 2dab Integrated Memory Controller Channel 1 Thermal Control
+ 2db0 Integrated Memory Controller Channel 2 Control
+ 2db1 Integrated Memory Controller Channel 2 Address
+ 2db2 Integrated Memory Controller Channel 2 Rank
+ 2db3 Integrated Memory Controller Channel 2 Thermal Control