+ int i;
+ word cmd = get_conf_word(d, PCI_COMMAND);
+ word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
+ word exca;
+ int verb = verbose > 2;
+
+ show_bases(d, 1, 0);
+ printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
+ get_conf_byte(d, PCI_CB_PRIMARY_BUS),
+ get_conf_byte(d, PCI_CB_CARD_BUS),
+ get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
+ get_conf_byte(d, PCI_CB_LATENCY_TIMER));
+ for (i=0; i<2; i++)
+ {
+ int p = 8*i;
+ u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
+ u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
+ limit = limit + 0xfff;
+ if (base <= limit || verb)
+ printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
+ (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
+ (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
+ }
+ for (i=0; i<2; i++)
+ {
+ int p = 8*i;
+ u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
+ u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
+ if (!(base & PCI_IO_RANGE_TYPE_32))
+ {
+ base &= 0xffff;
+ limit &= 0xffff;
+ }
+ base &= PCI_CB_IO_RANGE_MASK;
+ limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
+ if (base <= limit || verb)
+ printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
+ (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
+ }
+
+ if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
+ printf("\tSecondary status: SERR\n");
+ if (verbose > 1)
+ printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
+ FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
+ FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
+ FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
+ FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
+ FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
+ FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
+ FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
+ FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
+
+ if (d->config_cached < 128)
+ {
+ printf("\t<access denied to the rest>\n");
+ return;
+ }
+
+ exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
+ if (exca)
+ printf("\t16-bit legacy interface ports at %04x\n", exca);
+ show_caps(d, PCI_CB_CAPABILITY_LIST);
+}
+
+static void
+show_htype_unknown(struct device *d)
+{
+ struct pci_dev *p = d->dev;
+ u64 base, limit, flags;
+ const char *str;
+ int i, bits;
+
+ if (pacc->buscentric)
+ return;
+
+ show_bases(d, 6, 1);
+ for (i = 0; i < 4; i++)
+ {
+ if (!p->bridge_base_addr[i])
+ continue;
+ base = p->bridge_base_addr[i];
+ limit = base + p->bridge_size[i] - 1;
+ flags = p->bridge_flags[i];
+ if (flags & PCI_IORESOURCE_IO)
+ {
+ bits = (flags & PCI_IORESOURCE_IO_16BIT_ADDR) ? 16 : 32;
+ str = "\tI/O behind bridge";
+ }
+ else if (flags & PCI_IORESOURCE_MEM)
+ {
+ bits = (flags & PCI_IORESOURCE_MEM_64) ? 64 : 32;
+ if (flags & PCI_IORESOURCE_PREFETCH)
+ str = "\tPrefetchable memory behind bridge";
+ else
+ str = "\tMemory behind bridge";
+ }
+ else
+ {
+ bits = 0;
+ str = "\tUnknown resource behind bridge";
+ }
+ show_range(str, base, limit, bits, 0);
+ }
+ show_rom(d, -1);