+static void
+format_agp_rate(int rate, char *buf, int agp3)
+{
+ char *c = buf;
+ int i;
+
+ for(i=0; i<=2; i++)
+ if (rate & (1 << i))
+ {
+ if (c != buf)
+ *c++ = ',';
+ c += sprintf(c, "x%d", 1 << (i + 2*agp3));
+ }
+ if (c != buf)
+ *c = 0;
+ else
+ strcpy(buf, "<none>");
+}
+
+static void
+cap_agp(struct device *d, int where, int cap)
+{
+ u32 t;
+ char rate[16];
+ int ver, rev;
+ int agp3 = 0;
+
+ ver = (cap >> 4) & 0x0f;
+ rev = cap & 0x0f;
+ printf("AGP version %x.%x\n", ver, rev);
+ if (verbose < 2)
+ return;
+ if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
+ return;
+ t = get_conf_long(d, where + PCI_AGP_STATUS);
+ if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
+ agp3 = 1;
+ format_agp_rate(t & 7, rate, agp3);
+ printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
+ ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
+ FLAG(t, PCI_AGP_STATUS_ISOCH),
+ ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
+ ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
+ FLAG(t, PCI_AGP_STATUS_SBA),
+ FLAG(t, PCI_AGP_STATUS_ITA_COH),
+ FLAG(t, PCI_AGP_STATUS_GART64),
+ FLAG(t, PCI_AGP_STATUS_HTRANS),
+ FLAG(t, PCI_AGP_STATUS_64BIT),
+ FLAG(t, PCI_AGP_STATUS_FW),
+ FLAG(t, PCI_AGP_STATUS_AGP3),
+ rate);
+ t = get_conf_long(d, where + PCI_AGP_COMMAND);
+ format_agp_rate(t & 7, rate, agp3);
+ printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
+ ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
+ ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
+ ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
+ FLAG(t, PCI_AGP_COMMAND_SBA),
+ FLAG(t, PCI_AGP_COMMAND_AGP),
+ FLAG(t, PCI_AGP_COMMAND_GART64),
+ FLAG(t, PCI_AGP_COMMAND_64BIT),
+ FLAG(t, PCI_AGP_COMMAND_FW),
+ rate);
+}
+
+static void
+cap_pcix_nobridge(struct device *d, int where)
+{
+ u16 command;
+ u32 status;
+ static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
+
+ printf("PCI-X non-bridge device\n");
+
+ if (verbose < 2)
+ return;
+
+ if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
+ return;
+
+ command = get_conf_word(d, where + PCI_PCIX_COMMAND);
+ status = get_conf_long(d, where + PCI_PCIX_STATUS);
+ printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
+ FLAG(command, PCI_PCIX_COMMAND_DPERE),
+ FLAG(command, PCI_PCIX_COMMAND_ERO),
+ 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
+ max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
+ printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
+ ((status >> 8) & 0xff),
+ ((status >> 3) & 0x1f),
+ (status & PCI_PCIX_STATUS_FUNCTION),
+ FLAG(status, PCI_PCIX_STATUS_64BIT),
+ FLAG(status, PCI_PCIX_STATUS_133MHZ),
+ FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
+ FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
+ ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
+ 1 << (9 + ((status >> 21) & 3U)),
+ max_outstanding[(status >> 23) & 7U],
+ 1 << (3 + ((status >> 26) & 7U)),
+ FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
+ FLAG(status, PCI_PCIX_STATUS_266MHZ),
+ FLAG(status, PCI_PCIX_STATUS_533MHZ));
+}
+
+static void
+cap_pcix_bridge(struct device *d, int where)
+{
+ static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
+ u16 secstatus;
+ u32 status, upstcr, downstcr;
+
+ printf("PCI-X bridge device\n");
+
+ if (verbose < 2)
+ return;
+
+ if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
+ return;
+
+ secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
+ printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
+ FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
+ FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
+ FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
+ FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
+ FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
+ FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
+ sec_clock_freq[(secstatus >> 6) & 7]);
+ status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
+ printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
+ ((status >> 8) & 0xff),
+ ((status >> 3) & 0x1f),
+ (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
+ FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
+ FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
+ FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
+ FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
+ FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
+ FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
+ upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
+ printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
+ (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
+ (upstcr >> 16) & 0xffff);
+ downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
+ printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
+ (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
+ (downstcr >> 16) & 0xffff);
+}
+
+static void
+cap_pcix(struct device *d, int where)
+{
+ switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
+ {
+ case PCI_HEADER_TYPE_NORMAL:
+ cap_pcix_nobridge(d, where);
+ break;
+ case PCI_HEADER_TYPE_BRIDGE:
+ cap_pcix_bridge(d, where);
+ break;
+ }
+}
+
+static inline char *
+ht_link_width(unsigned width)
+{
+ static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
+ return widths[width];
+}
+
+static inline char *
+ht_link_freq(unsigned freq)
+{
+ static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
+ "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
+ return freqs[freq];
+}
+
+static void
+cap_ht_pri(struct device *d, int where, int cmd)
+{
+ u16 lctr0, lcnf0, lctr1, lcnf1, eh;
+ u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
+ char *fmt;
+
+ printf("HyperTransport: Slave or Primary Interface\n");
+ if (verbose < 2)
+ return;
+
+ if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
+ return;
+ rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
+ if (rid < 0x23 && rid > 0x11)
+ printf("\t\t!!! Possibly incomplete decoding\n");
+
+ if (rid >= 0x23)
+ fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
+ else
+ fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
+ printf(fmt,
+ (cmd & PCI_HT_PRI_CMD_BUID),
+ (cmd & PCI_HT_PRI_CMD_UC) >> 5,
+ FLAG(cmd, PCI_HT_PRI_CMD_MH),
+ FLAG(cmd, PCI_HT_PRI_CMD_DD),
+ FLAG(cmd, PCI_HT_PRI_CMD_DUL));
+ lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
+ if (rid >= 0x23)
+ fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
+ else
+ fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
+ printf(fmt,
+ FLAG(lctr0, PCI_HT_LCTR_CFLE),
+ FLAG(lctr0, PCI_HT_LCTR_CST),
+ FLAG(lctr0, PCI_HT_LCTR_CFE),
+ FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
+ FLAG(lctr0, PCI_HT_LCTR_INIT),
+ FLAG(lctr0, PCI_HT_LCTR_EOC),
+ FLAG(lctr0, PCI_HT_LCTR_TXO),
+ (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
+ FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
+ FLAG(lctr0, PCI_HT_LCTR_LSEN),
+ FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
+ FLAG(lctr0, PCI_HT_LCTR_64B));
+ lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
+ if (rid >= 0x23)
+ fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
+ else
+ fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
+ printf(fmt,
+ ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
+ ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
+ ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
+ ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
+ FLAG(lcnf0, PCI_HT_LCNF_DFI),
+ FLAG(lcnf0, PCI_HT_LCNF_DFO),
+ FLAG(lcnf0, PCI_HT_LCNF_DFIE),
+ FLAG(lcnf0, PCI_HT_LCNF_DFOE));
+ lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
+ if (rid >= 0x23)
+ fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
+ else
+ fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
+ printf(fmt,
+ FLAG(lctr1, PCI_HT_LCTR_CFLE),
+ FLAG(lctr1, PCI_HT_LCTR_CST),
+ FLAG(lctr1, PCI_HT_LCTR_CFE),
+ FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
+ FLAG(lctr1, PCI_HT_LCTR_INIT),
+ FLAG(lctr1, PCI_HT_LCTR_EOC),
+ FLAG(lctr1, PCI_HT_LCTR_TXO),
+ (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
+ FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
+ FLAG(lctr1, PCI_HT_LCTR_LSEN),
+ FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
+ FLAG(lctr1, PCI_HT_LCTR_64B));
+ lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
+ if (rid >= 0x23)
+ fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
+ else
+ fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
+ printf(fmt,
+ ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
+ ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
+ ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
+ ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
+ FLAG(lcnf1, PCI_HT_LCNF_DFI),
+ FLAG(lcnf1, PCI_HT_LCNF_DFO),
+ FLAG(lcnf1, PCI_HT_LCNF_DFIE),
+ FLAG(lcnf1, PCI_HT_LCNF_DFOE));
+ printf("\t\tRevision ID: %u.%02u\n",
+ (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
+ if (rid < 0x23)
+ return;
+ lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
+ printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
+ printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
+ FLAG(lfrer0, PCI_HT_LFRER_PROT),
+ FLAG(lfrer0, PCI_HT_LFRER_OV),
+ FLAG(lfrer0, PCI_HT_LFRER_EOC),
+ FLAG(lfrer0, PCI_HT_LFRER_CTLT));
+ lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
+ printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
+ FLAG(lfcap0, PCI_HT_LFCAP_200),
+ FLAG(lfcap0, PCI_HT_LFCAP_300),
+ FLAG(lfcap0, PCI_HT_LFCAP_400),
+ FLAG(lfcap0, PCI_HT_LFCAP_500),
+ FLAG(lfcap0, PCI_HT_LFCAP_600),
+ FLAG(lfcap0, PCI_HT_LFCAP_800),
+ FLAG(lfcap0, PCI_HT_LFCAP_1000),
+ FLAG(lfcap0, PCI_HT_LFCAP_1200),
+ FLAG(lfcap0, PCI_HT_LFCAP_1400),
+ FLAG(lfcap0, PCI_HT_LFCAP_1600),
+ FLAG(lfcap0, PCI_HT_LFCAP_VEND));
+ ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
+ printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
+ FLAG(ftr, PCI_HT_FTR_ISOCFC),
+ FLAG(ftr, PCI_HT_FTR_LDTSTOP),
+ FLAG(ftr, PCI_HT_FTR_CRCTM),
+ FLAG(ftr, PCI_HT_FTR_ECTLT),
+ FLAG(ftr, PCI_HT_FTR_64BA),
+ FLAG(ftr, PCI_HT_FTR_UIDRD));
+ lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
+ printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
+ printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
+ FLAG(lfrer1, PCI_HT_LFRER_PROT),
+ FLAG(lfrer1, PCI_HT_LFRER_OV),
+ FLAG(lfrer1, PCI_HT_LFRER_EOC),
+ FLAG(lfrer1, PCI_HT_LFRER_CTLT));
+ lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
+ printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
+ FLAG(lfcap1, PCI_HT_LFCAP_200),
+ FLAG(lfcap1, PCI_HT_LFCAP_300),
+ FLAG(lfcap1, PCI_HT_LFCAP_400),
+ FLAG(lfcap1, PCI_HT_LFCAP_500),
+ FLAG(lfcap1, PCI_HT_LFCAP_600),
+ FLAG(lfcap1, PCI_HT_LFCAP_800),
+ FLAG(lfcap1, PCI_HT_LFCAP_1000),
+ FLAG(lfcap1, PCI_HT_LFCAP_1200),
+ FLAG(lfcap1, PCI_HT_LFCAP_1400),
+ FLAG(lfcap1, PCI_HT_LFCAP_1600),
+ FLAG(lfcap1, PCI_HT_LFCAP_VEND));
+ eh = get_conf_word(d, where + PCI_HT_PRI_EH);
+ printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
+ FLAG(eh, PCI_HT_EH_PFLE),
+ FLAG(eh, PCI_HT_EH_OFLE),
+ FLAG(eh, PCI_HT_EH_PFE),
+ FLAG(eh, PCI_HT_EH_OFE),
+ FLAG(eh, PCI_HT_EH_EOCFE),
+ FLAG(eh, PCI_HT_EH_RFE),
+ FLAG(eh, PCI_HT_EH_CRCFE),
+ FLAG(eh, PCI_HT_EH_SERRFE),
+ FLAG(eh, PCI_HT_EH_CF),
+ FLAG(eh, PCI_HT_EH_RE),
+ FLAG(eh, PCI_HT_EH_PNFE),
+ FLAG(eh, PCI_HT_EH_ONFE),
+ FLAG(eh, PCI_HT_EH_EOCNFE),
+ FLAG(eh, PCI_HT_EH_RNFE),
+ FLAG(eh, PCI_HT_EH_CRCNFE),
+ FLAG(eh, PCI_HT_EH_SERRNFE));
+ mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
+ mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
+ printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
+ bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
+ printf("\t\tBus Number: %02x\n", bn);
+}
+
+static void
+cap_ht_sec(struct device *d, int where, int cmd)
+{
+ u16 lctr, lcnf, ftr, eh;
+ u8 rid, lfrer, lfcap, mbu, mlu;
+ char *fmt;
+
+ printf("HyperTransport: Host or Secondary Interface\n");
+ if (verbose < 2)
+ return;
+
+ if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
+ return;
+ rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
+ if (rid < 0x23 && rid > 0x11)
+ printf("\t\t!!! Possibly incomplete decoding\n");
+
+ if (rid >= 0x23)
+ fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
+ else
+ fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
+ printf(fmt,
+ FLAG(cmd, PCI_HT_SEC_CMD_WR),
+ FLAG(cmd, PCI_HT_SEC_CMD_DE),
+ (cmd & PCI_HT_SEC_CMD_DN) >> 2,
+ FLAG(cmd, PCI_HT_SEC_CMD_CS),
+ FLAG(cmd, PCI_HT_SEC_CMD_HH),
+ FLAG(cmd, PCI_HT_SEC_CMD_AS),
+ FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
+ FLAG(cmd, PCI_HT_SEC_CMD_DUL));
+ lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
+ if (rid >= 0x23)
+ fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
+ else
+ fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
+ printf(fmt,
+ FLAG(lctr, PCI_HT_LCTR_CFLE),
+ FLAG(lctr, PCI_HT_LCTR_CST),
+ FLAG(lctr, PCI_HT_LCTR_CFE),
+ FLAG(lctr, PCI_HT_LCTR_LKFAIL),
+ FLAG(lctr, PCI_HT_LCTR_INIT),
+ FLAG(lctr, PCI_HT_LCTR_EOC),
+ FLAG(lctr, PCI_HT_LCTR_TXO),
+ (lctr & PCI_HT_LCTR_CRCERR) >> 8,
+ FLAG(lctr, PCI_HT_LCTR_ISOCEN),
+ FLAG(lctr, PCI_HT_LCTR_LSEN),
+ FLAG(lctr, PCI_HT_LCTR_EXTCTL),
+ FLAG(lctr, PCI_HT_LCTR_64B));
+ lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
+ if (rid >= 0x23)
+ fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
+ else
+ fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
+ printf(fmt,
+ ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
+ ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
+ ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
+ ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
+ FLAG(lcnf, PCI_HT_LCNF_DFI),
+ FLAG(lcnf, PCI_HT_LCNF_DFO),
+ FLAG(lcnf, PCI_HT_LCNF_DFIE),
+ FLAG(lcnf, PCI_HT_LCNF_DFOE));
+ printf("\t\tRevision ID: %u.%02u\n",
+ (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
+ if (rid < 0x23)
+ return;
+ lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
+ printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
+ printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
+ FLAG(lfrer, PCI_HT_LFRER_PROT),
+ FLAG(lfrer, PCI_HT_LFRER_OV),
+ FLAG(lfrer, PCI_HT_LFRER_EOC),
+ FLAG(lfrer, PCI_HT_LFRER_CTLT));
+ lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
+ printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
+ FLAG(lfcap, PCI_HT_LFCAP_200),
+ FLAG(lfcap, PCI_HT_LFCAP_300),
+ FLAG(lfcap, PCI_HT_LFCAP_400),
+ FLAG(lfcap, PCI_HT_LFCAP_500),
+ FLAG(lfcap, PCI_HT_LFCAP_600),
+ FLAG(lfcap, PCI_HT_LFCAP_800),
+ FLAG(lfcap, PCI_HT_LFCAP_1000),
+ FLAG(lfcap, PCI_HT_LFCAP_1200),
+ FLAG(lfcap, PCI_HT_LFCAP_1400),
+ FLAG(lfcap, PCI_HT_LFCAP_1600),
+ FLAG(lfcap, PCI_HT_LFCAP_VEND));
+ ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
+ printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
+ FLAG(ftr, PCI_HT_FTR_ISOCFC),
+ FLAG(ftr, PCI_HT_FTR_LDTSTOP),
+ FLAG(ftr, PCI_HT_FTR_CRCTM),
+ FLAG(ftr, PCI_HT_FTR_ECTLT),
+ FLAG(ftr, PCI_HT_FTR_64BA),
+ FLAG(ftr, PCI_HT_FTR_UIDRD),
+ FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
+ FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
+ if (ftr & PCI_HT_SEC_FTR_EXTRS)