+ if (cap & PCI_MSI_FLAGS_MASK_BIT)
+ {
+ u32 mask, pending;
+
+ if (is64)
+ {
+ if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
+ return;
+ mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
+ pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
+ }
+ else
+ {
+ if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
+ return;
+ mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
+ pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
+ }
+ printf("\t\tMasking: %08x Pending: %08x\n", mask, pending);
+ }
+}
+
+static float power_limit(int value, int scale)
+{
+ static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
+ return value * scales[scale];
+}
+
+static const char *latency_l0s(int value)
+{
+ static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
+ return latencies[value];
+}
+
+static const char *latency_l1(int value)
+{
+ static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
+ return latencies[value];
+}
+
+static void cap_express_dev(struct device *d, int where, int type)
+{
+ u32 t;
+ u16 w;
+
+ t = get_conf_long(d, where + PCI_EXP_DEVCAP);
+ printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d, Latency L0s %s, L1 %s\n",
+ 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
+ (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
+ latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
+ latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
+ printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
+ if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
+ (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
+ printf(" AttnBtn%c AttnInd%c PwrInd%c",
+ FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
+ FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
+ printf(" RBE%c FLReset%c",
+ FLAG(t, PCI_EXP_DEVCAP_RBE),
+ FLAG(t, PCI_EXP_DEVCAP_FLRESET));
+ if (type == PCI_EXP_TYPE_UPSTREAM)
+ printf("SlotPowerLimit %fW",
+ power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
+ (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
+ printf("\n");
+
+ w = get_conf_word(d, where + PCI_EXP_DEVCTL);
+ printf("\t\tDevCtl:\tReport errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
+ FLAG(w, PCI_EXP_DEVCTL_CERE),
+ FLAG(w, PCI_EXP_DEVCTL_NFERE),
+ FLAG(w, PCI_EXP_DEVCTL_FERE),
+ FLAG(w, PCI_EXP_DEVCTL_URRE));
+ printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
+ FLAG(w, PCI_EXP_DEVCTL_RELAXED),
+ FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
+ FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
+ FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
+ FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
+ if (type == PCI_EXP_TYPE_PCI_BRIDGE || type == PCI_EXP_TYPE_PCIE_BRIDGE)
+ printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
+ if (type == PCI_EXP_TYPE_ENDPOINT && (t & PCI_EXP_DEVCAP_FLRESET))
+ printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
+ printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
+ 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
+ 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
+
+ w = get_conf_word(d, where + PCI_EXP_DEVSTA);
+ printf("\t\tDevSta:\tCorrErr%c UncorrErr%c FatalErr%c UnsuppReq%c AuxPwr%c TransPend%c\n",
+ FLAG(w, PCI_EXP_DEVSTA_CED),
+ FLAG(w, PCI_EXP_DEVSTA_NFED),
+ FLAG(w, PCI_EXP_DEVSTA_FED),
+ FLAG(w, PCI_EXP_DEVSTA_URD),
+ FLAG(w, PCI_EXP_DEVSTA_AUXPD),
+ FLAG(w, PCI_EXP_DEVSTA_TRPND));
+
+ /* FIXME: Second set of control/status registers is not supported yet. */
+}
+
+static char *link_speed(int speed)
+{
+ switch (speed)
+ {
+ case 1:
+ return "2.5GT/s";
+ case 2:
+ return "5GT/s";
+ default:
+ return "unknown";
+ }
+}
+
+static char *aspm_support(int code)
+{
+ switch (code)
+ {
+ case 1:
+ return "L0s";
+ case 3:
+ return "L0s L1";
+ default:
+ return "unknown";
+ }
+}
+
+static const char *aspm_enabled(int code)
+{
+ static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
+ return desc[code];
+}
+
+static void cap_express_link(struct device *d, int where, int type)
+{
+ u32 t;
+ u16 w;
+
+ t = get_conf_long(d, where + PCI_EXP_LNKCAP);
+ printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s, Latency L0 %s, L1 %s\n",
+ t >> 24,
+ link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
+ aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
+ latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
+ latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
+ printf("\t\t\tClockPM%c Suprise%c LLActRep%c BwNot%c\n",
+ FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
+ FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
+ FLAG(t, PCI_EXP_LNKCAP_DLLA),
+ FLAG(t, PCI_EXP_LNKCAP_LBNC));
+
+ w = get_conf_word(d, where + PCI_EXP_LNKCTL);
+ printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
+ if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
+ (type == PCI_EXP_TYPE_LEG_END))
+ printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
+ printf(" Disabled%c Retrain%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
+ FLAG(w, PCI_EXP_LNKCTL_DISABLE),
+ FLAG(w, PCI_EXP_LNKCTL_RETRAIN),
+ FLAG(w, PCI_EXP_LNKCTL_CLOCK),
+ FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
+ FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
+ FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
+ FLAG(w, PCI_EXP_LNKCTL_BWMIE),
+ FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
+
+ w = get_conf_word(d, where + PCI_EXP_LNKSTA);
+ printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
+ link_speed(w & PCI_EXP_LNKSTA_SPEED),
+ (w & PCI_EXP_LNKSTA_WIDTH) >> 4,
+ FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
+ FLAG(w, PCI_EXP_LNKSTA_TRAIN),
+ FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
+ FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
+ FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
+ FLAG(w, PCI_EXP_LNKSTA_AUTBW));
+}
+
+static const char *indicator(int code)
+{
+ static const char *names[] = { "Unknown", "On", "Blink", "Off" };
+ return names[code];
+}
+
+static void cap_express_slot(struct device *d, int where)
+{
+ u32 t;
+ u16 w;
+
+ t = get_conf_long(d, where + PCI_EXP_SLTCAP);
+ printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surpise%c\n",
+ FLAG(t, PCI_EXP_SLTCAP_ATNB),
+ FLAG(t, PCI_EXP_SLTCAP_PWRC),
+ FLAG(t, PCI_EXP_SLTCAP_MRL),
+ FLAG(t, PCI_EXP_SLTCAP_ATNI),
+ FLAG(t, PCI_EXP_SLTCAP_PWRI),
+ FLAG(t, PCI_EXP_SLTCAP_HPC),
+ FLAG(t, PCI_EXP_SLTCAP_HPS));
+ printf("\t\t\tSlot #%3x, PowerLimit %f; Interlock%c NoCompl%c\n",
+ t >> 19,
+ power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
+ FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
+ FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
+
+ w = get_conf_word(d, where + PCI_EXP_SLTCTL);
+ printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
+ FLAG(w, PCI_EXP_SLTCTL_ATNB),
+ FLAG(w, PCI_EXP_SLTCTL_PWRF),
+ FLAG(w, PCI_EXP_SLTCTL_MRLS),
+ FLAG(w, PCI_EXP_SLTCTL_PRSD),
+ FLAG(w, PCI_EXP_SLTCTL_CMDC),
+ FLAG(w, PCI_EXP_SLTCTL_HPIE),
+ FLAG(w, PCI_EXP_SLTCTL_LLCHG));
+ printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
+ indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
+ indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
+ FLAG(w, PCI_EXP_SLTCTL_PWRC),
+ FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
+
+ w = get_conf_word(d, where + PCI_EXP_SLTSTA);
+ printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
+ FLAG(w, PCI_EXP_SLTSTA_ATNB),
+ FLAG(w, PCI_EXP_SLTSTA_PWRF),
+ FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
+ FLAG(w, PCI_EXP_SLTSTA_CMDC),
+ FLAG(w, PCI_EXP_SLTSTA_PRES),
+ FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
+ printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
+ FLAG(w, PCI_EXP_SLTSTA_MRLS),
+ FLAG(w, PCI_EXP_SLTSTA_PRSD),
+ FLAG(w, PCI_EXP_SLTSTA_LLCHG));
+}
+
+static void cap_express_root(struct device *d, int where)
+{
+ u32 w = get_conf_word(d, where + PCI_EXP_RTCTL);
+ printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
+ FLAG(w, PCI_EXP_RTCTL_SECEE),
+ FLAG(w, PCI_EXP_RTCTL_SENFEE),
+ FLAG(w, PCI_EXP_RTCTL_SEFEE),
+ FLAG(w, PCI_EXP_RTCTL_PMEIE),
+ FLAG(w, PCI_EXP_RTCTL_CRSVIS));
+
+ w = get_conf_word(d, where + PCI_EXP_RTCAP);
+ printf("\t\tRootCap: CRSVisible%c\n",
+ FLAG(w, PCI_EXP_RTCAP_CRSVIS));
+
+ w = get_conf_word(d, where + PCI_EXP_RTSTA);
+ printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
+ w & PCI_EXP_RTSTA_PME_REQID,
+ FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
+ FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
+}
+
+static void
+cap_express(struct device *d, int where, int cap)
+{
+ int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
+ int size;
+ int slot = 0;
+
+ printf("Express ");
+ if (verbose >= 2)
+ printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
+ switch (type)
+ {
+ case PCI_EXP_TYPE_ENDPOINT:
+ printf("Endpoint");
+ break;
+ case PCI_EXP_TYPE_LEG_END:
+ printf("Legacy Endpoint");
+ break;
+ case PCI_EXP_TYPE_ROOT_PORT:
+ slot = cap & PCI_EXP_FLAGS_SLOT;
+ printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
+ break;
+ case PCI_EXP_TYPE_UPSTREAM:
+ printf("Upstream Port");
+ break;
+ case PCI_EXP_TYPE_DOWNSTREAM:
+ slot = cap & PCI_EXP_FLAGS_SLOT;
+ printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
+ break;
+ case PCI_EXP_TYPE_PCI_BRIDGE:
+ printf("PCI/PCI-X Bridge");
+ break;
+ case PCI_EXP_TYPE_PCIE_BRIDGE:
+ printf("PCI/PCI-X to PCI-Express Bridge");
+ break;
+ case PCI_EXP_TYPE_ROOT_INT_EP:
+ printf("Root Complex Integrated Endpoint");
+ break;
+ case PCI_EXP_TYPE_ROOT_EC:
+ printf("Root Complex Event Collector");
+ break;
+ default:
+ printf("Unknown type %d", type);
+ }
+ printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
+ if (verbose < 2)
+ return;
+
+ size = 16;
+ if (slot)
+ size = 24;
+ if (type == PCI_EXP_TYPE_ROOT_PORT)
+ size = 32;
+ if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
+ return;
+
+ cap_express_dev(d, where, type);
+ cap_express_link(d, where, type);
+ if (slot)
+ cap_express_slot(d, where);
+ if (type == PCI_EXP_TYPE_ROOT_PORT)
+ cap_express_root(d, where);