+static void
+cap_multicast(struct device *d, int where, int type)
+{
+ u16 w;
+ u32 l;
+ u64 bar, rcv, block;
+
+ printf("Multicast\n");
+ if (verbose < 2)
+ return;
+
+ if (!config_fetch(d, where + PCI_MCAST_CAP, 0x30))
+ return;
+
+ w = get_conf_word(d, where + PCI_MCAST_CAP);
+ printf("\t\tMcastCap: MaxGroups %d", PCI_MCAST_CAP_MAX_GROUP(w) + 1);
+ if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP)
+ printf(", WindowSz %d (%d bytes)",
+ PCI_MCAST_CAP_WIN_SIZE(w), 1 << PCI_MCAST_CAP_WIN_SIZE(w));
+ if (type == PCI_EXP_TYPE_ROOT_PORT ||
+ type == PCI_EXP_TYPE_UPSTREAM || type == PCI_EXP_TYPE_DOWNSTREAM)
+ printf(", ECRCRegen%c\n", FLAG(w, PCI_MCAST_CAP_ECRC));
+ w = get_conf_word(d, where + PCI_MCAST_CTRL);
+ printf("\t\tMcastCtl: NumGroups %d, Enable%c\n",
+ PCI_MCAST_CTRL_NUM_GROUP(w) + 1, FLAG(w, PCI_MCAST_CTRL_ENABLE));
+ bar = get_conf_long(d, where + PCI_MCAST_BAR);
+ l = get_conf_long(d, where + PCI_MCAST_BAR + 4);
+ bar |= (u64) l << 32;
+ printf("\t\tMcastBAR: IndexPos %d, BaseAddr %016" PCI_U64_FMT_X "\n",
+ PCI_MCAST_BAR_INDEX_POS(bar), bar & PCI_MCAST_BAR_MASK);
+ rcv = get_conf_long(d, where + PCI_MCAST_RCV);
+ l = get_conf_long(d, where + PCI_MCAST_RCV + 4);
+ rcv |= (u64) l << 32;
+ printf("\t\tMcastReceiveVec: %016" PCI_U64_FMT_X "\n", rcv);
+ block = get_conf_long(d, where + PCI_MCAST_BLOCK);
+ l = get_conf_long(d, where + PCI_MCAST_BLOCK + 4);
+ block |= (u64) l << 32;
+ printf("\t\tMcastBlockAllVec: %016" PCI_U64_FMT_X "\n", block);
+ block = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS);
+ l = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS + 4);
+ block |= (u64) l << 32;
+ printf("\t\tMcastBlockUntransVec: %016" PCI_U64_FMT_X "\n", block);
+
+ if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP)
+ return;
+ bar = get_conf_long(d, where + PCI_MCAST_OVL_BAR);
+ l = get_conf_long(d, where + PCI_MCAST_OVL_BAR + 4);
+ bar |= (u64) l << 32;
+ printf("\t\tMcastOverlayBAR: OverlaySize %d ", PCI_MCAST_OVL_SIZE(bar));
+ if (PCI_MCAST_OVL_SIZE(bar) >= 6)
+ printf("(%d bytes)", 1 << PCI_MCAST_OVL_SIZE(bar));
+ else
+ printf("(disabled)");
+ printf(", BaseAddr %016" PCI_U64_FMT_X "\n", bar & PCI_MCAST_OVL_MASK);
+}
+
+static void
+cap_vc(struct device *d, int where)
+{
+ u32 cr1, cr2;
+ u16 ctrl, status;
+ int evc_cnt;
+ int arb_table_pos;
+ int i, j;
+ static const char ref_clocks[][6] = { "100ns" };
+ static const char arb_selects[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "??4", "??5", "??6", "??7" };
+ static const char vc_arb_selects[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "??6", "??7" };
+ char buf[8];
+
+ printf("Virtual Channel\n");
+ if (verbose < 2)
+ return;
+
+ if (!config_fetch(d, where + 4, 0x1c - 4))
+ return;
+
+ cr1 = get_conf_long(d, where + PCI_VC_PORT_REG1);
+ cr2 = get_conf_long(d, where + PCI_VC_PORT_REG2);
+ ctrl = get_conf_word(d, where + PCI_VC_PORT_CTRL);
+ status = get_conf_word(d, where + PCI_VC_PORT_STATUS);
+
+ evc_cnt = BITS(cr1, 0, 3);
+ printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntryBits=%d\n",
+ BITS(cr1, 4, 3),
+ TABLE(ref_clocks, BITS(cr1, 8, 2), buf),
+ 1 << BITS(cr1, 10, 2));
+
+ printf("\t\tArb:");
+ for (i=0; i<8; i++)
+ if (arb_selects[i][0] != '?' || cr2 & (1 << i))
+ printf("%c%s%c", (i ? ' ' : '\t'), arb_selects[i], FLAG(cr2, 1 << i));
+ arb_table_pos = BITS(cr2, 24, 8);
+
+ printf("\n\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects, BITS(ctrl, 1, 3), buf));
+ printf("\t\tStatus:\tInProgress%c\n", FLAG(status, 1));
+
+ if (arb_table_pos)
+ {
+ arb_table_pos = where + 16*arb_table_pos;
+ printf("\t\tPort Arbitration Table [%x] <?>\n", arb_table_pos);
+ }
+
+ for (i=0; i<=evc_cnt; i++)
+ {
+ int pos = where + PCI_VC_RES_CAP + 12*i;
+ u32 rcap, rctrl;
+ u16 rstatus;
+ int pat_pos;
+
+ printf("\t\tVC%d:\t", i);
+ if (!config_fetch(d, pos, 12))
+ {
+ printf("<unreadable>\n");
+ continue;
+ }
+ rcap = get_conf_long(d, pos);
+ rctrl = get_conf_long(d, pos+4);
+ rstatus = get_conf_word(d, pos+10);
+
+ pat_pos = BITS(rcap, 24, 8);
+ printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n",
+ pat_pos,
+ BITS(rcap, 16, 6) + 1,
+ FLAG(rcap, 1 << 15));
+
+ printf("\t\t\tArb:");
+ for (j=0; j<8; j++)
+ if (vc_arb_selects[j][0] != '?' || rcap & (1 << j))
+ printf("%c%s%c", (j ? ' ' : '\t'), vc_arb_selects[j], FLAG(rcap, 1 << j));
+
+ printf("\n\t\t\tCtrl:\tEnable%c ID=%d ArbSelect=%s TC/VC=%02x\n",
+ FLAG(rctrl, 1 << 31),
+ BITS(rctrl, 24, 3),
+ TABLE(vc_arb_selects, BITS(rctrl, 17, 3), buf),
+ BITS(rctrl, 0, 8));
+
+ printf("\t\t\tStatus:\tNegoPending%c InProgress%c\n",
+ FLAG(rstatus, 2),
+ FLAG(rstatus, 1));
+
+ if (pat_pos)
+ printf("\t\t\tPort Arbitration Table <?>\n");
+ }
+}
+
+static void
+cap_rclink(struct device *d, int where)
+{
+ u32 esd;
+ int num_links;
+ int i;
+ static const char elt_types[][9] = { "Config", "Egress", "Internal" };
+ char buf[8];
+
+ printf("Root Complex Link\n");
+ if (verbose < 2)
+ return;
+
+ if (!config_fetch(d, where + 4, PCI_RCLINK_LINK1 - 4))
+ return;
+
+ esd = get_conf_long(d, where + PCI_RCLINK_ESD);
+ num_links = BITS(esd, 8, 8);
+ printf("\t\tDesc:\tPortNumber=%02x ComponentID=%02x EltType=%s\n",
+ BITS(esd, 24, 8),
+ BITS(esd, 16, 8),
+ TABLE(elt_types, BITS(esd, 0, 8), buf));
+
+ for (i=0; i<num_links; i++)
+ {
+ int pos = where + PCI_RCLINK_LINK1 + i*PCI_RCLINK_LINK_SIZE;
+ u32 desc;
+ u32 addr_lo, addr_hi;
+
+ printf("\t\tLink%d:\t", i);
+ if (!config_fetch(d, pos, PCI_RCLINK_LINK_SIZE))
+ {
+ printf("<unreadable>\n");
+ return;
+ }
+ desc = get_conf_long(d, pos + PCI_RCLINK_LINK_DESC);
+ addr_lo = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR);
+ addr_hi = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR + 4);
+
+ printf("Desc:\tTargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c\n",
+ BITS(desc, 24, 8),
+ BITS(desc, 16, 8),
+ FLAG(desc, 4),
+ ((desc & 2) ? "Config" : "MemMapped"),
+ FLAG(desc, 1));
+
+ if (desc & 2)
+ {
+ int n = addr_lo & 7;
+ if (!n)
+ n = 8;
+ printf("\t\t\tAddr:\t%02x:%02x.%d CfgSpace=%08x%08x\n",
+ BITS(addr_lo, 20, n),
+ BITS(addr_lo, 15, 5),
+ BITS(addr_lo, 12, 3),
+ addr_hi, addr_lo);
+ }
+ else
+ printf("\t\t\tAddr:\t%08x%08x\n", addr_hi, addr_lo);
+ }
+}
+
+static void
+cap_cxl(struct device *d, int where)
+{
+ u16 l;
+
+ printf("CXL Designated Vendor-Specific:\n");
+ if (verbose < 2)
+ return;
+
+ if (!config_fetch(d, where + PCI_CXL_CAP, 12))
+ return;
+
+ l = get_conf_word(d, where + PCI_CXL_CAP);
+ printf("\t\tCXLCap:\tCache%c IO%c Mem%c Mem HW Init%c HDMCount %d Viral%c\n",
+ FLAG(l, PCI_CXL_CAP_CACHE), FLAG(l, PCI_CXL_CAP_IO), FLAG(l, PCI_CXL_CAP_MEM),
+ FLAG(l, PCI_CXL_CAP_MEM_HWINIT), PCI_CXL_CAP_HDM_CNT(l), FLAG(l, PCI_CXL_CAP_VIRAL));
+
+ l = get_conf_word(d, where + PCI_CXL_CTRL);
+ printf("\t\tCXLCtl:\tCache%c IO%c Mem%c Cache SF Cov %d Cache SF Gran %d Cache Clean%c Viral%c\n",
+ FLAG(l, PCI_CXL_CTRL_CACHE), FLAG(l, PCI_CXL_CTRL_IO), FLAG(l, PCI_CXL_CTRL_MEM),
+ PCI_CXL_CTRL_CACHE_SF_COV(l), PCI_CXL_CTRL_CACHE_SF_GRAN(l), FLAG(l, PCI_CXL_CTRL_CACHE_CLN),
+ FLAG(l, PCI_CXL_CTRL_VIRAL));
+
+ l = get_conf_word(d, where + PCI_CXL_STATUS);
+ printf("\t\tCXLSta:\tViral%c\n", FLAG(l, PCI_CXL_STATUS_VIRAL));
+}
+
+static int
+is_cxl_cap(struct device *d, int where)
+{
+ u32 hdr;
+ u16 w;
+
+ if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8))
+ return 0;
+
+ /* Check for supported Vendor */
+ hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1);
+ w = BITS(hdr, 0, 16);
+ if (w != PCI_VENDOR_ID_INTEL)
+ return 0;
+
+ /* Check for Designated Vendor-Specific ID */
+ hdr = get_conf_long(d, where + PCI_DVSEC_HEADER2);
+ w = BITS(hdr, 0, 16);
+ if (w == PCI_DVSEC_INTEL_CXL)
+ return 1;
+
+ return 0;
+}
+
+static void
+cap_dvsec(struct device *d, int where)
+{
+ u32 hdr;
+
+ printf("Designated Vendor-Specific:\n");
+ if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8))
+ {
+ printf("<unreadable>\n");
+ return;
+ }
+
+ hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1);
+ printf("\t\tDVSEC Vendor ID=%04x Rev=%d Len=%03x <?>\n",
+ BITS(hdr, 0, 16),
+ BITS(hdr, 16, 4),
+ BITS(hdr, 20, 12));
+
+ hdr = get_conf_long(d, where + PCI_DVSEC_HEADER2);
+ printf("\t\tDVSEC ID=%04x <?>\n",
+ BITS(hdr, 0, 16));
+}
+
+static void
+cap_evendor(struct device *d, int where)
+{
+ u32 hdr;
+
+ printf("Vendor Specific Information: ");
+ if (!config_fetch(d, where + PCI_EVNDR_HEADER, 4))
+ {
+ printf("<unreadable>\n");
+ return;
+ }
+
+ hdr = get_conf_long(d, where + PCI_EVNDR_HEADER);
+ printf("ID=%04x Rev=%d Len=%03x <?>\n",
+ BITS(hdr, 0, 16),
+ BITS(hdr, 16, 4),
+ BITS(hdr, 20, 12));
+}
+
+static int l1pm_calc_pwron(int scale, int value)
+{
+ switch (scale)
+ {
+ case 0:
+ return 2 * value;
+ case 1:
+ return 10 * value;
+ case 2:
+ return 100 * value;
+ }
+ return -1;
+}
+
+static void
+cap_l1pm(struct device *d, int where)
+{
+ u32 l1_cap, val, scale;
+ int time;
+
+ printf("L1 PM Substates\n");
+
+ if (verbose < 2)
+ return;
+
+ if (!config_fetch(d, where + PCI_L1PM_SUBSTAT_CAP, 12))
+ {
+ printf("\t\t<unreadable>\n");
+ return;
+ }
+
+ l1_cap = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CAP);
+ printf("\t\tL1SubCap: ");
+ printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n",
+ FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L12),
+ FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L11),
+ FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L12),
+ FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L11),
+ FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP));
+
+ if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
+ {
+ printf("\t\t\t PortCommonModeRestoreTime=%dus ", BITS(l1_cap, 8, 8));
+ time = l1pm_calc_pwron(BITS(l1_cap, 16, 2), BITS(l1_cap, 19, 5));
+ if (time != -1)
+ printf("PortTPowerOnTime=%dus\n", time);
+ else
+ printf("PortTPowerOnTime=<error>\n");
+ }
+
+ val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL1);
+ printf("\t\tL1SubCtl1: PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n",
+ FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L12),
+ FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L11),
+ FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12),
+ FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11));
+
+ if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
+ {
+ printf("\t\t\t T_CommonMode=%dus", BITS(val, 8, 8));
+
+ if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
+ {
+ scale = BITS(val, 29, 3);
+ if (scale > 5)
+ printf(" LTR1.2_Threshold=<error>");
+ else
+ printf(" LTR1.2_Threshold=%lldns", BITS(val, 16, 10) * (unsigned long long) cap_ltr_scale(scale));
+ }
+ printf("\n");
+ }
+
+ val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2);
+ printf("\t\tL1SubCtl2:");
+ if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
+ {
+ time = l1pm_calc_pwron(BITS(val, 0, 2), BITS(val, 3, 5));
+ if (time != -1)
+ printf(" T_PwrOn=%dus", time);
+ else
+ printf(" T_PwrOn=<error>");
+ }
+ printf("\n");
+}
+
+static void
+cap_ptm(struct device *d, int where)
+{
+ u32 buff;
+ u16 clock;
+
+ printf("Precision Time Measurement\n");
+
+ if (verbose < 2)
+ return;
+
+ if (!config_fetch(d, where + 4, 8))
+ {
+ printf("\t\t<unreadable>\n");
+ return;
+ }
+
+ buff = get_conf_long(d, where + 4);
+ printf("\t\tPTMCap: ");
+ printf("Requester:%c Responder:%c Root:%c\n",
+ FLAG(buff, 0x1),
+ FLAG(buff, 0x2),
+ FLAG(buff, 0x4));
+
+ clock = BITS(buff, 8, 8);
+ printf("\t\tPTMClockGranularity: ");
+ switch (clock)
+ {
+ case 0x00:
+ printf("Unimplemented\n");
+ break;
+ case 0xff:
+ printf("Greater than 254ns\n");
+ break;
+ default:
+ printf("%huns\n", clock);
+ }
+
+ buff = get_conf_long(d, where + 8);
+ printf("\t\tPTMControl: ");
+ printf("Enabled:%c RootSelected:%c\n",
+ FLAG(buff, 0x1),
+ FLAG(buff, 0x2));
+
+ clock = BITS(buff, 8, 8);
+ printf("\t\tPTMEffectiveGranularity: ");
+ switch (clock)
+ {
+ case 0x00:
+ printf("Unknown\n");
+ break;
+ case 0xff:
+ printf("Greater than 254ns\n");
+ break;
+ default:
+ printf("%huns\n", clock);
+ }
+}
+