+ FLAG(w, PCI_CXL_DEV_CTRL_CACHE), FLAG(w, PCI_CXL_DEV_CTRL_IO), FLAG(w, PCI_CXL_DEV_CTRL_MEM),
+ PCI_CXL_DEV_CTRL_CACHE_SF_COV(w), PCI_CXL_DEV_CTRL_CACHE_SF_GRAN(w), FLAG(w, PCI_CXL_DEV_CTRL_CACHE_CLN),
+ FLAG(w, PCI_CXL_DEV_CTRL_VIRAL));
+
+ w = get_conf_word(d, where + PCI_CXL_DEV_STATUS);
+ printf("\t\tCXLSta:\tViral%c\n", FLAG(w, PCI_CXL_DEV_STATUS_VIRAL));
+
+ w = get_conf_word(d, where + PCI_CXL_DEV_STATUS2);
+ printf("\t\tCXLSta2:\tResetComplete%c ResetError%c PMComplete%c\n",
+ FLAG(w, PCI_CXL_DEV_STATUS_RC), FLAG(w,PCI_CXL_DEV_STATUS_RE), FLAG(w, PCI_CXL_DEV_STATUS_PMC));
+
+ w = get_conf_word(d, where + PCI_CXL_DEV_CAP2);
+ cache_unit_size = BITS(w, 0, 4);
+ cache_size = BITS(w, 8, 8);
+ switch (cache_unit_size)
+ {
+ case PCI_CXL_DEV_CAP2_CACHE_1M:
+ printf("\t\tCache Size: %08x\n", cache_size * (1<<20));
+ break;
+ case PCI_CXL_DEV_CAP2_CACHE_64K:
+ printf("\t\tCache Size: %08x\n", cache_size * (64<<10));
+ break;
+ case PCI_CXL_DEV_CAP2_CACHE_UNK:
+ printf("\t\tCache Size Not Reported\n");
+ break;
+ default:
+ printf("\t\tCache Size: %d of unknown unit size (%d)\n", cache_size, cache_unit_size);
+ break;
+ }
+
+ l = get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_HI);
+ range_size = (u64) l << 32;
+ l = get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_LO);
+ range_size |= l;
+ l = get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_HI);
+ range_base = (u64) l << 32;
+ l = get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_LO);
+ range_base |= l;
+ cxl_range(range_base, range_size, 1);
+
+ l = get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_HI);
+ range_size = (u64) l << 32;
+ l = get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_LO);
+ range_size |= l;
+ l = get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_HI);
+ range_base = (u64) l << 32;
+ l = get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_LO);
+ range_base |= l;
+ cxl_range(range_base, range_size, 2);
+}
+
+static void
+dvsec_cxl_port(struct device *d, int where)
+{
+ u16 w, m1, m2;
+ u8 b1, b2;
+
+ w = get_conf_word(d, where + PCI_CXL_PORT_EXT_STATUS);
+ printf("\t\tCXLPortSta:\tPMComplete%c\n", FLAG(w, PCI_CXL_PORT_EXT_STATUS));
+
+ w = get_conf_word(d, where + PCI_CXL_PORT_CTRL);
+ printf("\t\tCXLPortCtl:\tUnmaskSBR%c UnmaskLinkDisable%c AltMem%c AltBME%c ViralEnable%c\n",
+ FLAG(w, PCI_CXL_PORT_UNMASK_SBR), FLAG(w, PCI_CXL_PORT_UNMASK_LINK),
+ FLAG(w, PCI_CXL_PORT_ALT_MEMORY), FLAG(w, PCI_CXL_PORT_ALT_BME),
+ FLAG(w, PCI_CXL_PORT_VIRAL_EN));
+
+ b1 = get_conf_byte(d, where + PCI_CXL_PORT_ALT_BUS_BASE);
+ b2 = get_conf_byte(d, where + PCI_CXL_PORT_ALT_BUS_LIMIT);
+ printf("\t\tAlternateBus:\t%02x-%02x\n", b1, b2);
+ m1 = get_conf_word(d, where + PCI_CXL_PORT_ALT_MEM_BASE);
+ m2 = get_conf_word(d, where + PCI_CXL_PORT_ALT_MEM_LIMIT);
+ printf("\t\tAlternateBus:\t%04x-%04x\n", m1, m2);
+}
+
+static const char *id[] = {
+ "empty",
+ "component registers",
+ "BAR virtualization",
+ "CXL device registers"};
+
+static inline void
+dvsec_decode_block(uint32_t lo, uint32_t hi, char which)
+{
+ u64 base_hi = hi, base_lo;
+ u8 bir, block_id;
+
+ bir = BITS(lo, 0, 3);
+ block_id = BITS(lo, 8, 8);
+ base_lo = BITS(lo, 16, 16);
+
+ if (!block_id)
+ return;
+
+ printf("\t\tBlock%c\tBIR: bar%d\tID: %s\n", which, bir, id[block_id]);
+ printf("\t\t\tRegisterOffset: %016" PCI_U64_FMT_X "\n", (base_hi << 32ULL) | base_lo << 16);
+}
+
+static void
+dvsec_cxl_register_locator(struct device *d, int where, int len)
+{
+ int i, j;
+
+ for (i = 0xc, j = 1; i < len; i += 8, j++) {
+ dvsec_decode_block(get_conf_long(d, where + i), get_conf_long(d, where + i + 4), j + 0x31);
+ }
+}
+
+static void
+cap_dvsec_cxl(struct device *d, int id, int where)
+{
+ u16 len;
+ u8 rev;
+
+ printf(": CXL\n");
+ if (verbose < 2)
+ return;
+
+ rev = BITS(get_conf_byte(d, where + 0x6), 0, 4);