Released as 3.9.0

[pciutils.git] / lib / i386-ports.c

diff --git a/lib/i386-ports.c b/lib/i386-ports.c
index 0b1677a236c7320139f1dafb2f3f2959a0bace47..0ca87ddda2ab731448dcd12912fc644eda7425e8 100644 (file)
--- a/lib/i386-ports.c
+++ b/lib/i386-ports.c
@@ -10,7 +10,7 @@
 
 #include "internal.h"
 
 
 #include "internal.h"
 

-#include <unistd.h>
+#include <string.h>

 
 #if defined(PCI_OS_LINUX)
 #include "i386-io-linux.h"
 
 #if defined(PCI_OS_LINUX)
 #include "i386-io-linux.h"


@@ -50,10 +50,13 @@ conf12_init(struct pci_access *a)
 }
 
 static void
 }
 
 static void

-conf12_cleanup(struct pci_access *a UNUSED)
+conf12_cleanup(struct pci_access *a)

 {
   if (conf12_io_enabled > 0)
 {
   if (conf12_io_enabled > 0)

-    conf12_io_enabled = intel_cleanup_io(a);
+    {
+      intel_cleanup_io(a);
+      conf12_io_enabled = -1;
+    }

 }
 
 /*
 }
 
 /*


@@ -72,6 +75,7 @@ intel_sanity_check(struct pci_access *a, struct pci_methods *m)
 {
   struct pci_dev d;
 
 {
   struct pci_dev d;
 

+  memset(&d, 0, sizeof(d));

   a->debug("...sanity check");
   d.bus = 0;
   d.func = 0;
   a->debug("...sanity check");
   d.bus = 0;
   d.func = 0;


@@ -129,9 +133,12 @@ conf1_read(struct pci_dev *d, int pos, byte *buf, int len)
   int addr = 0xcfc + (pos&3);
   int res = 1;
 
   int addr = 0xcfc + (pos&3);
   int res = 1;
 

-  if (pos >= 256)
+  if (d->domain || pos >= 256)

     return 0;
 
     return 0;
 

+  if (len != 1 && len != 2 && len != 4)
+    return pci_generic_block_read(d, pos, buf, len);
+

   intel_io_lock();
   outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
 
   intel_io_lock();
   outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
 


@@ -146,8 +153,6 @@ conf1_read(struct pci_dev *d, int pos, byte *buf, int len)
     case 4:
       ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
       break;
     case 4:
       ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
       break;

-    default:
-      res = pci_generic_block_read(d, pos, buf, len);

     }
 
   intel_io_unlock();
     }
 
   intel_io_unlock();


@@ -160,9 +165,12 @@ conf1_write(struct pci_dev *d, int pos, byte *buf, int len)
   int addr = 0xcfc + (pos&3);
   int res = 1;
 
   int addr = 0xcfc + (pos&3);
   int res = 1;
 

-  if (pos >= 256)
+  if (d->domain || pos >= 256)

     return 0;
 
     return 0;
 

+  if (len != 1 && len != 2 && len != 4)
+    return pci_generic_block_write(d, pos, buf, len);
+

   intel_io_lock();
   outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
 
   intel_io_lock();
   outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
 


@@ -177,8 +185,6 @@ conf1_write(struct pci_dev *d, int pos, byte *buf, int len)
     case 4:
       outl(le32_to_cpu(((u32 *) buf)[0]), addr);
       break;
     case 4:
       outl(le32_to_cpu(((u32 *) buf)[0]), addr);
       break;

-    default:
-      res = pci_generic_block_write(d, pos, buf, len);

     }
   intel_io_unlock();
   return res;
     }
   intel_io_unlock();
   return res;


@@ -217,13 +223,16 @@ conf2_read(struct pci_dev *d, int pos, byte *buf, int len)
   int res = 1;
   int addr = 0xc000 | (d->dev << 8) | pos;
 
   int res = 1;
   int addr = 0xc000 | (d->dev << 8) | pos;
 

-  if (pos >= 256)
+  if (d->domain || pos >= 256)

     return 0;
 
   if (d->dev >= 16)
     /* conf2 supports only 16 devices per bus */
     return 0;
 
     return 0;
 
   if (d->dev >= 16)
     /* conf2 supports only 16 devices per bus */
     return 0;
 

+  if (len != 1 && len != 2 && len != 4)
+    return pci_generic_block_read(d, pos, buf, len);
+

   intel_io_lock();
   outb((d->func << 1) | 0xf0, 0xcf8);
   outb(d->bus, 0xcfa);
   intel_io_lock();
   outb((d->func << 1) | 0xf0, 0xcf8);
   outb(d->bus, 0xcfa);


@@ -238,8 +247,6 @@ conf2_read(struct pci_dev *d, int pos, byte *buf, int len)
     case 4:
       ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
       break;
     case 4:
       ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
       break;

-    default:
-      res = pci_generic_block_read(d, pos, buf, len);

     }
   outb(0, 0xcf8);
   intel_io_unlock();
     }
   outb(0, 0xcf8);
   intel_io_unlock();


@@ -252,11 +259,15 @@ conf2_write(struct pci_dev *d, int pos, byte *buf, int len)
   int res = 1;
   int addr = 0xc000 | (d->dev << 8) | pos;
 
   int res = 1;
   int addr = 0xc000 | (d->dev << 8) | pos;
 

-  if (pos >= 256)
+  if (d->domain || pos >= 256)

     return 0;
 
   if (d->dev >= 16)
     return 0;
 
   if (d->dev >= 16)

-    d->access->error("conf2_write: only first 16 devices exist.");
+    /* conf2 supports only 16 devices per bus */
+    return 0;
+
+  if (len != 1 && len != 2 && len != 4)
+    return pci_generic_block_write(d, pos, buf, len);

 
   intel_io_lock();
   outb((d->func << 1) | 0xf0, 0xcf8);
 
   intel_io_lock();
   outb((d->func << 1) | 0xf0, 0xcf8);


@@ -272,8 +283,6 @@ conf2_write(struct pci_dev *d, int pos, byte *buf, int len)
     case 4:
       outl(le32_to_cpu(* (u32 *) buf), addr);
       break;
     case 4:
       outl(le32_to_cpu(* (u32 *) buf), addr);
       break;

-    default:
-      res = pci_generic_block_write(d, pos, buf, len);

     }
 
   outb(0, 0xcf8);
     }
 
   outb(0, 0xcf8);