#define PCI_HT_SEC_CMD 2 /* Command Register */
#define PCI_HT_SEC_CMD_WR 0x0001 /* Warm Reset */
#define PCI_HT_SEC_CMD_DE 0x0002 /* Double-Ended */
#define PCI_HT_SEC_CMD 2 /* Command Register */
#define PCI_HT_SEC_CMD_WR 0x0001 /* Warm Reset */
#define PCI_HT_SEC_CMD_DE 0x0002 /* Double-Ended */
#define PCI_HT_SEC_CMD_CS 0x0080 /* Chain Side */
#define PCI_HT_SEC_CMD_HH 0x0100 /* Host Hide */
#define PCI_HT_SEC_CMD_AS 0x0400 /* Act as Slave */
#define PCI_HT_SEC_CMD_CS 0x0080 /* Chain Side */
#define PCI_HT_SEC_CMD_HH 0x0100 /* Host Hide */
#define PCI_HT_SEC_CMD_AS 0x0400 /* Act as Slave */
/* Access Control Services */
#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
#define PCI_ACS_CAP_VALID 0x0001 /* ACS Source Validation */
/* Access Control Services */
#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
#define PCI_ACS_CAP_VALID 0x0001 /* ACS Source Validation */
#define PCI_L1PM_SUBSTAT_CAP_PM_L11 0x2 /* PCI-PM L1.1 Supported */
#define PCI_L1PM_SUBSTAT_CAP_ASPM_L12 0x4 /* ASPM L1.2 Supported */
#define PCI_L1PM_SUBSTAT_CAP_ASPM_L11 0x8 /* ASPM L1.1 Supported */
#define PCI_L1PM_SUBSTAT_CAP_PM_L11 0x2 /* PCI-PM L1.1 Supported */
#define PCI_L1PM_SUBSTAT_CAP_ASPM_L12 0x4 /* ASPM L1.2 Supported */
#define PCI_L1PM_SUBSTAT_CAP_ASPM_L11 0x8 /* ASPM L1.1 Supported */
#define PCI_L1PM_SUBSTAT_CTL1 0x8 /* L1 PM Substate Control 1 */
#define PCI_L1PM_SUBSTAT_CTL1_PM_L12 0x1 /* PCI-PM L1.2 Enable */
#define PCI_L1PM_SUBSTAT_CTL1_PM_L11 0x2 /* PCI-PM L1.1 Enable */
#define PCI_L1PM_SUBSTAT_CTL1 0x8 /* L1 PM Substate Control 1 */
#define PCI_L1PM_SUBSTAT_CTL1_PM_L12 0x1 /* PCI-PM L1.2 Enable */
#define PCI_L1PM_SUBSTAT_CTL1_PM_L11 0x2 /* PCI-PM L1.1 Enable */