lspci: Add L1 PM Substate capability reporting

[pciutils.git] / lib / header.h

diff --git a/lib/header.h b/lib/header.h
index d820a0c2fae083fb09cadef2f57f4f89917b5102..660800375fcbd539fc033161fd5ae29c9b792ef6 100644 (file)
--- a/lib/header.h
+++ b/lib/header.h
@@ -1,7 +1,7 @@
 /*
  *     The PCI Library -- PCI Header Structure (based on <linux/pci.h>)
  *
 /*
  *     The PCI Library -- PCI Header Structure (based on <linux/pci.h>)
  *

- *     Copyright (c) 1997--2007 Martin Mares <mj@ucw.cz>
+ *     Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz>

  *
  *     Can be freely distributed and used under the terms of the GNU GPL.
  */
  *
  *     Can be freely distributed and used under the terms of the GNU GPL.
  */


@@ -144,7 +144,8 @@
 #define  PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN 0x800    /* PCI-X? */
 
 /* Header type 2 (CardBus bridges) */
 #define  PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN 0x800    /* PCI-X? */
 
 /* Header type 2 (CardBus bridges) */

-/* 0x14-0x15 reserved */
+#define PCI_CB_CAPABILITY_LIST 0x14
+/* 0x15 reserved */

 #define PCI_CB_SEC_STATUS      0x16    /* Secondary status */
 #define PCI_CB_PRIMARY_BUS     0x18    /* PCI bus number */
 #define PCI_CB_CARD_BUS                0x19    /* CardBus bus number */
 #define PCI_CB_SEC_STATUS      0x16    /* Secondary status */
 #define PCI_CB_PRIMARY_BUS     0x18    /* PCI bus number */
 #define PCI_CB_CARD_BUS                0x19    /* CardBus bus number */


@@ -187,17 +188,21 @@
 #define  PCI_CAP_ID_AGP                0x02    /* Accelerated Graphics Port */
 #define  PCI_CAP_ID_VPD                0x03    /* Vital Product Data */
 #define  PCI_CAP_ID_SLOTID     0x04    /* Slot Identification */
 #define  PCI_CAP_ID_AGP                0x02    /* Accelerated Graphics Port */
 #define  PCI_CAP_ID_VPD                0x03    /* Vital Product Data */
 #define  PCI_CAP_ID_SLOTID     0x04    /* Slot Identification */

-#define  PCI_CAP_ID_MSI                0x05    /* Message Signalled Interrupts */
+#define  PCI_CAP_ID_MSI                0x05    /* Message Signaled Interrupts */

 #define  PCI_CAP_ID_CHSWP      0x06    /* CompactPCI HotSwap */
 #define  PCI_CAP_ID_PCIX        0x07    /* PCI-X */
 #define  PCI_CAP_ID_HT          0x08    /* HyperTransport */
 #define  PCI_CAP_ID_VNDR       0x09    /* Vendor specific */
 #define  PCI_CAP_ID_DBG                0x0A    /* Debug port */
 #define  PCI_CAP_ID_CCRC       0x0B    /* CompactPCI Central Resource Control */
 #define  PCI_CAP_ID_CHSWP      0x06    /* CompactPCI HotSwap */
 #define  PCI_CAP_ID_PCIX        0x07    /* PCI-X */
 #define  PCI_CAP_ID_HT          0x08    /* HyperTransport */
 #define  PCI_CAP_ID_VNDR       0x09    /* Vendor specific */
 #define  PCI_CAP_ID_DBG                0x0A    /* Debug port */
 #define  PCI_CAP_ID_CCRC       0x0B    /* CompactPCI Central Resource Control */

+#define  PCI_CAP_ID_HOTPLUG    0x0C    /* PCI hot-plug */

 #define  PCI_CAP_ID_SSVID      0x0D    /* Bridge subsystem vendor/device ID */
 #define  PCI_CAP_ID_AGP3       0x0E    /* AGP 8x */
 #define  PCI_CAP_ID_SSVID      0x0D    /* Bridge subsystem vendor/device ID */
 #define  PCI_CAP_ID_AGP3       0x0E    /* AGP 8x */

+#define  PCI_CAP_ID_SECURE     0x0F    /* Secure device (?) */

 #define  PCI_CAP_ID_EXP                0x10    /* PCI Express */
 #define  PCI_CAP_ID_MSIX       0x11    /* MSI-X */
 #define  PCI_CAP_ID_EXP                0x10    /* PCI Express */
 #define  PCI_CAP_ID_MSIX       0x11    /* MSI-X */

+#define  PCI_CAP_ID_SATA       0x12    /* Serial-ATA HBA */
+#define  PCI_CAP_ID_AF         0x13    /* Advanced features of PCI devices integrated in PCIe root cplx */

 #define PCI_CAP_LIST_NEXT      1       /* Next capability in the list */
 #define PCI_CAP_FLAGS          2       /* Capability defined flags (16 bits) */
 #define PCI_CAP_SIZEOF         4
 #define PCI_CAP_LIST_NEXT      1       /* Next capability in the list */
 #define PCI_CAP_FLAGS          2       /* Capability defined flags (16 bits) */
 #define PCI_CAP_SIZEOF         4


@@ -208,6 +213,22 @@
 #define PCI_EXT_CAP_ID_VC      0x02    /* Virtual Channel */
 #define PCI_EXT_CAP_ID_DSN     0x03    /* Device Serial Number */
 #define PCI_EXT_CAP_ID_PB      0x04    /* Power Budgeting */
 #define PCI_EXT_CAP_ID_VC      0x02    /* Virtual Channel */
 #define PCI_EXT_CAP_ID_DSN     0x03    /* Device Serial Number */
 #define PCI_EXT_CAP_ID_PB      0x04    /* Power Budgeting */

+#define PCI_EXT_CAP_ID_RCLINK  0x05    /* Root Complex Link Declaration */
+#define PCI_EXT_CAP_ID_RCILINK 0x06    /* Root Complex Internal Link Declaration */
+#define PCI_EXT_CAP_ID_RCECOLL 0x07    /* Root Complex Event Collector */
+#define PCI_EXT_CAP_ID_MFVC    0x08    /* Multi-Function Virtual Channel */
+#define PCI_EXT_CAP_ID_VC2     0x09    /* Virtual Channel (2nd ID) */
+#define PCI_EXT_CAP_ID_RBCB    0x0a    /* Root Bridge Control Block */
+#define PCI_EXT_CAP_ID_VNDR    0x0b    /* Vendor specific */
+#define PCI_EXT_CAP_ID_ACS     0x0d    /* Access Controls */
+#define PCI_EXT_CAP_ID_ARI     0x0e    /* Alternative Routing-ID Interpretation */
+#define PCI_EXT_CAP_ID_ATS     0x0f    /* Address Translation Service */
+#define PCI_EXT_CAP_ID_SRIOV   0x10    /* Single Root I/O Virtualization */
+#define PCI_EXT_CAP_ID_TPH     0x17    /* Transaction processing hints */
+#define PCI_EXT_CAP_ID_LTR     0x18    /* Latency Tolerance Reporting */
+#define PCI_EXT_CAP_ID_L1PM    0x1e    /* L1 PM Substates */
+
+/*** Definitions of capabilities ***/

 
 /* Power Management Registers */
 
 
 /* Power Management Registers */
 


@@ -224,6 +245,7 @@
 #define  PCI_PM_CAP_PME_D3_COLD        0x8000  /* PME can be asserted from D3cold */
 #define PCI_PM_CTRL            4       /* PM control and status register */
 #define  PCI_PM_CTRL_STATE_MASK        0x0003  /* Current power state (D0 to D3) */
 #define  PCI_PM_CAP_PME_D3_COLD        0x8000  /* PME can be asserted from D3cold */
 #define PCI_PM_CTRL            4       /* PM control and status register */
 #define  PCI_PM_CTRL_STATE_MASK        0x0003  /* Current power state (D0 to D3) */

+#define  PCI_PM_CTRL_NO_SOFT_RST       0x0008  /* No Soft Reset from D3hot to D0 */

 #define  PCI_PM_CTRL_PME_ENABLE        0x0100  /* PME pin enable */
 #define  PCI_PM_CTRL_DATA_SEL_MASK     0x1e00  /* PM table data index */
 #define  PCI_PM_CTRL_DATA_SCALE_MASK   0x6000  /* PM table data scaling factor */
 #define  PCI_PM_CTRL_PME_ENABLE        0x0100  /* PME pin enable */
 #define  PCI_PM_CTRL_DATA_SEL_MASK     0x1e00  /* PM table data index */
 #define  PCI_PM_CTRL_DATA_SCALE_MASK   0x6000  /* PM table data scaling factor */


@@ -267,6 +289,13 @@
 #define  PCI_AGP_COMMAND_RATE1 0x0001  /* Use 1x rate (4x in AGP3 mode) */
 #define PCI_AGP_SIZEOF         12
 
 #define  PCI_AGP_COMMAND_RATE1 0x0001  /* Use 1x rate (4x in AGP3 mode) */
 #define PCI_AGP_SIZEOF         12
 

+/* Vital Product Data */
+
+#define PCI_VPD_ADDR           2       /* Address to access (15 bits!) */
+#define  PCI_VPD_ADDR_MASK     0x7fff  /* Address mask */
+#define  PCI_VPD_ADDR_F                0x8000  /* Write 0, 1 indicates completion */
+#define PCI_VPD_DATA           4       /* 32-bits of data returned here */
+

 /* Slot Identification */
 
 #define PCI_SID_ESR            2       /* Expansion Slot Register */
 /* Slot Identification */
 
 #define PCI_SID_ESR            2       /* Expansion Slot Register */


@@ -274,7 +303,7 @@
 #define  PCI_SID_ESR_FIC       0x20    /* First In Chassis Flag */
 #define PCI_SID_CHASSIS_NR     3       /* Chassis Number */
 
 #define  PCI_SID_ESR_FIC       0x20    /* First In Chassis Flag */
 #define PCI_SID_CHASSIS_NR     3       /* Chassis Number */
 

-/* Message Signalled Interrupts registers */
+/* Message Signaled Interrupts registers */

 
 #define PCI_MSI_FLAGS          2       /* Various flags */
 #define  PCI_MSI_FLAGS_MASK_BIT        0x100   /* interrupt masking & reporting supported */
 
 #define PCI_MSI_FLAGS          2       /* Various flags */
 #define  PCI_MSI_FLAGS_MASK_BIT        0x100   /* interrupt masking & reporting supported */


@@ -687,6 +716,9 @@
 #define PCI_HT_RM_CNT1         10      /* Retry Count 1 Register */
 #define PCI_HT_RM_SIZEOF       12
 
 #define PCI_HT_RM_CNT1         10      /* Retry Count 1 Register */
 #define PCI_HT_RM_SIZEOF       12
 

+/* Vendor-Specific Capability (see PCI_EVNDR_xxx for the PCIe version) */
+#define PCI_VNDR_LENGTH                2       /* Length byte */
+

 /* PCI Express */
 #define PCI_EXP_FLAGS          0x2     /* Capabilities register */
 #define PCI_EXP_FLAGS_VERS     0x000f  /* Capability version */
 /* PCI Express */
 #define PCI_EXP_FLAGS          0x2     /* Capabilities register */
 #define PCI_EXP_FLAGS_VERS     0x000f  /* Capability version */


@@ -711,8 +743,10 @@
 #define  PCI_EXP_DEVCAP_ATN_BUT        0x1000  /* Attention Button Present */
 #define  PCI_EXP_DEVCAP_ATN_IND        0x2000  /* Attention Indicator Present */
 #define  PCI_EXP_DEVCAP_PWR_IND        0x4000  /* Power Indicator Present */
 #define  PCI_EXP_DEVCAP_ATN_BUT        0x1000  /* Attention Button Present */
 #define  PCI_EXP_DEVCAP_ATN_IND        0x2000  /* Attention Indicator Present */
 #define  PCI_EXP_DEVCAP_PWR_IND        0x4000  /* Power Indicator Present */

+#define  PCI_EXP_DEVCAP_RBE    0x8000  /* Role-Based Error Reporting */

 #define  PCI_EXP_DEVCAP_PWR_VAL        0x3fc0000 /* Slot Power Limit Value */
 #define  PCI_EXP_DEVCAP_PWR_SCL        0xc000000 /* Slot Power Limit Scale */
 #define  PCI_EXP_DEVCAP_PWR_VAL        0x3fc0000 /* Slot Power Limit Value */
 #define  PCI_EXP_DEVCAP_PWR_SCL        0xc000000 /* Slot Power Limit Scale */

+#define  PCI_EXP_DEVCAP_FLRESET        0x10000000 /* Function-Level Reset */

 #define PCI_EXP_DEVCTL         0x8     /* Device Control */
 #define  PCI_EXP_DEVCTL_CERE   0x0001  /* Correctable Error Reporting En. */
 #define  PCI_EXP_DEVCTL_NFERE  0x0002  /* Non-Fatal Error Reporting Enable */
 #define PCI_EXP_DEVCTL         0x8     /* Device Control */
 #define  PCI_EXP_DEVCTL_CERE   0x0001  /* Correctable Error Reporting En. */
 #define  PCI_EXP_DEVCTL_NFERE  0x0002  /* Non-Fatal Error Reporting Enable */


@@ -725,6 +759,8 @@
 #define  PCI_EXP_DEVCTL_AUX_PME        0x0400  /* Auxiliary Power PM Enable */
 #define  PCI_EXP_DEVCTL_NOSNOOP        0x0800  /* Enable No Snoop */
 #define  PCI_EXP_DEVCTL_READRQ 0x7000  /* Max_Read_Request_Size */
 #define  PCI_EXP_DEVCTL_AUX_PME        0x0400  /* Auxiliary Power PM Enable */
 #define  PCI_EXP_DEVCTL_NOSNOOP        0x0800  /* Enable No Snoop */
 #define  PCI_EXP_DEVCTL_READRQ 0x7000  /* Max_Read_Request_Size */

+#define  PCI_EXP_DEVCTL_BCRE   0x8000  /* Bridge Configuration Retry Enable */
+#define  PCI_EXP_DEVCTL_FLRESET        0x8000  /* Function-Level Reset [bit shared with BCRE] */

 #define PCI_EXP_DEVSTA         0xa     /* Device Status */
 #define  PCI_EXP_DEVSTA_CED    0x01    /* Correctable Error Detected */
 #define  PCI_EXP_DEVSTA_NFED   0x02    /* Non-Fatal Error Detected */
 #define PCI_EXP_DEVSTA         0xa     /* Device Status */
 #define  PCI_EXP_DEVSTA_CED    0x01    /* Correctable Error Detected */
 #define  PCI_EXP_DEVSTA_NFED   0x02    /* Non-Fatal Error Detected */


@@ -738,6 +774,10 @@
 #define  PCI_EXP_LNKCAP_ASPM   0x00c00 /* Active State Power Management */
 #define  PCI_EXP_LNKCAP_L0S    0x07000 /* L0s Acceptable Latency */
 #define  PCI_EXP_LNKCAP_L1     0x38000 /* L1 Acceptable Latency */
 #define  PCI_EXP_LNKCAP_ASPM   0x00c00 /* Active State Power Management */
 #define  PCI_EXP_LNKCAP_L0S    0x07000 /* L0s Acceptable Latency */
 #define  PCI_EXP_LNKCAP_L1     0x38000 /* L1 Acceptable Latency */

+#define  PCI_EXP_LNKCAP_CLOCKPM        0x40000 /* Clock Power Management */
+#define  PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */
+#define  PCI_EXP_LNKCAP_DLLA   0x100000 /* Data Link Layer Active Reporting */
+#define  PCI_EXP_LNKCAP_LBNC   0x200000 /* Link Bandwidth Notification Capability */

 #define  PCI_EXP_LNKCAP_PORT   0xff000000 /* Port Number */
 #define PCI_EXP_LNKCTL         0x10    /* Link Control */
 #define  PCI_EXP_LNKCTL_ASPM   0x0003  /* ASPM Control */
 #define  PCI_EXP_LNKCAP_PORT   0xff000000 /* Port Number */
 #define PCI_EXP_LNKCTL         0x10    /* Link Control */
 #define  PCI_EXP_LNKCTL_ASPM   0x0003  /* ASPM Control */


@@ -746,12 +786,19 @@
 #define  PCI_EXP_LNKCTL_RETRAIN        0x0020  /* Retrain Link */
 #define  PCI_EXP_LNKCTL_CLOCK  0x0040  /* Common Clock Configuration */
 #define  PCI_EXP_LNKCTL_XSYNCH 0x0080  /* Extended Synch */
 #define  PCI_EXP_LNKCTL_RETRAIN        0x0020  /* Retrain Link */
 #define  PCI_EXP_LNKCTL_CLOCK  0x0040  /* Common Clock Configuration */
 #define  PCI_EXP_LNKCTL_XSYNCH 0x0080  /* Extended Synch */

+#define  PCI_EXP_LNKCTL_CLOCKPM        0x0100  /* Clock Power Management */
+#define  PCI_EXP_LNKCTL_HWAUTWD        0x0200  /* Hardware Autonomous Width Disable */
+#define  PCI_EXP_LNKCTL_BWMIE  0x0400  /* Bandwidth Mgmt Interrupt Enable */
+#define  PCI_EXP_LNKCTL_AUTBWIE        0x0800  /* Autonomous Bandwidth Mgmt Interrupt Enable */

 #define PCI_EXP_LNKSTA         0x12    /* Link Status */
 #define  PCI_EXP_LNKSTA_SPEED  0x000f  /* Negotiated Link Speed */
 #define  PCI_EXP_LNKSTA_WIDTH  0x03f0  /* Negotiated Link Width */
 #define PCI_EXP_LNKSTA         0x12    /* Link Status */
 #define  PCI_EXP_LNKSTA_SPEED  0x000f  /* Negotiated Link Speed */
 #define  PCI_EXP_LNKSTA_WIDTH  0x03f0  /* Negotiated Link Width */

-#define  PCI_EXP_LNKSTA_TR_ERR 0x0400  /* Training Error */
+#define  PCI_EXP_LNKSTA_TR_ERR 0x0400  /* Training Error (obsolete) */

 #define  PCI_EXP_LNKSTA_TRAIN  0x0800  /* Link Training */
 #define  PCI_EXP_LNKSTA_SL_CLK 0x1000  /* Slot Clock Configuration */
 #define  PCI_EXP_LNKSTA_TRAIN  0x0800  /* Link Training */
 #define  PCI_EXP_LNKSTA_SL_CLK 0x1000  /* Slot Clock Configuration */

+#define  PCI_EXP_LNKSTA_DL_ACT 0x2000  /* Data Link Layer in DL_Active State */
+#define  PCI_EXP_LNKSTA_BWMGMT 0x4000  /* Bandwidth Mgmt Status */
+#define  PCI_EXP_LNKSTA_AUTBW  0x8000  /* Autonomous Bandwidth Mgmt Status */

 #define PCI_EXP_SLTCAP         0x14    /* Slot Capabilities */
 #define  PCI_EXP_SLTCAP_ATNB   0x0001  /* Attention Button Present */
 #define  PCI_EXP_SLTCAP_PWRC   0x0002  /* Power Controller Present */
 #define PCI_EXP_SLTCAP         0x14    /* Slot Capabilities */
 #define  PCI_EXP_SLTCAP_ATNB   0x0001  /* Attention Button Present */
 #define  PCI_EXP_SLTCAP_PWRC   0x0002  /* Power Controller Present */


@@ -762,6 +809,8 @@
 #define  PCI_EXP_SLTCAP_HPC    0x0040  /* Hot-Plug Capable */
 #define  PCI_EXP_SLTCAP_PWR_VAL        0x00007f80 /* Slot Power Limit Value */
 #define  PCI_EXP_SLTCAP_PWR_SCL        0x00018000 /* Slot Power Limit Scale */
 #define  PCI_EXP_SLTCAP_HPC    0x0040  /* Hot-Plug Capable */
 #define  PCI_EXP_SLTCAP_PWR_VAL        0x00007f80 /* Slot Power Limit Value */
 #define  PCI_EXP_SLTCAP_PWR_SCL        0x00018000 /* Slot Power Limit Scale */

+#define  PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */
+#define  PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */

 #define  PCI_EXP_SLTCAP_PSN    0xfff80000 /* Physical Slot Number */
 #define PCI_EXP_SLTCTL         0x18    /* Slot Control */
 #define  PCI_EXP_SLTCTL_ATNB   0x0001  /* Attention Button Pressed Enable */
 #define  PCI_EXP_SLTCAP_PSN    0xfff80000 /* Physical Slot Number */
 #define PCI_EXP_SLTCTL         0x18    /* Slot Control */
 #define  PCI_EXP_SLTCTL_ATNB   0x0001  /* Attention Button Pressed Enable */


@@ -770,21 +819,69 @@
 #define  PCI_EXP_SLTCTL_PRSD   0x0008  /* Presence Detect Changed Enable */
 #define  PCI_EXP_SLTCTL_CMDC   0x0010  /* Command Completed Interrupt Enable */
 #define  PCI_EXP_SLTCTL_HPIE   0x0020  /* Hot-Plug Interrupt Enable */
 #define  PCI_EXP_SLTCTL_PRSD   0x0008  /* Presence Detect Changed Enable */
 #define  PCI_EXP_SLTCTL_CMDC   0x0010  /* Command Completed Interrupt Enable */
 #define  PCI_EXP_SLTCTL_HPIE   0x0020  /* Hot-Plug Interrupt Enable */

-#define  PCI_EXP_SLTCTL_ATNI   0x00C0  /* Attention Indicator Control */
+#define  PCI_EXP_SLTCTL_ATNI   0x00c0  /* Attention Indicator Control */

 #define  PCI_EXP_SLTCTL_PWRI   0x0300  /* Power Indicator Control */
 #define  PCI_EXP_SLTCTL_PWRC   0x0400  /* Power Controller Control */
 #define  PCI_EXP_SLTCTL_PWRI   0x0300  /* Power Indicator Control */
 #define  PCI_EXP_SLTCTL_PWRC   0x0400  /* Power Controller Control */

+#define  PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */
+#define  PCI_EXP_SLTCTL_LLCHG  0x1000  /* Data Link Layer State Changed Enable */

 #define PCI_EXP_SLTSTA         0x1a    /* Slot Status */
 #define PCI_EXP_SLTSTA         0x1a    /* Slot Status */

+#define  PCI_EXP_SLTSTA_ATNB   0x0001  /* Attention Button Pressed */
+#define  PCI_EXP_SLTSTA_PWRF   0x0002  /* Power Fault Detected */
+#define  PCI_EXP_SLTSTA_MRLS   0x0004  /* MRL Sensor Changed */
+#define  PCI_EXP_SLTSTA_PRSD   0x0008  /* Presence Detect Changed */
+#define  PCI_EXP_SLTSTA_CMDC   0x0010  /* Command Completed */
+#define  PCI_EXP_SLTSTA_MRL_ST 0x0020  /* MRL Sensor State */
+#define  PCI_EXP_SLTSTA_PRES   0x0040  /* Presence Detect State */
+#define  PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */
+#define  PCI_EXP_SLTSTA_LLCHG  0x0100  /* Data Link Layer State Changed */

 #define PCI_EXP_RTCTL          0x1c    /* Root Control */
 #define PCI_EXP_RTCTL          0x1c    /* Root Control */

-#define  PCI_EXP_RTCTL_SECEE   0x1     /* System Error on Correctable Error */
-#define  PCI_EXP_RTCTL_SENFEE  0x1     /* System Error on Non-Fatal Error */
-#define  PCI_EXP_RTCTL_SEFEE   0x1     /* System Error on Fatal Error */
-#define  PCI_EXP_RTCTL_PMEIE   0x1     /* PME Interrupt Enable */
+#define  PCI_EXP_RTCTL_SECEE   0x0001  /* System Error on Correctable Error */
+#define  PCI_EXP_RTCTL_SENFEE  0x0002  /* System Error on Non-Fatal Error */
+#define  PCI_EXP_RTCTL_SEFEE   0x0004  /* System Error on Fatal Error */
+#define  PCI_EXP_RTCTL_PMEIE   0x0008  /* PME Interrupt Enable */
+#define  PCI_EXP_RTCTL_CRSVIS  0x0010  /* Configuration Request Retry Status Visible to SW */
+#define PCI_EXP_RTCAP          0x1e    /* Root Capabilities */
+#define  PCI_EXP_RTCAP_CRSVIS  0x0010  /* Configuration Request Retry Status Visible to SW */

 #define PCI_EXP_RTSTA          0x20    /* Root Status */
 #define PCI_EXP_RTSTA          0x20    /* Root Status */

+#define  PCI_EXP_RTSTA_PME_REQID   0x0000ffff /* PME Requester ID */
+#define  PCI_EXP_RTSTA_PME_STATUS  0x00010000 /* PME Status */
+#define  PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
+#define PCI_EXP_DEVCAP2                        0x24    /* Device capabilities 2 */
+#define  PCI_EXP_DEVCAP2_LTR           0x0800  /* LTR supported */
+#define  PCI_EXP_DEVCAP2_OBFF(x)       (((x) >> 18) & 3) /* OBFF supported */
+#define PCI_EXP_DEVCTL2                        0x28    /* Device Control */
+#define  PCI_EXP_DEV2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ranges Supported */
+#define  PCI_EXP_DEV2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Value */
+#define  PCI_EXP_DEV2_TIMEOUT_DIS      0x0010  /* Completion Timeout Disable Supported */
+#define  PCI_EXP_DEV2_ARI              0x0020  /* ARI Forwarding */
+#define  PCI_EXP_DEV2_LTR              0x0400  /* LTR enabled */
+#define  PCI_EXP_DEV2_OBFF(x)          (((x) >> 13) & 3) /* OBFF enabled */
+#define PCI_EXP_DEVSTA2                        0x2a    /* Device Status */
+#define PCI_EXP_LNKCAP2                        0x2c    /* Link Capabilities */
+#define PCI_EXP_LNKCTL2                        0x30    /* Link Control */
+#define  PCI_EXP_LNKCTL2_SPEED(x)      ((x) & 0xf) /* Target Link Speed */
+#define  PCI_EXP_LNKCTL2_CMPLNC                0x0010  /* Enter Compliance */
+#define  PCI_EXP_LNKCTL2_SPEED_DIS     0x0020  /* Hardware Autonomous Speed Disable */
+#define  PCI_EXP_LNKCTL2_DEEMPHASIS(x) (((x) >> 6) & 1) /* Selectable De-emphasis */
+#define  PCI_EXP_LNKCTL2_MARGIN(x)     (((x) >> 7) & 7) /* Transmit Margin */
+#define  PCI_EXP_LNKCTL2_MOD_CMPLNC    0x0400  /* Enter Modified Compliance */
+#define  PCI_EXP_LNKCTL2_CMPLNC_SOS    0x0800  /* Compliance SOS */
+#define  PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 0xf) /* Compliance De-emphasis */
+#define PCI_EXP_LNKSTA2                        0x32    /* Link Status */
+#define  PCI_EXP_LINKSTA2_DEEMPHASIS(x)        ((x) & 1)       /* Current De-emphasis Level */
+#define  PCI_EXP_LINKSTA2_EQU_COMP     0x02    /* Equalization Complete */
+#define  PCI_EXP_LINKSTA2_EQU_PHASE1   0x04    /* Equalization Phase 1 Successful */
+#define  PCI_EXP_LINKSTA2_EQU_PHASE2   0x08    /* Equalization Phase 2 Successful */
+#define  PCI_EXP_LINKSTA2_EQU_PHASE3   0x10    /* Equalization Phase 3 Successful */
+#define  PCI_EXP_LINKSTA2_EQU_REQ      0x20    /* Link Equalization Request */
+#define PCI_EXP_SLTCAP2                        0x34    /* Slot Capabilities */
+#define PCI_EXP_SLTCTL2                        0x38    /* Slot Control */
+#define PCI_EXP_SLTSTA2                        0x3a    /* Slot Status */

 
 /* MSI-X */
 #define  PCI_MSIX_ENABLE       0x8000
 #define  PCI_MSIX_MASK         0x4000
 
 /* MSI-X */
 #define  PCI_MSIX_ENABLE       0x8000
 #define  PCI_MSIX_MASK         0x4000

-#define  PCI_MSIX_TABSIZE      0x03ff
+#define  PCI_MSIX_TABSIZE      0x07ff

 #define PCI_MSIX_TABLE         4
 #define PCI_MSIX_PBA           8
 #define  PCI_MSIX_BIR          0x7
 #define PCI_MSIX_TABLE         4
 #define PCI_MSIX_PBA           8
 #define  PCI_MSIX_BIR          0x7


@@ -793,10 +890,26 @@
 #define PCI_SSVID_VENDOR       4
 #define PCI_SSVID_DEVICE       6
 
 #define PCI_SSVID_VENDOR       4
 #define PCI_SSVID_DEVICE       6
 

+/* PCI Advanced Features */
+#define PCI_AF_CAP             3
+#define  PCI_AF_CAP_TP         0x01
+#define  PCI_AF_CAP_FLR                0x02
+#define PCI_AF_CTRL            4
+#define  PCI_AF_CTRL_FLR       0x01
+#define PCI_AF_STATUS          5
+#define  PCI_AF_STATUS_TP      0x01
+
+/* SATA Host Bus Adapter */
+#define PCI_SATA_HBA_BARS      4
+#define PCI_SATA_HBA_REG0      8
+
+/*** Definitions of extended capabilities ***/
+

 /* Advanced Error Reporting */
 #define PCI_ERR_UNCOR_STATUS   4       /* Uncorrectable Error Status */
 /* Advanced Error Reporting */
 #define PCI_ERR_UNCOR_STATUS   4       /* Uncorrectable Error Status */

-#define  PCI_ERR_UNC_TRAIN     0x00000001      /* Training */
+#define  PCI_ERR_UNC_TRAIN     0x00000001      /* Undefined in PCIe rev1.1 & 2.0 spec */

 #define  PCI_ERR_UNC_DLP       0x00000010      /* Data Link Protocol */
 #define  PCI_ERR_UNC_DLP       0x00000010      /* Data Link Protocol */

+#define  PCI_ERR_UNC_SDES      0x00000020      /* Surprise Down Error */

 #define  PCI_ERR_UNC_POISON_TLP        0x00001000      /* Poisoned TLP */
 #define  PCI_ERR_UNC_FCP       0x00002000      /* Flow Control Protocol */
 #define  PCI_ERR_UNC_COMP_TIME 0x00004000      /* Completion Timeout */
 #define  PCI_ERR_UNC_POISON_TLP        0x00001000      /* Poisoned TLP */
 #define  PCI_ERR_UNC_FCP       0x00002000      /* Flow Control Protocol */
 #define  PCI_ERR_UNC_COMP_TIME 0x00004000      /* Completion Timeout */


@@ -806,6 +919,7 @@
 #define  PCI_ERR_UNC_MALF_TLP  0x00040000      /* Malformed TLP */
 #define  PCI_ERR_UNC_ECRC      0x00080000      /* ECRC Error Status */
 #define  PCI_ERR_UNC_UNSUP     0x00100000      /* Unsupported Request */
 #define  PCI_ERR_UNC_MALF_TLP  0x00040000      /* Malformed TLP */
 #define  PCI_ERR_UNC_ECRC      0x00080000      /* ECRC Error Status */
 #define  PCI_ERR_UNC_UNSUP     0x00100000      /* Unsupported Request */

+#define  PCI_ERR_UNC_ACS_VIOL  0x00200000      /* ACS Violation */

 #define PCI_ERR_UNCOR_MASK     8       /* Uncorrectable Error Mask */
        /* Same bits as above */
 #define PCI_ERR_UNCOR_SEVER    12      /* Uncorrectable Error Severity */
 #define PCI_ERR_UNCOR_MASK     8       /* Uncorrectable Error Mask */
        /* Same bits as above */
 #define PCI_ERR_UNCOR_SEVER    12      /* Uncorrectable Error Severity */


@@ -816,6 +930,7 @@
 #define  PCI_ERR_COR_BAD_DLLP  0x00000080      /* Bad DLLP Status */
 #define  PCI_ERR_COR_REP_ROLL  0x00000100      /* REPLAY_NUM Rollover */
 #define  PCI_ERR_COR_REP_TIMER 0x00001000      /* Replay Timer Timeout */
 #define  PCI_ERR_COR_BAD_DLLP  0x00000080      /* Bad DLLP Status */
 #define  PCI_ERR_COR_REP_ROLL  0x00000100      /* REPLAY_NUM Rollover */
 #define  PCI_ERR_COR_REP_TIMER 0x00001000      /* Replay Timer Timeout */

+#define  PCI_ERR_COR_REP_ANFE  0x00002000      /* Advisory Non-Fatal Error */

 #define PCI_ERR_COR_MASK       20      /* Correctable Error Mask */
        /* Same bits as above */
 #define PCI_ERR_CAP            24      /* Advanced Error Capabilities */
 #define PCI_ERR_COR_MASK       20      /* Correctable Error Mask */
        /* Same bits as above */
 #define PCI_ERR_CAP            24      /* Advanced Error Capabilities */


@@ -851,6 +966,99 @@
 #define PCI_PWR_CAP            12      /* Capability */
 #define  PCI_PWR_CAP_BUDGET(x) ((x) & 1)       /* Included in system budget */
 
 #define PCI_PWR_CAP            12      /* Capability */
 #define  PCI_PWR_CAP_BUDGET(x) ((x) & 1)       /* Included in system budget */
 

+/* Root Complex Link */
+#define PCI_RCLINK_ESD         4       /* Element Self Description */
+#define PCI_RCLINK_LINK1       16      /* First Link Entry */
+#define  PCI_RCLINK_LINK_DESC  0       /* Link Entry: Description */
+#define  PCI_RCLINK_LINK_ADDR  8       /* Link Entry: Address (64-bit) */
+#define  PCI_RCLINK_LINK_SIZE  16      /* Link Entry: sizeof */
+
+/* PCIe Vendor-Specific Capability */
+#define PCI_EVNDR_HEADER       4       /* Vendor-Specific Header */
+#define PCI_EVNDR_REGISTERS    8       /* Vendor-Specific Registers */
+
+/* Access Control Services */
+#define PCI_ACS_CAP            0x04    /* ACS Capability Register */
+#define PCI_ACS_CAP_VALID      0x0001  /* ACS Source Validation */
+#define PCI_ACS_CAP_BLOCK      0x0002  /* ACS Translation Blocking */
+#define PCI_ACS_CAP_REQ_RED    0x0004  /* ACS P2P Request Redirect */
+#define PCI_ACS_CAP_CMPLT_RED  0x0008  /* ACS P2P Completion Redirect */
+#define PCI_ACS_CAP_FORWARD    0x0010  /* ACS Upstream Forwarding */
+#define PCI_ACS_CAP_EGRESS     0x0020  /* ACS P2P Egress Control */
+#define PCI_ACS_CAP_TRANS      0x0040  /* ACS Direct Translated P2P */
+#define PCI_ACS_CAP_VECTOR(x)  (((x) >> 8) & 0xff) /* Egress Control Vector Size */
+#define PCI_ACS_CTRL           0x06    /* ACS Control Register */
+#define PCI_ACS_CTRL_VALID     0x0001  /* ACS Source Validation Enable */
+#define PCI_ACS_CTRL_BLOCK     0x0002  /* ACS Translation Blocking Enable */
+#define PCI_ACS_CTRL_REQ_RED   0x0004  /* ACS P2P Request Redirect Enable */
+#define PCI_ACS_CTRL_CMPLT_RED 0x0008  /* ACS P2P Completion Redirect Enable */
+#define PCI_ACS_CTRL_FORWARD   0x0010  /* ACS Upstream Forwarding Enable */
+#define PCI_ACS_CTRL_EGRESS    0x0020  /* ACS P2P Egress Control Enable */
+#define PCI_ACS_CTRL_TRANS     0x0040  /* ACS Direct Translated P2P Enable */
+#define PCI_ACS_EGRESS_CTRL    0x08    /* Egress Control Vector */
+
+/* Alternative Routing-ID Interpretation */
+#define PCI_ARI_CAP            0x04    /* ARI Capability Register */
+#define  PCI_ARI_CAP_MFVC      0x0001  /* MFVC Function Groups Capability */
+#define  PCI_ARI_CAP_ACS       0x0002  /* ACS Function Groups Capability */
+#define  PCI_ARI_CAP_NFN(x)    (((x) >> 8) & 0xff) /* Next Function Number */
+#define PCI_ARI_CTRL           0x06    /* ARI Control Register */
+#define  PCI_ARI_CTRL_MFVC     0x0001  /* MFVC Function Groups Enable */
+#define  PCI_ARI_CTRL_ACS      0x0002  /* ACS Function Groups Enable */
+#define  PCI_ARI_CTRL_FG(x)    (((x) >> 4) & 7) /* Function Group */
+
+/* Address Translation Service */
+#define PCI_ATS_CAP            0x04    /* ATS Capability Register */
+#define  PCI_ATS_CAP_IQD(x)    ((x) & 0x1f) /* Invalidate Queue Depth */
+#define PCI_ATS_CTRL           0x06    /* ATS Control Register */
+#define  PCI_ATS_CTRL_STU(x)   ((x) & 0x1f) /* Smallest Translation Unit */
+#define  PCI_ATS_CTRL_ENABLE   0x8000  /* ATS Enable */
+
+/* Single Root I/O Virtualization */
+#define PCI_IOV_CAP            0x04    /* SR-IOV Capability Register */
+#define  PCI_IOV_CAP_VFM       0x00000001 /* VF Migration Capable */
+#define  PCI_IOV_CAP_IMN(x)    ((x) >> 21) /* VF Migration Interrupt Message Number */
+#define PCI_IOV_CTRL           0x08    /* SR-IOV Control Register */
+#define  PCI_IOV_CTRL_VFE      0x0001  /* VF Enable */
+#define  PCI_IOV_CTRL_VFME     0x0002  /* VF Migration Enable */
+#define  PCI_IOV_CTRL_VFMIE    0x0004  /* VF Migration Interrupt Enable */
+#define  PCI_IOV_CTRL_MSE      0x0008  /* VF MSE */
+#define  PCI_IOV_CTRL_ARI      0x0010  /* ARI Capable Hierarchy */
+#define PCI_IOV_STATUS         0x0a    /* SR-IOV Status Register */
+#define  PCI_IOV_STATUS_MS     0x0001  /* VF Migration Status */
+#define PCI_IOV_INITIALVF      0x0c    /* Number of VFs that are initially associated */
+#define PCI_IOV_TOTALVF                0x0e    /* Maximum number of VFs that could be associated */
+#define PCI_IOV_NUMVF          0x10    /* Number of VFs that are available */
+#define PCI_IOV_FDL            0x12    /* Function Dependency Link */
+#define PCI_IOV_OFFSET         0x14    /* First VF Offset */
+#define PCI_IOV_STRIDE         0x16    /* Routing ID offset from one VF to the next one */
+#define PCI_IOV_DID            0x1a    /* VF Device ID */
+#define PCI_IOV_SUPPS          0x1c    /* Supported Page Sizes */
+#define PCI_IOV_SYSPS          0x20    /* System Page Size */
+#define PCI_IOV_BAR_BASE       0x24    /* VF BAR0, VF BAR1, ... VF BAR5 */
+#define PCI_IOV_NUM_BAR                6       /* Number of VF BARs */
+#define PCI_IOV_MSAO           0x3c    /* VF Migration State Array Offset */
+#define PCI_IOV_MSA_BIR(x)     ((x) & 7) /* VF Migration State BIR */
+#define PCI_IOV_MSA_OFFSET(x)  ((x) & 0xfffffff8) /* VF Migration State Offset */
+
+/* Transaction Processing Hints */
+#define PCI_TPH_CAPABILITIES   4
+#define   PCI_TPH_INTVEC_SUP   (1<<1)  /* Supports interrupt vector mode */
+#define   PCI_TPH_DEV_SUP              (1<<2)  /* Device specific mode supported */
+#define   PCI_TPH_EXT_REQ_SUP  (1<<8)  /* Supports extended requests */
+#define   PCI_TPH_ST_LOC_MASK  (3<<9)  /* Steering table location bits */
+#define     PCI_TPH_ST_NONE    (0<<9)  /* No steering table */
+#define     PCI_TPH_ST_CAP     (1<<9)  /* Steering table in TPH cap */
+#define     PCI_TPH_ST_MSIX    (2<<9)  /* Steering table in MSI-X table */
+#define   PCI_TPH_ST_SIZE_SHIFT        (16)    /* Encoded as size - 1 */
+
+/* Latency Tolerance Reporting */
+#define PCI_LTR_MAX_SNOOP      4       /* 16 bit value */
+#define   PCI_LTR_VALUE_MASK   (0x3ff)
+#define   PCI_LTR_SCALE_SHIFT  (10)
+#define   PCI_LTR_SCALE_MASK   (7)
+#define PCI_LTR_MAX_NOSNOOP    6       /* 16 bit value */
+

 /*
  * The PCI interface treats multi-function devices as independent
  * devices.  The slot/function address of each device is encoded
 /*
  * The PCI interface treats multi-function devices as independent
  * devices.  The slot/function address of each device is encoded