Merge remote-tracking branch 'twilfredo/wilfred/fixup-doe-bits'

[pciutils.git] / lib / header.h

diff --git a/lib/header.h b/lib/header.h
index cc69a5189be93e707d970a9462bcc3de3a130a35..5ab606ff39f3d687585322a36cc741d1033c7855 100644 (file)
--- a/lib/header.h
+++ b/lib/header.h
@@ -3,7 +3,9 @@
  *
  *     Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz>
  *
  *
  *     Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz>
  *

- *     Can be freely distributed and used under the terms of the GNU GPL.
+ *     Can be freely distributed and used under the terms of the GNU GPL v2+
+ *
+ *     SPDX-License-Identifier: GPL-2.0-or-later

  */
 
 /*
  */
 
 /*


@@ -1141,6 +1143,17 @@
 #define PCI_CXL_GPF_DEV_100MS   0x5
 #define PCI_CXL_GPF_DEV_1S      0x6
 #define PCI_CXL_GPF_DEV_10S     0x7
 #define PCI_CXL_GPF_DEV_100MS   0x5
 #define PCI_CXL_GPF_DEV_1S      0x6
 #define PCI_CXL_GPF_DEV_10S     0x7

+#define PCI_CXL_GPF_PORT_LEN    0x10
+#define PCI_CXL_GPF_PORT_PHASE1_CTRL  0x0c /* GPF Phase 1 Control Register */
+#define PCI_CXL_GPF_PORT_PHASE2_CTRL 0x0e /* GPF Phase 2 Control Register */
+#define PCI_CXL_GPF_PORT_1US     0x0
+#define PCI_CXL_GPF_PORT_10US    0x1
+#define PCI_CXL_GPF_PORT_100US   0x2
+#define PCI_CXL_GPF_PORT_1MS     0x3
+#define PCI_CXL_GPF_PORT_10MS    0x4
+#define PCI_CXL_GPF_PORT_100MS   0x5
+#define PCI_CXL_GPF_PORT_1S      0x6
+#define PCI_CXL_GPF_PORT_10S     0x7

 
 /* PCIe CXL Designated Vendor-Specific Capabilities for Flex Bus Port */
 #define PCI_CXL_FB_LEN                0x20
 
 /* PCIe CXL Designated Vendor-Specific Capabilities for Flex Bus Port */
 #define PCI_CXL_FB_LEN                0x20


@@ -1182,6 +1195,22 @@
 #define  PCI_CXL_FB_CTRL2_NOP_HINT          0x01    /* NOP Hint Enable */
 #define PCI_CXL_FB_PORT_STATUS2             0x1c    /* CXL Flex Bus Port Status2 Register */
 
 #define  PCI_CXL_FB_CTRL2_NOP_HINT          0x01    /* NOP Hint Enable */
 #define PCI_CXL_FB_PORT_STATUS2             0x1c    /* CXL Flex Bus Port Status2 Register */
 

+/* PCIe CXL Designated Vendor-Specific Capabilities for Multi-Logical Device */
+#define PCI_CXL_MLD_LEN     0x10
+#define PCI_CXL_MLD_NUM_LD  0xa
+#define PCI_CXL_MLD_MAX_LD  0x10
+
+/* PCIe CXL Designated Vendor-Specific Capabilities for Non-CXL Function Map */
+#define PCI_CXL_FUN_MAP_LEN     0x2c
+#define PCI_CXL_FUN_MAP_REG_0   0x0c
+#define PCI_CXL_FUN_MAP_REG_1   0x10
+#define PCI_CXL_FUN_MAP_REG_2   0x14
+#define PCI_CXL_FUN_MAP_REG_3   0x18
+#define PCI_CXL_FUN_MAP_REG_4   0x1c
+#define PCI_CXL_FUN_MAP_REG_5   0x20
+#define PCI_CXL_FUN_MAP_REG_6   0x24
+#define PCI_CXL_FUN_MAP_REG_7   0x28
+

 /* Access Control Services */
 #define PCI_ACS_CAP            0x04    /* ACS Capability Register */
 #define PCI_ACS_CAP_VALID      0x0001  /* ACS Source Validation */
 /* Access Control Services */
 #define PCI_ACS_CAP            0x04    /* ACS Capability Register */
 #define PCI_ACS_CAP_VALID      0x0001  /* ACS Source Validation */


@@ -1362,7 +1391,7 @@
 #define PCI_DOE_STS            0xC     /* DOE Status Register */
 #define  PCI_DOE_STS_BUSY              0x1     /* DOE Busy */
 #define  PCI_DOE_STS_INT               0x2     /* DOE Interrupt Status */
 #define PCI_DOE_STS            0xC     /* DOE Status Register */
 #define  PCI_DOE_STS_BUSY              0x1     /* DOE Busy */
 #define  PCI_DOE_STS_INT               0x2     /* DOE Interrupt Status */

-#define  PCI_DOE_STS_ERROR             0x3     /* DOE Error */
+#define  PCI_DOE_STS_ERROR             0x4     /* DOE Error */

 #define  PCI_DOE_STS_OBJECT_READY      0x80000000 /* Data Object Ready */
 
 /*
 #define  PCI_DOE_STS_OBJECT_READY      0x80000000 /* Data Object Ready */
 
 /*