+#define PCI_CXL_DEV_CTRL2 0x10 /* CXL Control Register 2 */
+#define PCI_CXL_DEV_CTRL2_DISABLE_CACHING 0x0001
+#define PCI_CXL_DEV_CTRL2_INIT_WB_INVAL 0x0002
+#define PCI_CXL_DEV_CTRL2_INIT_CXL_RST 0x0003
+#define PCI_CXL_DEV_CTRL2_INIT_CXL_RST_CLR_EN 0x0004
+#define PCI_CXL_DEV_CTRL2_INIT_CXL_HDM_STATE_HOTRST 0x0005