/*
* The PCI Utilities -- List All PCI Devices
*
- * Copyright (c) 1997--2007 Martin Mares <mj@ucw.cz>
+ * Copyright (c) 1997--2008 Martin Mares <mj@ucw.cz>
*
* Can be freely distributed and used under the terms of the GNU GPL.
*/
#include <stdarg.h>
#include <unistd.h>
+#define PCIUTILS_LSPCI
#include "pciutils.h"
/* Options */
static int verbose; /* Show detailed information */
-static int buscentric_view; /* Show bus addresses/IRQ's instead of CPU-visible ones */
-static int show_hex; /* Show contents of config space as hexadecimal numbers */
+static int opt_buscentric; /* Show bus addresses/IRQ's instead of CPU-visible ones */
+static int opt_hex; /* Show contents of config space as hexadecimal numbers */
static struct pci_filter filter; /* Device filter */
-static int show_tree; /* Show bus tree */
-static int machine_readable; /* Generate machine-readable output */
-static int map_mode; /* Bus mapping mode enabled */
-static int show_domains; /* Show domain numbers (0=disabled, 1=auto-detected, 2=requested) */
+static int opt_tree; /* Show bus tree */
+static int opt_machine; /* Generate machine-readable output */
+static int opt_map_mode; /* Bus mapping mode enabled */
+static int opt_domains; /* Show domain numbers (0=disabled, 1=auto-detected, 2=requested) */
+static int opt_kernel; /* Show kernel drivers */
+static int opt_query_dns; /* Query the DNS (0=disabled, 1=enabled, 2=refresh cache) */
+static int opt_query_all; /* Query the DNS for all entries */
+static char *opt_pcimap; /* Override path to Linux modules.pcimap */
const char program_name[] = "lspci";
-static char options[] = "nvbxs:d:ti:mgMD" GENERIC_OPTIONS ;
-
-static char help_msg[] = "\
-Usage: lspci [<switches>]\n\
-\n\
--v\t\tBe verbose\n\
--n\t\tShow numeric ID's\n\
--nn\t\tShow both textual and numeric ID's (names & numbers)\n\
--b\t\tBus-centric view (PCI addresses and IRQ's instead of those seen by the CPU)\n\
--x\t\tShow hex-dump of the standard portion of config space\n\
--xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n\
--xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n\
--s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n\
--d [<vendor>]:[<device>]\tShow only selected devices\n\
--t\t\tShow bus tree\n\
--m\t\tProduce machine-readable output\n\
--i <file>\tUse specified ID database instead of %s\n\
--D\t\tAlways show domain numbers\n\
--M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
+static char options[] = "nvbxs:d:ti:mgp:qkMDQ" GENERIC_OPTIONS ;
+
+static char help_msg[] =
+"Usage: lspci [<switches>]\n"
+"\n"
+"Basic display modes:\n"
+"-mm\t\tProduce machine-readable output (single -m for an obsolete format)\n"
+"-t\t\tShow bus tree\n"
+"\n"
+"Display options:\n"
+"-v\t\tBe verbose (-vv for very verbose)\n"
+#ifdef PCI_OS_LINUX
+"-k\t\tShow kernel drivers handling each device\n"
+#endif
+"-x\t\tShow hex-dump of the standard part of the config space\n"
+"-xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n"
+"-xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n"
+"-b\t\tBus-centric view (addresses and IRQ's as seen by the bus)\n"
+"-D\t\tAlways show domain numbers\n"
+"\n"
+"Resolving of device ID's to names:\n"
+"-n\t\tShow numeric ID's\n"
+"-nn\t\tShow both textual and numeric ID's (names & numbers)\n"
+#ifdef PCI_USE_DNS
+"-q\t\tQuery the PCI ID database for unknown ID's via DNS\n"
+"-qq\t\tAs above, but re-query locally cached entries\n"
+"-Q\t\tQuery the PCI ID database for all ID's via DNS\n"
+#endif
+"\n"
+"Selection of devices:\n"
+"-s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n"
+"-d [<vendor>]:[<device>]\t\t\tShow only devices with specified ID's\n"
+"\n"
+"Other options:\n"
+"-i <file>\tUse specified ID database instead of %s\n"
+#ifdef PCI_OS_LINUX
+"-p <file>\tLook up kernel modules in a given file instead of default modules.pcimap\n"
+#endif
+"-M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
+"\n"
+"PCI access options:\n"
GENERIC_HELP
;
-/* Communication with libpci */
+/*** Communication with libpci ***/
static struct pci_access *pacc;
#define alloca xmalloc
#endif
-/* Our view of the PCI bus */
+/*** Our view of the PCI bus ***/
struct device {
struct device *next;
{
struct device *d;
- if (p->domain && !show_domains)
- show_domains = 1;
+ if (p->domain && !opt_domains)
+ opt_domains = 1;
if (!pci_filter_match(&filter, p))
return NULL;
d = xmalloc(sizeof(struct device));
}
}
-/* Config space accesses */
+/*** Config space accesses ***/
static void
check_conf_range(struct device *d, unsigned int pos, unsigned int len)
(d->config[pos+3] << 24);
}
-/* Sorting */
+/*** Sorting ***/
static int
compare_them(const void *A, const void *B)
*last_dev = NULL;
}
-/* Normal output */
+/*** Normal output ***/
#define FLAG(x,y) ((x & y) ? '+' : '-')
{
struct pci_dev *p = d->dev;
- if (!machine_readable ? show_domains : (p->domain || show_domains >= 2))
+ if (!opt_machine ? opt_domains : (p->domain || opt_domains >= 2))
printf("%04x:", p->domain);
printf("%02x:%02x.%d", p->bus, p->dev, p->func);
}
}
static void
-show_size(pciaddr_t x)
-{
- if (!x)
- return;
- printf(" [size=");
- if (x < 1024)
- printf("%d", (int) x);
- else if (x < 1048576)
- printf("%dK", (int)(x / 1024));
- else if (x < 0x80000000)
- printf("%dM", (int)(x / 1048576));
- else
- printf(PCIADDR_T_FMT, x);
- putchar(']');
-}
-
-static void
-show_bases(struct device *d, int cnt)
+get_subid(struct device *d, word *subvp, word *subdp)
{
- struct pci_dev *p = d->dev;
- word cmd = get_conf_word(d, PCI_COMMAND);
- int i;
+ byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
- for(i=0; i<cnt; i++)
+ if (htype == PCI_HEADER_TYPE_NORMAL)
{
- pciaddr_t pos = p->base_addr[i];
- pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
- u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
- if (flg == 0xffffffff)
- flg = 0;
- if (!pos && !flg && !len)
- continue;
- if (verbose > 1)
- printf("\tRegion %d: ", i);
- else
- putchar('\t');
- if (pos && !flg) /* Reported by the OS, but not by the device */
- {
- printf("[virtual] ");
- flg = pos;
- }
- if (flg & PCI_BASE_ADDRESS_SPACE_IO)
- {
- pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
- printf("I/O ports at ");
- if (a)
- printf(PCIADDR_PORT_FMT, a);
- else if (flg & PCI_BASE_ADDRESS_IO_MASK)
- printf("<ignored>");
- else
- printf("<unassigned>");
- if (!(cmd & PCI_COMMAND_IO))
- printf(" [disabled]");
- }
- else
- {
- int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
- pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
- int done = 0;
- u32 z = 0;
-
- printf("Memory at ");
- if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
- {
- if (i >= cnt - 1)
- {
- printf("<invalid-64bit-slot>");
- done = 1;
- }
- else
- {
- i++;
- z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
- if (buscentric_view)
- {
- u32 y = a & 0xffffffff;
- if (a || z)
- printf("%08x%08x", z, y);
- else
- printf("<unassigned>");
- done = 1;
- }
- }
- }
- if (!done)
- {
- if (a)
- printf(PCIADDR_T_FMT, a);
- else
- printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
- }
- printf(" (%s, %sprefetchable)",
- (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
- (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
- (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
- (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
- if (!(cmd & PCI_COMMAND_MEMORY))
- printf(" [disabled]");
- }
- show_size(len);
- putchar('\n');
+ *subvp = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
+ *subdp = get_conf_word(d, PCI_SUBSYSTEM_ID);
+ }
+ else if (htype == PCI_HEADER_TYPE_CARDBUS && d->config_cached >= 128)
+ {
+ *subvp = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
+ *subdp = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
}
+ else
+ *subvp = *subdp = 0xffff;
}
+/*** Capabilities ***/
+
static void
-show_pm(struct device *d, int where, int cap)
+cap_pm(struct device *d, int where, int cap)
{
int t, b;
static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
}
static void
-show_agp(struct device *d, int where, int cap)
+cap_agp(struct device *d, int where, int cap)
{
u32 t;
char rate[16];
}
static void
-show_pcix_nobridge(struct device *d, int where)
+cap_pcix_nobridge(struct device *d, int where)
{
u16 command;
u32 status;
}
static void
-show_pcix_bridge(struct device *d, int where)
+cap_pcix_bridge(struct device *d, int where)
{
static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
u16 secstatus;
}
static void
-show_pcix(struct device *d, int where)
+cap_pcix(struct device *d, int where)
{
switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
{
case PCI_HEADER_TYPE_NORMAL:
- show_pcix_nobridge(d, where);
+ cap_pcix_nobridge(d, where);
break;
case PCI_HEADER_TYPE_BRIDGE:
- show_pcix_bridge(d, where);
+ cap_pcix_bridge(d, where);
break;
}
}
}
static void
-show_ht_pri(struct device *d, int where, int cmd)
+cap_ht_pri(struct device *d, int where, int cmd)
{
u16 lctr0, lcnf0, lctr1, lcnf1, eh;
u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
return;
rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
- if (rid < 0x23 && rid > 0x11)
+ if (rid < 0x22 && rid > 0x11)
printf("\t\t!!! Possibly incomplete decoding\n");
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
else
fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
FLAG(cmd, PCI_HT_PRI_CMD_DD),
FLAG(cmd, PCI_HT_PRI_CMD_DUL));
lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
else
fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
FLAG(lctr0, PCI_HT_LCTR_64B));
lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
else
fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
FLAG(lcnf0, PCI_HT_LCNF_DFIE),
FLAG(lcnf0, PCI_HT_LCNF_DFOE));
lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
else
fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
FLAG(lctr1, PCI_HT_LCTR_64B));
lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
else
fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
FLAG(lcnf1, PCI_HT_LCNF_DFOE));
printf("\t\tRevision ID: %u.%02u\n",
(rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
- if (rid < 0x23)
+ if (rid < 0x22)
return;
lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
}
static void
-show_ht_sec(struct device *d, int where, int cmd)
+cap_ht_sec(struct device *d, int where, int cmd)
{
u16 lctr, lcnf, ftr, eh;
u8 rid, lfrer, lfcap, mbu, mlu;
if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
return;
rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
- if (rid < 0x23 && rid > 0x11)
+ if (rid < 0x22 && rid > 0x11)
printf("\t\t!!! Possibly incomplete decoding\n");
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
else
fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
FLAG(cmd, PCI_HT_SEC_CMD_DUL));
lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
else
fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
FLAG(lctr, PCI_HT_LCTR_EXTCTL),
FLAG(lctr, PCI_HT_LCTR_64B));
lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
else
fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
FLAG(lcnf, PCI_HT_LCNF_DFOE));
printf("\t\tRevision ID: %u.%02u\n",
(rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
- if (rid < 0x23)
+ if (rid < 0x22)
return;
lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
}
static void
-show_ht(struct device *d, int where, int cmd)
+cap_ht(struct device *d, int where, int cmd)
{
int type;
switch (cmd & PCI_HT_CMD_TYP_HI)
{
case PCI_HT_CMD_TYP_HI_PRI:
- show_ht_pri(d, where, cmd);
+ cap_ht_pri(d, where, cmd);
return;
case PCI_HT_CMD_TYP_HI_SEC:
- show_ht_sec(d, where, cmd);
+ cap_ht_sec(d, where, cmd);
return;
}
}
static void
-show_rom(struct device *d, int reg)
-{
- struct pci_dev *p = d->dev;
- pciaddr_t rom = p->rom_base_addr;
- pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
- u32 flg = get_conf_long(d, reg);
- word cmd = get_conf_word(d, PCI_COMMAND);
-
- if (!rom && !flg && !len)
- return;
- putchar('\t');
- if ((rom & PCI_ROM_ADDRESS_MASK) && !(flg & PCI_ROM_ADDRESS_MASK))
- {
- printf("[virtual] ");
- flg = rom;
- }
- printf("Expansion ROM at ");
- if (rom & PCI_ROM_ADDRESS_MASK)
- printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
- else if (flg & PCI_ROM_ADDRESS_MASK)
- printf("<ignored>");
- else
- printf("<unassigned>");
- if (!(flg & PCI_ROM_ADDRESS_ENABLE))
- printf(" [disabled]");
- else if (!(cmd & PCI_COMMAND_MEMORY))
- printf(" [disabled by cmd]");
- show_size(len);
- putchar('\n');
-}
-
-static void
-show_msi(struct device *d, int where, int cap)
+cap_msi(struct device *d, int where, int cap)
{
int is64;
u32 t;
u16 w;
- printf("Message Signalled Interrupts: Mask%c 64bit%c Queue=%d/%d Enable%c\n",
+ printf("MSI: Mask%c 64bit%c Count=%d/%d Enable%c\n",
FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
FLAG(cap, PCI_MSI_FLAGS_64BIT),
- (cap & PCI_MSI_FLAGS_QSIZE) >> 4,
- (cap & PCI_MSI_FLAGS_QMASK) >> 1,
+ 1 << ((cap & PCI_MSI_FLAGS_QSIZE) >> 4),
+ 1 << ((cap & PCI_MSI_FLAGS_QMASK) >> 1),
FLAG(cap, PCI_MSI_FLAGS_ENABLE));
if (verbose < 2)
return;
}
}
-static void show_vendor(void)
-{
- printf("Vendor Specific Information\n");
-}
-
-static void show_debug(void)
-{
- printf("Debug port\n");
-}
-
static float power_limit(int value, int scale)
{
static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
return latencies[value];
}
-static void show_express_dev(struct device *d, int where, int type)
+static void cap_express_dev(struct device *d, int where, int type)
{
u32 t;
u16 w;
FLAG(w, PCI_EXP_DEVSTA_URD),
FLAG(w, PCI_EXP_DEVSTA_AUXPD),
FLAG(w, PCI_EXP_DEVSTA_TRPND));
-
- /* FIXME: Second set of control/status registers is not supported yet. */
}
static char *link_speed(int speed)
return desc[code];
}
-static void show_express_link(struct device *d, int where, int type)
+static void cap_express_link(struct device *d, int where, int type)
{
u32 t;
u16 w;
return names[code];
}
-static void show_express_slot(struct device *d, int where)
+static void cap_express_slot(struct device *d, int where)
{
u32 t;
u16 w;
FLAG(w, PCI_EXP_SLTSTA_LLCHG));
}
-static void show_express_root(struct device *d, int where)
+static void cap_express_root(struct device *d, int where)
{
u32 w = get_conf_word(d, where + PCI_EXP_RTCTL);
printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
}
+static const char *cap_express_dev2_timeout_range(int type)
+{
+ /* Decode Completion Timeout Ranges. */
+ switch (type)
+ {
+ case 0:
+ return "Not Supported";
+ case 1:
+ return "Range A";
+ case 2:
+ return "Range B";
+ case 3:
+ return "Range AB";
+ case 6:
+ return "Range BC";
+ case 7:
+ return "Range ABC";
+ case 14:
+ return "Range BCD";
+ case 15:
+ return "Range ABCD";
+ default:
+ return "Unknown";
+ }
+}
+
+static const char *cap_express_dev2_timeout_value(int type)
+{
+ /* Decode Completion Timeout Value. */
+ switch (type)
+ {
+ case 0:
+ return "50us to 50ms";
+ case 1:
+ return "50us to 100us";
+ case 2:
+ return "1ms to 10ms";
+ case 5:
+ return "16ms to 55ms";
+ case 6:
+ return "65ms to 210ms";
+ case 9:
+ return "260ms to 900ms";
+ case 10:
+ return "1s to 3.5s";
+ case 13:
+ return "4s to 13s";
+ case 14:
+ return "17s to 64s";
+ default:
+ return "Unknown";
+ }
+}
+
+static void cap_express_dev2(struct device *d, int where, int type)
+{
+ u32 l;
+ u16 w;
+
+ l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
+ printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c",
+ cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)),
+ FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS));
+ if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
+ printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEV2_ARI));
+ else
+ printf("\n");
+
+ w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
+ printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c",
+ cap_express_dev2_timeout_value(PCI_EXP_DEV2_TIMEOUT_VALUE(w)),
+ FLAG(w, PCI_EXP_DEV2_TIMEOUT_DIS));
+ if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
+ printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEV2_ARI));
+ else
+ printf("\n");
+}
+
+static const char *cap_express_link2_speed(int type)
+{
+ switch (type)
+ {
+ case 0: /* hardwire to 0 means only the 2.5GT/s is supported */
+ case 1:
+ return "2.5GT/s";
+ case 2:
+ return "5GT/s";
+ default:
+ return "Unknown";
+ }
+}
+
+static const char *cap_express_link2_deemphasis(int type)
+{
+ switch (type)
+ {
+ case 0:
+ return "-6dB";
+ case 1:
+ return "-3.5dB";
+ default:
+ return "Unknown";
+ }
+}
+
+static const char *cap_express_link2_transmargin(int type)
+{
+ switch (type)
+ {
+ case 0:
+ return "Normal Operating Range";
+ case 1:
+ return "800-1200mV(full-swing)/400-700mV(half-swing)";
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ return "200-400mV(full-swing)/100-200mV(half-swing)";
+ default:
+ return "Unknown";
+ }
+}
+
+static void cap_express_link2(struct device *d, int where, int type UNUSED)
+{
+ u16 w;
+
+ w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
+ printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c, Selectable De-emphasis: %s\n"
+ "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
+ "\t\t\t Compliance De-emphasis: %s\n",
+ cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)),
+ FLAG(w, PCI_EXP_LNKCTL2_CMPLNC),
+ FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS),
+ cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)),
+ cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)),
+ FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC),
+ FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS),
+ cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w)));
+
+ w = get_conf_word(d, where + PCI_EXP_LNKSTA2);
+ printf("\t\tLnkSta2: Current De-emphasis Level: %s\n",
+ cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)));
+}
+
+static void cap_express_slot2(struct device *d UNUSED, int where UNUSED)
+{
+ /* No capabilities that require this field in PCIe rev2.0 spec. */
+}
+
static void
-show_express(struct device *d, int where, int cap)
+cap_express(struct device *d, int where, int cap)
{
int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
int size;
if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
return;
- show_express_dev(d, where, type);
- show_express_link(d, where, type);
+ cap_express_dev(d, where, type);
+ cap_express_link(d, where, type);
if (slot)
- show_express_slot(d, where);
+ cap_express_slot(d, where);
if (type == PCI_EXP_TYPE_ROOT_PORT)
- show_express_root(d, where);
+ cap_express_root(d, where);
+
+ if ((cap & PCI_EXP_FLAGS_VERS) < 2)
+ return;
+
+ size = 16;
+ if (slot)
+ size = 24;
+ if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size))
+ return;
+
+ cap_express_dev2(d, where, type);
+ cap_express_link2(d, where, type);
+ if (slot)
+ cap_express_slot2(d, where);
}
static void
-show_msix(struct device *d, int where, int cap)
+cap_msix(struct device *d, int where, int cap)
{
u32 off;
}
static void
-show_slotid(int cap)
+cap_slotid(int cap)
{
int esr = cap & 0xff;
int chs = cap >> 8;
}
static void
-show_ssvid(struct device *d, int where)
+cap_ssvid(struct device *d, int where)
{
u16 subsys_v, subsys_d;
char ssnamebuf[256];
}
static void
-show_dsn(struct device *d, int where)
+cap_dsn(struct device *d, int where)
{
u32 t1, t2;
if (!config_fetch(d, where + 4, 8))
t2 & 0xff, (t2 >> 8) & 0xff, (t2 >> 16) & 0xff, t2 >> 24);
}
+static void
+cap_debug_port(int cap)
+{
+ int bar = cap >> 13;
+ int pos = cap & 0x1fff;
+ printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
+}
+
+static void
+cap_aer(struct device *d, int where)
+{
+ u32 l;
+
+ printf("Advanced Error Reporting\n");
+ if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 24))
+ return;
+
+ l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS);
+ printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
+ "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
+ FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
+ FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
+ FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
+ FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
+ l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK);
+ printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
+ "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
+ FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
+ FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
+ FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
+ FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
+ l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER);
+ printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
+ "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
+ FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
+ FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
+ FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
+ FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
+ l = get_conf_long(d, where + PCI_ERR_COR_STATUS);
+ printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n",
+ FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
+ FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
+ l = get_conf_long(d, where + PCI_ERR_COR_MASK);
+ printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n",
+ FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
+ FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
+ l = get_conf_long(d, where + PCI_ERR_CAP);
+ printf("\t\tAERCap:\tFirst Error Pointer: %02x, GenCap%c CGenEn%c ChkCap%c ChkEn%c\n",
+ PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE),
+ FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE));
+
+}
+
+static void
+cap_acs(struct device *d, int where)
+{
+ u16 w;
+
+ printf("Access Control Services\n");
+ if (!config_fetch(d, where + PCI_ACS_CAP, 4))
+ return;
+
+ w = get_conf_word(d, where + PCI_ACS_CAP);
+ printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
+ "DirectTrans%c\n",
+ FLAG(w, PCI_ACS_CAP_VALID), FLAG(w, PCI_ACS_CAP_BLOCK), FLAG(w, PCI_ACS_CAP_REQ_RED),
+ FLAG(w, PCI_ACS_CAP_CMPLT_RED), FLAG(w, PCI_ACS_CAP_FORWARD), FLAG(w, PCI_ACS_CAP_EGRESS),
+ FLAG(w, PCI_ACS_CAP_TRANS));
+ w = get_conf_word(d, where + PCI_ACS_CTRL);
+ printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
+ "DirectTrans%c\n",
+ FLAG(w, PCI_ACS_CTRL_VALID), FLAG(w, PCI_ACS_CTRL_BLOCK), FLAG(w, PCI_ACS_CTRL_REQ_RED),
+ FLAG(w, PCI_ACS_CTRL_CMPLT_RED), FLAG(w, PCI_ACS_CTRL_FORWARD), FLAG(w, PCI_ACS_CTRL_EGRESS),
+ FLAG(w, PCI_ACS_CTRL_TRANS));
+}
+
+static void
+cap_ari(struct device *d, int where)
+{
+ u16 w;
+
+ printf("Alternative Routing-ID Interpretation (ARI)\n");
+ if (!config_fetch(d, where + PCI_ARI_CAP, 4))
+ return;
+
+ w = get_conf_word(d, where + PCI_ARI_CAP);
+ printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n",
+ FLAG(w, PCI_ARI_CAP_MFVC), FLAG(w, PCI_ARI_CAP_ACS),
+ PCI_ARI_CAP_NFN(w));
+ w = get_conf_word(d, where + PCI_ARI_CTRL);
+ printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n",
+ FLAG(w, PCI_ARI_CTRL_MFVC), FLAG(w, PCI_ARI_CTRL_ACS),
+ PCI_ARI_CTRL_FG(w));
+}
+
+static void
+cap_sriov(struct device *d, int where)
+{
+ u16 b;
+ u16 w;
+ u32 l;
+
+ printf("Single Root I/O Virtualization (SR-IOV)\n");
+ if (!config_fetch(d, where + PCI_IOV_CAP, 0x3c))
+ return;
+
+ l = get_conf_long(d, where + PCI_IOV_CAP);
+ printf("\t\tIOVCap:\tMigration%c, Interrupt Message Number: %03x\n",
+ FLAG(l, PCI_IOV_CAP_VFM), PCI_IOV_CAP_IMN(l));
+ w = get_conf_word(d, where + PCI_IOV_CTRL);
+ printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c\n",
+ FLAG(w, PCI_IOV_CTRL_VFE), FLAG(w, PCI_IOV_CTRL_VFME),
+ FLAG(w, PCI_IOV_CTRL_VFMIE), FLAG(w, PCI_IOV_CTRL_MSE),
+ FLAG(w, PCI_IOV_CTRL_ARI));
+ w = get_conf_word(d, where + PCI_IOV_STATUS);
+ printf("\t\tIOVSta:\tMigration%c\n", FLAG(w, PCI_IOV_STATUS_MS));
+ w = get_conf_word(d, where + PCI_IOV_INITIALVF);
+ printf("\t\tInitial VFs: %d, ", w);
+ w = get_conf_word(d, where + PCI_IOV_TOTALVF);
+ printf("Total VFs: %d, ", w);
+ w = get_conf_word(d, where + PCI_IOV_NUMVF);
+ printf("Number of VFs: %d, ", w);
+ b = get_conf_byte(d, where + PCI_IOV_FDL);
+ printf("Function Dependency Link: %02x\n", b);
+ w = get_conf_word(d, where + PCI_IOV_OFFSET);
+ printf("\t\tVF offset: %d, ", w);
+ w = get_conf_word(d, where + PCI_IOV_STRIDE);
+ printf("stride: %d, ", w);
+ w = get_conf_word(d, where + PCI_IOV_DID);
+ printf("Device ID: %04x\n", w);
+ l = get_conf_long(d, where + PCI_IOV_SUPPS);
+ printf("\t\tSupported Page Size: %08x, ", l);
+ l = get_conf_long(d, where + PCI_IOV_SYSPS);
+ printf("System Page Size: %08x\n", l);
+ printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l),
+ PCI_IOV_MSA_BIR(l));
+}
+
static void
show_ext_caps(struct device *d)
{
break;
id = header & 0xffff;
printf("\tCapabilities: [%03x] ", where);
- if (been_there[where++])
+ if (been_there[where]++)
{
printf("<chain looped>\n");
break;
switch (id)
{
case PCI_EXT_CAP_ID_AER:
- printf("Advanced Error Reporting\n");
- /* FIXME: Not decoded yet */
+ cap_aer(d, where);
break;
case PCI_EXT_CAP_ID_VC:
- printf("Virtual Channel\n");
- /* FIXME: Not decoded yet */
+ printf("Virtual Channel <?>\n");
break;
case PCI_EXT_CAP_ID_DSN:
- show_dsn(d, where);
+ cap_dsn(d, where);
break;
case PCI_EXT_CAP_ID_PB:
- printf("Power Budgeting\n");
- /* FIXME: Not decoded yet */
+ printf("Power Budgeting <?>\n");
break;
case PCI_EXT_CAP_ID_RCLINK:
- printf("Root Complex Link\n");
- /* FIXME: Not decoded yet */
+ printf("Root Complex Link <?>\n");
break;
case PCI_EXT_CAP_ID_RCILINK:
- printf("Root Complex Internal Link\n");
- /* FIXME: Not decoded yet */
+ printf("Root Complex Internal Link <?>\n");
break;
case PCI_EXT_CAP_ID_RCECOLL:
- printf("Root Complex Event Collector\n");
- /* FIXME: Not decoded yet */
+ printf("Root Complex Event Collector <?>\n");
break;
case PCI_EXT_CAP_ID_MFVC:
- printf("Multi-Function Virtual Channel\n");
- /* FIXME: Not decoded yet */
+ printf("Multi-Function Virtual Channel <?>\n");
break;
case PCI_EXT_CAP_ID_RBCB:
- printf("Root Bridge Control Block\n");
- /* FIXME: Not decoded yet */
+ printf("Root Bridge Control Block <?>\n");
break;
case PCI_EXT_CAP_ID_VNDR:
- printf("Vendor specific\n");
+ printf("Vendor Specific Information <?>\n");
break;
case PCI_EXT_CAP_ID_ACS:
- printf("Access Controls\n");
- /* FIXME: Not decoded yet */
+ cap_acs(d, where);
+ break;
+ case PCI_EXT_CAP_ID_ARI:
+ cap_ari(d, where);
+ break;
+ case PCI_EXT_CAP_ID_SRIOV:
+ cap_sriov(d, where);
break;
default:
printf("#%02x\n", id);
switch (id)
{
case PCI_CAP_ID_PM:
- show_pm(d, where, cap);
+ cap_pm(d, where, cap);
break;
case PCI_CAP_ID_AGP:
- show_agp(d, where, cap);
+ cap_agp(d, where, cap);
break;
case PCI_CAP_ID_VPD:
- printf("Vital Product Data\n");
+ printf("Vital Product Data <?>\n");
break;
case PCI_CAP_ID_SLOTID:
- show_slotid(cap);
+ cap_slotid(cap);
break;
case PCI_CAP_ID_MSI:
- show_msi(d, where, cap);
+ cap_msi(d, where, cap);
+ break;
+ case PCI_CAP_ID_CHSWP:
+ printf("CompactPCI hot-swap <?>\n");
break;
case PCI_CAP_ID_PCIX:
- show_pcix(d, where);
+ cap_pcix(d, where);
can_have_ext_caps = 1;
break;
case PCI_CAP_ID_HT:
- show_ht(d, where, cap);
+ cap_ht(d, where, cap);
break;
case PCI_CAP_ID_VNDR:
- show_vendor();
+ printf("Vendor Specific Information <?>\n");
break;
case PCI_CAP_ID_DBG:
- show_debug();
+ cap_debug_port(cap);
+ break;
+ case PCI_CAP_ID_CCRC:
+ printf("CompactPCI central resource control <?>\n");
+ break;
+ case PCI_CAP_ID_HOTPLUG:
+ printf("Hot-plug capable\n");
break;
case PCI_CAP_ID_SSVID:
- show_ssvid(d, where);
+ cap_ssvid(d, where);
+ break;
+ case PCI_CAP_ID_AGP3:
+ printf("AGP3 <?>\n");
+ break;
+ case PCI_CAP_ID_SECURE:
+ printf("Secure device <?>\n");
break;
case PCI_CAP_ID_EXP:
- show_express(d, where, cap);
+ cap_express(d, where, cap);
can_have_ext_caps = 1;
break;
case PCI_CAP_ID_MSIX:
- show_msix(d, where, cap);
+ cap_msix(d, where, cap);
+ break;
+ case PCI_CAP_ID_SATA:
+ printf("SATA HBA <?>\n");
+ break;
+ case PCI_CAP_ID_AF:
+ printf("PCIe advanced features <?>\n");
break;
default:
printf("#%02x [%04x]\n", id, cap);
show_ext_caps(d);
}
+/*** Kernel drivers ***/
+
+#ifdef PCI_OS_LINUX
+
+#include <sys/utsname.h>
+
+struct pcimap_entry {
+ struct pcimap_entry *next;
+ unsigned int vendor, device;
+ unsigned int subvendor, subdevice;
+ unsigned int class, class_mask;
+ char module[1];
+};
+
+static struct pcimap_entry *pcimap_head;
+
+static void
+load_pcimap(void)
+{
+ static int tried_pcimap;
+ struct utsname uts;
+ char *name, line[1024];
+ FILE *f;
+
+ if (tried_pcimap)
+ return;
+ tried_pcimap = 1;
+
+ if (name = opt_pcimap)
+ {
+ f = fopen(name, "r");
+ if (!f)
+ die("Cannot open pcimap file %s: %m", name);
+ }
+ else
+ {
+ if (uname(&uts) < 0)
+ die("uname() failed: %m");
+ name = alloca(64 + strlen(uts.release));
+ sprintf(name, "/lib/modules/%s/modules.pcimap", uts.release);
+ f = fopen(name, "r");
+ if (!f)
+ return;
+ }
+
+ while (fgets(line, sizeof(line), f))
+ {
+ char *c = strchr(line, '\n');
+ struct pcimap_entry *e;
+
+ if (!c)
+ die("Unterminated or too long line in %s", name);
+ *c = 0;
+ if (!line[0] || line[0] == '#')
+ continue;
+
+ c = line;
+ while (*c && *c != ' ' && *c != '\t')
+ c++;
+ if (!*c)
+ continue; /* FIXME: Emit warnings! */
+ *c++ = 0;
+
+ e = xmalloc(sizeof(*e) + strlen(line));
+ if (sscanf(c, "%i%i%i%i%i%i",
+ &e->vendor, &e->device,
+ &e->subvendor, &e->subdevice,
+ &e->class, &e->class_mask) != 6)
+ continue;
+ e->next = pcimap_head;
+ pcimap_head = e;
+ strcpy(e->module, line);
+ }
+ fclose(f);
+}
+
+static int
+match_pcimap(struct device *d, struct pcimap_entry *e)
+{
+ struct pci_dev *dev = d->dev;
+ unsigned int class = get_conf_long(d, PCI_REVISION_ID) >> 8;
+ word subv, subd;
+
+#define MATCH(x, y) ((y) > 0xffff || (x) == (y))
+ get_subid(d, &subv, &subd);
+ return
+ MATCH(dev->vendor_id, e->vendor) &&
+ MATCH(dev->device_id, e->device) &&
+ MATCH(subv, e->subvendor) &&
+ MATCH(subd, e->subdevice) &&
+ (class & e->class_mask) == e->class;
+#undef MATCH
+}
+
+#define DRIVER_BUF_SIZE 1024
+
+static char *
+find_driver(struct device *d, char *buf)
+{
+ struct pci_dev *dev = d->dev;
+ char name[1024], *drv, *base;
+ int n;
+
+ if (dev->access->method != PCI_ACCESS_SYS_BUS_PCI)
+ return NULL;
+
+ base = pci_get_param(dev->access, "sysfs.path");
+ if (!base || !base[0])
+ return NULL;
+
+ n = snprintf(name, sizeof(name), "%s/devices/%04x:%02x:%02x.%d/driver",
+ base, dev->domain, dev->bus, dev->dev, dev->func);
+ if (n < 0 || n >= (int)sizeof(name))
+ die("show_driver: sysfs device name too long, why?");
+
+ n = readlink(name, buf, DRIVER_BUF_SIZE);
+ if (n < 0)
+ return NULL;
+ if (n >= DRIVER_BUF_SIZE)
+ return "<name-too-long>";
+ buf[n] = 0;
+
+ if (drv = strrchr(buf, '/'))
+ return drv+1;
+ else
+ return buf;
+}
+
+static void
+show_kernel(struct device *d)
+{
+ char buf[DRIVER_BUF_SIZE];
+ char *driver;
+ struct pcimap_entry *e, *last = NULL;
+
+ if (driver = find_driver(d, buf))
+ printf("\tKernel driver in use: %s\n", driver);
+
+ load_pcimap();
+ for (e=pcimap_head; e; e=e->next)
+ if (match_pcimap(d, e) && (!last || strcmp(last->module, e->module)))
+ {
+ printf("%s %s", (last ? "," : "\tKernel modules:"), e->module);
+ last = e;
+ }
+ if (last)
+ putchar('\n');
+}
+
+static void
+show_kernel_machine(struct device *d)
+{
+ char buf[DRIVER_BUF_SIZE];
+ char *driver;
+ struct pcimap_entry *e, *last = NULL;
+
+ if (driver = find_driver(d, buf))
+ printf("Driver:\t%s\n", driver);
+
+ load_pcimap();
+ for (e=pcimap_head; e; e=e->next)
+ if (match_pcimap(d, e) && (!last || strcmp(last->module, e->module)))
+ {
+ printf("Module:\t%s\n", e->module);
+ last = e;
+ }
+}
+
+#else
+
+static void
+show_kernel(struct device *d UNUSED)
+{
+}
+
+static void
+show_kernel_machine(struct device *d UNUSED)
+{
+}
+
+#endif
+
+/*** Verbose output ***/
+
+static void
+show_size(pciaddr_t x)
+{
+ if (!x)
+ return;
+ printf(" [size=");
+ if (x < 1024)
+ printf("%d", (int) x);
+ else if (x < 1048576)
+ printf("%dK", (int)(x / 1024));
+ else if (x < 0x80000000)
+ printf("%dM", (int)(x / 1048576));
+ else
+ printf(PCIADDR_T_FMT, x);
+ putchar(']');
+}
+
+static void
+show_bases(struct device *d, int cnt)
+{
+ struct pci_dev *p = d->dev;
+ word cmd = get_conf_word(d, PCI_COMMAND);
+ int i;
+
+ for(i=0; i<cnt; i++)
+ {
+ pciaddr_t pos = p->base_addr[i];
+ pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
+ u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
+ if (flg == 0xffffffff)
+ flg = 0;
+ if (!pos && !flg && !len)
+ continue;
+ if (verbose > 1)
+ printf("\tRegion %d: ", i);
+ else
+ putchar('\t');
+ if (pos && !flg) /* Reported by the OS, but not by the device */
+ {
+ printf("[virtual] ");
+ flg = pos;
+ }
+ if (flg & PCI_BASE_ADDRESS_SPACE_IO)
+ {
+ pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
+ printf("I/O ports at ");
+ if (a)
+ printf(PCIADDR_PORT_FMT, a);
+ else if (flg & PCI_BASE_ADDRESS_IO_MASK)
+ printf("<ignored>");
+ else
+ printf("<unassigned>");
+ if (!(cmd & PCI_COMMAND_IO))
+ printf(" [disabled]");
+ }
+ else
+ {
+ int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
+ pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
+ int done = 0;
+ u32 z = 0;
+
+ printf("Memory at ");
+ if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
+ {
+ if (i >= cnt - 1)
+ {
+ printf("<invalid-64bit-slot>");
+ done = 1;
+ }
+ else
+ {
+ i++;
+ z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
+ if (opt_buscentric)
+ {
+ u32 y = a & 0xffffffff;
+ if (a || z)
+ printf("%08x%08x", z, y);
+ else
+ printf("<unassigned>");
+ done = 1;
+ }
+ }
+ }
+ if (!done)
+ {
+ if (a)
+ printf(PCIADDR_T_FMT, a);
+ else
+ printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
+ }
+ printf(" (%s, %sprefetchable)",
+ (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
+ (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
+ (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
+ (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
+ if (!(cmd & PCI_COMMAND_MEMORY))
+ printf(" [disabled]");
+ }
+ show_size(len);
+ putchar('\n');
+ }
+}
+
+static void
+show_rom(struct device *d, int reg)
+{
+ struct pci_dev *p = d->dev;
+ pciaddr_t rom = p->rom_base_addr;
+ pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
+ u32 flg = get_conf_long(d, reg);
+ word cmd = get_conf_word(d, PCI_COMMAND);
+
+ if (!rom && !flg && !len)
+ return;
+ putchar('\t');
+ if ((rom & PCI_ROM_ADDRESS_MASK) && !(flg & PCI_ROM_ADDRESS_MASK))
+ {
+ printf("[virtual] ");
+ flg = rom;
+ }
+ printf("Expansion ROM at ");
+ if (rom & PCI_ROM_ADDRESS_MASK)
+ printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
+ else if (flg & PCI_ROM_ADDRESS_MASK)
+ printf("<ignored>");
+ else
+ printf("<unassigned>");
+ if (!(flg & PCI_ROM_ADDRESS_ENABLE))
+ printf(" [disabled]");
+ else if (!(cmd & PCI_COMMAND_MEMORY))
+ printf(" [disabled by cmd]");
+ show_size(len);
+ putchar('\n');
+}
+
static void
show_htype0(struct device *d)
{
show_rom(d, PCI_ROM_ADDRESS1);
if (verbose > 1)
- printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
- FLAG(brc, PCI_BRIDGE_CTL_PARITY),
- FLAG(brc, PCI_BRIDGE_CTL_SERR),
- FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
- FLAG(brc, PCI_BRIDGE_CTL_VGA),
- FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
- FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
- FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
+ {
+ printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
+ FLAG(brc, PCI_BRIDGE_CTL_PARITY),
+ FLAG(brc, PCI_BRIDGE_CTL_SERR),
+ FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
+ FLAG(brc, PCI_BRIDGE_CTL_VGA),
+ FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
+ FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
+ FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
+ printf("\t\tPriDiscTmr%c SecDiscTmr%c DiscTmrStat%c DiscTmrSERREn%c\n",
+ FLAG(brc, PCI_BRIDGE_CTL_PRI_DISCARD_TIMER),
+ FLAG(brc, PCI_BRIDGE_CTL_SEC_DISCARD_TIMER),
+ FLAG(brc, PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS),
+ FLAG(brc, PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN));
+ }
show_caps(d);
}
byte max_lat, min_gnt;
byte int_pin = get_conf_byte(d, PCI_INTERRUPT_PIN);
unsigned int irq = p->irq;
- word subsys_v = 0, subsys_d = 0;
+ word subsys_v, subsys_d;
char ssnamebuf[256];
show_terse(d);
printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
max_lat = get_conf_byte(d, PCI_MAX_LAT);
min_gnt = get_conf_byte(d, PCI_MIN_GNT);
- subsys_v = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
- subsys_d = get_conf_word(d, PCI_SUBSYSTEM_ID);
break;
case PCI_HEADER_TYPE_BRIDGE:
if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
min_gnt = max_lat = 0;
- if (d->config_cached >= 128)
- {
- subsys_v = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
- subsys_d = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
- }
break;
default:
printf("\t!!! Unknown header type %02x\n", htype);
return;
}
+ get_subid(d, &subsys_v, &subsys_d);
if (subsys_v && subsys_v != 0xffff)
printf("\tSubsystem: %s\n",
pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
if (verbose > 1)
{
- printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c\n",
+ printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c DisINTx%c\n",
FLAG(cmd, PCI_COMMAND_IO),
FLAG(cmd, PCI_COMMAND_MEMORY),
FLAG(cmd, PCI_COMMAND_MASTER),
FLAG(cmd, PCI_COMMAND_PARITY),
FLAG(cmd, PCI_COMMAND_WAIT),
FLAG(cmd, PCI_COMMAND_SERR),
- FLAG(cmd, PCI_COMMAND_FAST_BACK));
- printf("\tStatus: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c\n",
+ FLAG(cmd, PCI_COMMAND_FAST_BACK),
+ FLAG(cmd, PCI_COMMAND_DISABLE_INTx));
+ printf("\tStatus: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c INTx%c\n",
FLAG(status, PCI_STATUS_CAP_LIST),
FLAG(status, PCI_STATUS_66MHZ),
FLAG(status, PCI_STATUS_UDF),
FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
- FLAG(status, PCI_STATUS_DETECTED_PARITY));
+ FLAG(status, PCI_STATUS_DETECTED_PARITY),
+ FLAG(status, PCI_STATUS_INTx));
if (cmd & PCI_COMMAND_MASTER)
{
printf("\tLatency: %d", latency);
}
}
+/*** Machine-readable dumps ***/
+
static void
show_hex_dump(struct device *d)
{
unsigned int i, cnt;
cnt = d->config_cached;
- if (show_hex >= 3 && config_fetch(d, cnt, 256-cnt))
+ if (opt_hex >= 3 && config_fetch(d, cnt, 256-cnt))
{
cnt = 256;
- if (show_hex >= 4 && config_fetch(d, 256, 4096-256))
+ if (opt_hex >= 4 && config_fetch(d, 256, 4096-256))
cnt = 4096;
}
{
struct pci_dev *p = d->dev;
int c;
- word sv_id=0, sd_id=0;
+ word sv_id, sd_id;
char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
- switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
- {
- case PCI_HEADER_TYPE_NORMAL:
- sv_id = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
- sd_id = get_conf_word(d, PCI_SUBSYSTEM_ID);
- break;
- case PCI_HEADER_TYPE_CARDBUS:
- if (d->config_cached >= 128)
- {
- sv_id = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
- sd_id = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
- }
- break;
- }
+ get_subid(d, &sv_id, &sd_id);
if (verbose)
{
- printf((machine_readable >= 2) ? "Slot:\t" : "Device:\t");
+ printf((opt_machine >= 2) ? "Slot:\t" : "Device:\t");
show_slot_name(d);
putchar('\n');
printf("Class:\t%s\n",
printf("Rev:\t%02x\n", c);
if (c = get_conf_byte(d, PCI_CLASS_PROG))
printf("ProgIf:\t%02x\n", c);
+ if (opt_kernel)
+ show_kernel_machine(d);
}
else
{
}
}
+/*** Main show function ***/
+
static void
show_device(struct device *d)
{
- if (machine_readable)
+ if (opt_machine)
show_machine(d);
- else if (verbose)
- show_verbose(d);
else
- show_terse(d);
- if (show_hex)
+ {
+ if (verbose)
+ show_verbose(d);
+ else
+ show_terse(d);
+ if (opt_kernel || verbose)
+ show_kernel(d);
+ }
+ if (opt_hex)
show_hex_dump(d);
- if (verbose || show_hex)
+ if (verbose || opt_hex)
putchar('\n');
}
show_device(d);
}
-/* Tree output */
+/*** Tree output ***/
struct bridge {
struct bridge *chain; /* Single-linked list of bridges */
show_tree_bridge(&host_bridge, line, line);
}
-/* Bus mapping mode */
+/*** Bus mapping mode ***/
struct bus_bridge {
struct bus_bridge *next;
break;
case 'b':
pacc->buscentric = 1;
- buscentric_view = 1;
+ opt_buscentric = 1;
break;
case 's':
if (msg = pci_filter_parse_slot(&filter, optarg))
die("-d: %s", msg);
break;
case 'x':
- show_hex++;
+ opt_hex++;
break;
case 't':
- show_tree++;
+ opt_tree++;
break;
case 'i':
pci_set_name_list_path(pacc, optarg, 0);
break;
case 'm':
- machine_readable++;
+ opt_machine++;
+ break;
+ case 'p':
+ opt_pcimap = optarg;
break;
+#ifdef PCI_OS_LINUX
+ case 'k':
+ opt_kernel++;
+ break;
+#endif
case 'M':
- map_mode++;
+ opt_map_mode++;
break;
case 'D':
- show_domains = 2;
+ opt_domains = 2;
break;
+#ifdef PCI_USE_DNS
+ case 'q':
+ opt_query_dns++;
+ break;
+ case 'Q':
+ opt_query_all = 1;
+ break;
+#else
+ case 'q':
+ case 'Q':
+ die("DNS queries are not available in this version");
+#endif
default:
if (parse_generic_option(i, pacc, optarg))
break;
if (optind < argc)
goto bad;
+ if (opt_query_dns)
+ {
+ pacc->id_lookup_mode |= PCI_LOOKUP_NETWORK;
+ if (opt_query_dns > 1)
+ pacc->id_lookup_mode |= PCI_LOOKUP_REFRESH_CACHE;
+ }
+ if (opt_query_all)
+ pacc->id_lookup_mode |= PCI_LOOKUP_NETWORK | PCI_LOOKUP_SKIP_LOCAL;
+
pci_init(pacc);
- if (map_mode)
+ if (opt_map_mode)
map_the_bus();
else
{
scan_devices();
sort_them();
- if (show_tree)
+ if (opt_tree)
show_forest();
else
show();
projects / pciutils.git / blobdiff