if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
(type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
printf(" RCB %d bytes,", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
- printf(" Disabled%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
+ printf(" LnkDisable%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
FLAG(w, PCI_EXP_LNKCTL_DISABLE),
FLAG(w, PCI_EXP_LNKCTL_CLOCK),
FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK));
printf("\n");
}
- printf("\t\t\t IDOReq%c IDOCompl%c LTR%c 10BitTagReq%c OBFF %s\n",
+ printf("\t\t\t IDOReq%c IDOCompl%c LTR%c EmergencyPowerReductionReq%c\n",
FLAG(w, PCI_EXP_DEVCTL2_IDO_REQ_EN),
FLAG(w, PCI_EXP_DEVCTL2_IDO_CMP_EN),
FLAG(w, PCI_EXP_DEVCTL2_LTR),
+ FLAG(w, PCI_EXP_DEVCTL2_EPR_REQ));
+ printf("\t\t\t 10BitTagReq%c OBFF %s, EETLPPrefixBlk%c\n",
FLAG(w, PCI_EXP_DEVCTL2_10BIT_TAG_REQ),
- cap_express_devctl2_obff(PCI_EXP_DEVCTL2_OBFF(w)));
+ cap_express_devctl2_obff(PCI_EXP_DEVCTL2_OBFF(w)),
+ FLAG(w, PCI_EXP_DEVCTL2_EE_TLP_BLK));
}
static const char *cap_express_link2_speed_cap(int vector)
* permitted to skip support for any data rates between 2.5GT/s and the
* highest supported rate.
*/
- if (vector & 0x60)
+ if (vector & 0x40)
return "RsvdP";
+ if (vector & 0x20)
+ return "2.5-64GT/s";
if (vector & 0x10)
return "2.5-32GT/s";
if (vector & 0x08)
default:
printf("Unknown type %d", type);
}
- printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
+ printf(", IntMsgNum %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
if (verbose < 2)
return type;
break;
case PCI_CAP_ID_EXP:
type = cap_express(d, where, cap);
+ struct pci_cap* test = pci_find_cap(d->dev, PCI_CAP_ID_EXP, PCI_CAP_NORMAL);
can_have_ext_caps = 1;
break;
case PCI_CAP_ID_MSIX: