2 ******************************************************************************
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3 * @file startup_stm32f030x8.s
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4 * @author MCD Application Team
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5 * @brief STM32F030x8 devices vector table for GCC toolchain.
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6 * This module performs:
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7 * - Set the initial SP
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8 * - Set the initial PC == Reset_Handler,
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9 * - Set the vector table entries with the exceptions ISR address
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10 * - Branches to main in the C library (which eventually
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12 * After Reset the Cortex-M0 processor is in Thread mode,
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13 * priority is Privileged, and the Stack is set to Main.
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14 ******************************************************************************
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16 * Redistribution and use in source and binary forms, with or without modification,
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17 * are permitted provided that the following conditions are met:
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18 * 1. Redistributions of source code must retain the above copyright notice,
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19 * this list of conditions and the following disclaimer.
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20 * 2. Redistributions in binary form must reproduce the above copyright notice,
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21 * this list of conditions and the following disclaimer in the documentation
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22 * and/or other materials provided with the distribution.
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23 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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24 * may be used to endorse or promote products derived from this software
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25 * without specific prior written permission.
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27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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28 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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30 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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33 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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34 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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38 ******************************************************************************
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46 .global g_pfnVectors
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47 .global Default_Handler
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49 /* start address for the initialization values of the .data section.
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50 defined in linker script */
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52 /* start address for the .data section. defined in linker script */
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54 /* end address for the .data section. defined in linker script */
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56 /* start address for the .bss section. defined in linker script */
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58 /* end address for the .bss section. defined in linker script */
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61 .section .text.Reset_Handler
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63 .type Reset_Handler, %function
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66 mov sp, r0 /* set stack pointer */
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68 /* Copy the data segment initializers from flash to SRAM */
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85 /* Zero fill the bss segment. */
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99 /* Call the clock system intitialization function.*/
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101 /* Call static constructors */
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102 bl __libc_init_array
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103 /* Call the application's entry point.*/
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110 .size Reset_Handler, .-Reset_Handler
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113 * @brief This is the code that gets called when the processor receives an
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114 * unexpected interrupt. This simply enters an infinite loop, preserving
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115 * the system state for examination by a debugger.
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120 .section .text.Default_Handler,"ax",%progbits
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124 .size Default_Handler, .-Default_Handler
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125 /******************************************************************************
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127 * The minimal vector table for a Cortex M0. Note that the proper constructs
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128 * must be placed on this to ensure that it ends up at physical address
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131 ******************************************************************************/
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132 .section .isr_vector,"a",%progbits
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133 .type g_pfnVectors, %object
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134 .size g_pfnVectors, .-g_pfnVectors
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139 .word Reset_Handler
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141 .word HardFault_Handler
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152 .word PendSV_Handler
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153 .word SysTick_Handler
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154 .word WWDG_IRQHandler /* Window WatchDog */
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155 .word 0 /* Reserved */
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156 .word RTC_IRQHandler /* RTC through the EXTI line */
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157 .word FLASH_IRQHandler /* FLASH */
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158 .word RCC_IRQHandler /* RCC */
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159 .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
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160 .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
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161 .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
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162 .word 0 /* Reserved */
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163 .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
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164 .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
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165 .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */
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166 .word ADC1_IRQHandler /* ADC1 */
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167 .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
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168 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
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169 .word 0 /* Reserved */
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170 .word TIM3_IRQHandler /* TIM3 */
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171 .word TIM6_IRQHandler /* TIM6 */
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172 .word 0 /* Reserved */
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173 .word TIM14_IRQHandler /* TIM14 */
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174 .word TIM15_IRQHandler /* TIM15 */
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175 .word TIM16_IRQHandler /* TIM16 */
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176 .word TIM17_IRQHandler /* TIM17 */
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177 .word I2C1_IRQHandler /* I2C1 */
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178 .word I2C2_IRQHandler /* I2C2 */
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179 .word SPI1_IRQHandler /* SPI1 */
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180 .word SPI2_IRQHandler /* SPI2 */
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181 .word USART1_IRQHandler /* USART1 */
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182 .word USART2_IRQHandler /* USART2 */
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183 .word 0 /* Reserved */
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184 .word 0 /* Reserved */
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185 .word 0 /* Reserved */
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187 /*******************************************************************************
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189 * Provide weak aliases for each Exception handler to the Default_Handler.
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190 * As they are weak aliases, any function with the same name will override
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193 *******************************************************************************/
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196 .thumb_set NMI_Handler,Default_Handler
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198 .weak HardFault_Handler
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199 .thumb_set HardFault_Handler,Default_Handler
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202 .thumb_set SVC_Handler,Default_Handler
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204 .weak PendSV_Handler
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205 .thumb_set PendSV_Handler,Default_Handler
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207 .weak SysTick_Handler
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208 .thumb_set SysTick_Handler,Default_Handler
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210 .weak WWDG_IRQHandler
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211 .thumb_set WWDG_IRQHandler,Default_Handler
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213 .weak RTC_IRQHandler
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214 .thumb_set RTC_IRQHandler,Default_Handler
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216 .weak FLASH_IRQHandler
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217 .thumb_set FLASH_IRQHandler,Default_Handler
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219 .weak RCC_IRQHandler
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220 .thumb_set RCC_IRQHandler,Default_Handler
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222 .weak EXTI0_1_IRQHandler
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223 .thumb_set EXTI0_1_IRQHandler,Default_Handler
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225 .weak EXTI2_3_IRQHandler
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226 .thumb_set EXTI2_3_IRQHandler,Default_Handler
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228 .weak EXTI4_15_IRQHandler
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229 .thumb_set EXTI4_15_IRQHandler,Default_Handler
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231 .weak DMA1_Channel1_IRQHandler
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232 .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
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234 .weak DMA1_Channel2_3_IRQHandler
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235 .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
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237 .weak DMA1_Channel4_5_IRQHandler
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238 .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
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240 .weak ADC1_IRQHandler
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241 .thumb_set ADC1_IRQHandler,Default_Handler
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243 .weak TIM1_BRK_UP_TRG_COM_IRQHandler
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244 .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
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246 .weak TIM1_CC_IRQHandler
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247 .thumb_set TIM1_CC_IRQHandler,Default_Handler
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249 .weak TIM3_IRQHandler
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250 .thumb_set TIM3_IRQHandler,Default_Handler
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252 .weak TIM6_IRQHandler
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253 .thumb_set TIM6_IRQHandler,Default_Handler
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255 .weak TIM14_IRQHandler
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256 .thumb_set TIM14_IRQHandler,Default_Handler
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258 .weak TIM15_IRQHandler
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259 .thumb_set TIM15_IRQHandler,Default_Handler
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261 .weak TIM16_IRQHandler
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262 .thumb_set TIM16_IRQHandler,Default_Handler
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264 .weak TIM17_IRQHandler
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265 .thumb_set TIM17_IRQHandler,Default_Handler
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267 .weak I2C1_IRQHandler
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268 .thumb_set I2C1_IRQHandler,Default_Handler
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270 .weak I2C2_IRQHandler
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271 .thumb_set I2C2_IRQHandler,Default_Handler
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273 .weak SPI1_IRQHandler
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274 .thumb_set SPI1_IRQHandler,Default_Handler
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276 .weak SPI2_IRQHandler
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277 .thumb_set SPI2_IRQHandler,Default_Handler
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279 .weak USART1_IRQHandler
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280 .thumb_set USART1_IRQHandler,Default_Handler
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282 .weak USART2_IRQHandler
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283 .thumb_set USART2_IRQHandler,Default_Handler
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285 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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