2 ******************************************************************************
3 * @file startup_stm32f030x8.s
4 * @author MCD Application Team
5 * @brief STM32F030x8 devices vector table for GCC toolchain.
6 * This module performs:
8 * - Set the initial PC == Reset_Handler,
9 * - Set the vector table entries with the exceptions ISR address
10 * - Branches to main in the C library (which eventually
12 * After Reset the Cortex-M0 processor is in Thread mode,
13 * priority is Privileged, and the Stack is set to Main.
14 ******************************************************************************
16 * Redistribution and use in source and binary forms, with or without modification,
17 * are permitted provided that the following conditions are met:
18 * 1. Redistributions of source code must retain the above copyright notice,
19 * this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 * this list of conditions and the following disclaimer in the documentation
22 * and/or other materials provided with the distribution.
23 * 3. Neither the name of STMicroelectronics nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
28 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
30 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
33 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
34 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 ******************************************************************************
47 .global Default_Handler
49 /* start address for the initialization values of the .data section.
50 defined in linker script */
52 /* start address for the .data section. defined in linker script */
54 /* end address for the .data section. defined in linker script */
56 /* start address for the .bss section. defined in linker script */
58 /* end address for the .bss section. defined in linker script */
61 .section .text.Reset_Handler
63 .type Reset_Handler, %function
66 mov sp, r0 /* set stack pointer */
68 /* Copy the data segment initializers from flash to SRAM */
85 /* Zero fill the bss segment. */
99 /* Call the clock system intitialization function.*/
101 /* Call static constructors */
103 /* Call the application's entry point.*/
110 .size Reset_Handler, .-Reset_Handler
113 * @brief This is the code that gets called when the processor receives an
114 * unexpected interrupt. This simply enters an infinite loop, preserving
115 * the system state for examination by a debugger.
120 .section .text.Default_Handler,"ax",%progbits
124 .size Default_Handler, .-Default_Handler
125 /******************************************************************************
127 * The minimal vector table for a Cortex M0. Note that the proper constructs
128 * must be placed on this to ensure that it ends up at physical address
131 ******************************************************************************/
132 .section .isr_vector,"a",%progbits
133 .type g_pfnVectors, %object
134 .size g_pfnVectors, .-g_pfnVectors
141 .word HardFault_Handler
153 .word SysTick_Handler
154 .word WWDG_IRQHandler /* Window WatchDog */
155 .word 0 /* Reserved */
156 .word RTC_IRQHandler /* RTC through the EXTI line */
157 .word FLASH_IRQHandler /* FLASH */
158 .word RCC_IRQHandler /* RCC */
159 .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
160 .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
161 .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
162 .word 0 /* Reserved */
163 .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
164 .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
165 .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */
166 .word ADC1_IRQHandler /* ADC1 */
167 .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
168 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
169 .word 0 /* Reserved */
170 .word TIM3_IRQHandler /* TIM3 */
171 .word TIM6_IRQHandler /* TIM6 */
172 .word 0 /* Reserved */
173 .word TIM14_IRQHandler /* TIM14 */
174 .word TIM15_IRQHandler /* TIM15 */
175 .word TIM16_IRQHandler /* TIM16 */
176 .word TIM17_IRQHandler /* TIM17 */
177 .word I2C1_IRQHandler /* I2C1 */
178 .word I2C2_IRQHandler /* I2C2 */
179 .word SPI1_IRQHandler /* SPI1 */
180 .word SPI2_IRQHandler /* SPI2 */
181 .word USART1_IRQHandler /* USART1 */
182 .word USART2_IRQHandler /* USART2 */
183 .word 0 /* Reserved */
184 .word 0 /* Reserved */
185 .word 0 /* Reserved */
187 /*******************************************************************************
189 * Provide weak aliases for each Exception handler to the Default_Handler.
190 * As they are weak aliases, any function with the same name will override
193 *******************************************************************************/
196 .thumb_set NMI_Handler,Default_Handler
198 .weak HardFault_Handler
199 .thumb_set HardFault_Handler,Default_Handler
202 .thumb_set SVC_Handler,Default_Handler
205 .thumb_set PendSV_Handler,Default_Handler
207 .weak SysTick_Handler
208 .thumb_set SysTick_Handler,Default_Handler
210 .weak WWDG_IRQHandler
211 .thumb_set WWDG_IRQHandler,Default_Handler
214 .thumb_set RTC_IRQHandler,Default_Handler
216 .weak FLASH_IRQHandler
217 .thumb_set FLASH_IRQHandler,Default_Handler
220 .thumb_set RCC_IRQHandler,Default_Handler
222 .weak EXTI0_1_IRQHandler
223 .thumb_set EXTI0_1_IRQHandler,Default_Handler
225 .weak EXTI2_3_IRQHandler
226 .thumb_set EXTI2_3_IRQHandler,Default_Handler
228 .weak EXTI4_15_IRQHandler
229 .thumb_set EXTI4_15_IRQHandler,Default_Handler
231 .weak DMA1_Channel1_IRQHandler
232 .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
234 .weak DMA1_Channel2_3_IRQHandler
235 .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
237 .weak DMA1_Channel4_5_IRQHandler
238 .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
240 .weak ADC1_IRQHandler
241 .thumb_set ADC1_IRQHandler,Default_Handler
243 .weak TIM1_BRK_UP_TRG_COM_IRQHandler
244 .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
246 .weak TIM1_CC_IRQHandler
247 .thumb_set TIM1_CC_IRQHandler,Default_Handler
249 .weak TIM3_IRQHandler
250 .thumb_set TIM3_IRQHandler,Default_Handler
252 .weak TIM6_IRQHandler
253 .thumb_set TIM6_IRQHandler,Default_Handler
255 .weak TIM14_IRQHandler
256 .thumb_set TIM14_IRQHandler,Default_Handler
258 .weak TIM15_IRQHandler
259 .thumb_set TIM15_IRQHandler,Default_Handler
261 .weak TIM16_IRQHandler
262 .thumb_set TIM16_IRQHandler,Default_Handler
264 .weak TIM17_IRQHandler
265 .thumb_set TIM17_IRQHandler,Default_Handler
267 .weak I2C1_IRQHandler
268 .thumb_set I2C1_IRQHandler,Default_Handler
270 .weak I2C2_IRQHandler
271 .thumb_set I2C2_IRQHandler,Default_Handler
273 .weak SPI1_IRQHandler
274 .thumb_set SPI1_IRQHandler,Default_Handler
276 .weak SPI2_IRQHandler
277 .thumb_set SPI2_IRQHandler,Default_Handler
279 .weak USART1_IRQHandler
280 .thumb_set USART1_IRQHandler,Default_Handler
282 .weak USART2_IRQHandler
283 .thumb_set USART2_IRQHandler,Default_Handler
285 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/