2 * The PCI Utilities -- List All PCI Devices
4 * Copyright (c) 1997--2007 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
19 static int verbose; /* Show detailed information */
20 static int opt_buscentric; /* Show bus addresses/IRQ's instead of CPU-visible ones */
21 static int opt_hex; /* Show contents of config space as hexadecimal numbers */
22 static struct pci_filter filter; /* Device filter */
23 static int opt_tree; /* Show bus tree */
24 static int opt_machine; /* Generate machine-readable output */
25 static int opt_map_mode; /* Bus mapping mode enabled */
26 static int opt_domains; /* Show domain numbers (0=disabled, 1=auto-detected, 2=requested) */
28 const char program_name[] = "lspci";
30 static char options[] = "nvbxs:d:ti:mgMD" GENERIC_OPTIONS ;
32 static char help_msg[] = "\
33 Usage: lspci [<switches>]\n\
36 -n\t\tShow numeric ID's\n\
37 -nn\t\tShow both textual and numeric ID's (names & numbers)\n\
38 -b\t\tBus-centric view (PCI addresses and IRQ's instead of those seen by the CPU)\n\
39 -x\t\tShow hex-dump of the standard portion of config space\n\
40 -xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n\
41 -xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n\
42 -s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n\
43 -d [<vendor>]:[<device>]\tShow only selected devices\n\
44 -t\t\tShow bus tree\n\
45 -m\t\tProduce machine-readable output\n\
46 -i <file>\tUse specified ID database instead of %s\n\
47 -D\t\tAlways show domain numbers\n\
48 -M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
52 /*** Communication with libpci ***/
54 static struct pci_access *pacc;
57 * If we aren't being compiled by GCC, use xmalloc() instead of alloca().
58 * This increases our memory footprint, but only slightly since we don't
61 #if defined (__FreeBSD__) || defined (__NetBSD__) || defined (__OpenBSD__) || defined (__DragonFly__)
62 /* alloca() is defined in stdlib.h */
63 #elif defined(__GNUC__) && !defined(PCI_OS_WINDOWS)
67 #define alloca xmalloc
70 /*** Our view of the PCI bus ***/
75 unsigned int config_cached, config_bufsize;
76 byte *config; /* Cached configuration space data */
77 byte *present; /* Maps which configuration bytes are present */
80 static struct device *first_dev;
81 static int seen_errors;
84 config_fetch(struct device *d, unsigned int pos, unsigned int len)
86 unsigned int end = pos+len;
89 while (pos < d->config_bufsize && len && d->present[pos])
91 while (pos+len <= d->config_bufsize && len && d->present[pos+len-1])
96 if (end > d->config_bufsize)
98 int orig_size = d->config_bufsize;
99 while (end > d->config_bufsize)
100 d->config_bufsize *= 2;
101 d->config = xrealloc(d->config, d->config_bufsize);
102 d->present = xrealloc(d->present, d->config_bufsize);
103 memset(d->present + orig_size, 0, d->config_bufsize - orig_size);
105 result = pci_read_block(d->dev, pos, d->config + pos, len);
107 memset(d->present + pos, 1, len);
111 static struct device *
112 scan_device(struct pci_dev *p)
116 if (p->domain && !opt_domains)
118 if (!pci_filter_match(&filter, p))
120 d = xmalloc(sizeof(struct device));
121 memset(d, 0, sizeof(*d));
123 d->config_cached = d->config_bufsize = 64;
124 d->config = xmalloc(64);
125 d->present = xmalloc(64);
126 memset(d->present, 1, 64);
127 if (!pci_read_block(p, 0, d->config, 64))
129 fprintf(stderr, "lspci: Unable to read the standard configuration space header of device %04x:%02x:%02x.%d\n",
130 p->domain, p->bus, p->dev, p->func);
134 if ((d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
136 /* For cardbus bridges, we need to fetch 64 bytes more to get the
137 * full standard header... */
138 if (config_fetch(d, 64, 64))
139 d->config_cached += 64;
141 pci_setup_cache(p, d->config, d->config_cached);
142 pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_CLASS | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
153 for(p=pacc->devices; p; p=p->next)
154 if (d = scan_device(p))
161 /*** Config space accesses ***/
164 check_conf_range(struct device *d, unsigned int pos, unsigned int len)
167 if (!d->present[pos])
168 die("Internal bug: Accessing non-read configuration byte at position %x", pos);
174 get_conf_byte(struct device *d, unsigned int pos)
176 check_conf_range(d, pos, 1);
177 return d->config[pos];
181 get_conf_word(struct device *d, unsigned int pos)
183 check_conf_range(d, pos, 2);
184 return d->config[pos] | (d->config[pos+1] << 8);
188 get_conf_long(struct device *d, unsigned int pos)
190 check_conf_range(d, pos, 4);
191 return d->config[pos] |
192 (d->config[pos+1] << 8) |
193 (d->config[pos+2] << 16) |
194 (d->config[pos+3] << 24);
200 compare_them(const void *A, const void *B)
202 const struct pci_dev *a = (*(const struct device **)A)->dev;
203 const struct pci_dev *b = (*(const struct device **)B)->dev;
205 if (a->domain < b->domain)
207 if (a->domain > b->domain)
217 if (a->func < b->func)
219 if (a->func > b->func)
227 struct device **index, **h, **last_dev;
232 for(d=first_dev; d; d=d->next)
234 h = index = alloca(sizeof(struct device *) * cnt);
235 for(d=first_dev; d; d=d->next)
237 qsort(index, cnt, sizeof(struct device *), compare_them);
238 last_dev = &first_dev;
243 last_dev = &(*h)->next;
249 /*** Normal output ***/
251 #define FLAG(x,y) ((x & y) ? '+' : '-')
254 show_slot_name(struct device *d)
256 struct pci_dev *p = d->dev;
258 if (!opt_machine ? opt_domains : (p->domain || opt_domains >= 2))
259 printf("%04x:", p->domain);
260 printf("%02x:%02x.%d", p->bus, p->dev, p->func);
264 show_terse(struct device *d)
267 struct pci_dev *p = d->dev;
268 char classbuf[128], devbuf[128];
272 pci_lookup_name(pacc, classbuf, sizeof(classbuf),
275 pci_lookup_name(pacc, devbuf, sizeof(devbuf),
276 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
277 p->vendor_id, p->device_id));
278 if (c = get_conf_byte(d, PCI_REVISION_ID))
279 printf(" (rev %02x)", c);
283 c = get_conf_byte(d, PCI_CLASS_PROG);
284 x = pci_lookup_name(pacc, devbuf, sizeof(devbuf),
285 PCI_LOOKUP_PROGIF | PCI_LOOKUP_NO_NUMBERS,
289 printf(" (prog-if %02x", c);
298 /*** Capabilities ***/
301 cap_pm(struct device *d, int where, int cap)
304 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
306 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
309 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
310 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
311 FLAG(cap, PCI_PM_CAP_DSI),
312 FLAG(cap, PCI_PM_CAP_D1),
313 FLAG(cap, PCI_PM_CAP_D2),
314 pm_aux_current[(cap >> 6) & 7],
315 FLAG(cap, PCI_PM_CAP_PME_D0),
316 FLAG(cap, PCI_PM_CAP_PME_D1),
317 FLAG(cap, PCI_PM_CAP_PME_D2),
318 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
319 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
320 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
322 t = get_conf_word(d, where + PCI_PM_CTRL);
323 printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
324 t & PCI_PM_CTRL_STATE_MASK,
325 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
326 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
327 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
328 FLAG(t, PCI_PM_CTRL_PME_STATUS));
329 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
331 printf("\t\tBridge: PM%c B3%c\n",
332 FLAG(t, PCI_PM_BPCC_ENABLE),
333 FLAG(~t, PCI_PM_PPB_B2_B3));
337 format_agp_rate(int rate, char *buf, int agp3)
347 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
352 strcpy(buf, "<none>");
356 cap_agp(struct device *d, int where, int cap)
363 ver = (cap >> 4) & 0x0f;
365 printf("AGP version %x.%x\n", ver, rev);
368 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
370 t = get_conf_long(d, where + PCI_AGP_STATUS);
371 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
373 format_agp_rate(t & 7, rate, agp3);
374 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
375 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
376 FLAG(t, PCI_AGP_STATUS_ISOCH),
377 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
378 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
379 FLAG(t, PCI_AGP_STATUS_SBA),
380 FLAG(t, PCI_AGP_STATUS_ITA_COH),
381 FLAG(t, PCI_AGP_STATUS_GART64),
382 FLAG(t, PCI_AGP_STATUS_HTRANS),
383 FLAG(t, PCI_AGP_STATUS_64BIT),
384 FLAG(t, PCI_AGP_STATUS_FW),
385 FLAG(t, PCI_AGP_STATUS_AGP3),
387 t = get_conf_long(d, where + PCI_AGP_COMMAND);
388 format_agp_rate(t & 7, rate, agp3);
389 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
390 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
391 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
392 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
393 FLAG(t, PCI_AGP_COMMAND_SBA),
394 FLAG(t, PCI_AGP_COMMAND_AGP),
395 FLAG(t, PCI_AGP_COMMAND_GART64),
396 FLAG(t, PCI_AGP_COMMAND_64BIT),
397 FLAG(t, PCI_AGP_COMMAND_FW),
402 cap_pcix_nobridge(struct device *d, int where)
406 static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
408 printf("PCI-X non-bridge device\n");
413 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
416 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
417 status = get_conf_long(d, where + PCI_PCIX_STATUS);
418 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
419 FLAG(command, PCI_PCIX_COMMAND_DPERE),
420 FLAG(command, PCI_PCIX_COMMAND_ERO),
421 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
422 max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
423 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
424 ((status >> 8) & 0xff),
425 ((status >> 3) & 0x1f),
426 (status & PCI_PCIX_STATUS_FUNCTION),
427 FLAG(status, PCI_PCIX_STATUS_64BIT),
428 FLAG(status, PCI_PCIX_STATUS_133MHZ),
429 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
430 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
431 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
432 1 << (9 + ((status >> 21) & 3U)),
433 max_outstanding[(status >> 23) & 7U],
434 1 << (3 + ((status >> 26) & 7U)),
435 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
436 FLAG(status, PCI_PCIX_STATUS_266MHZ),
437 FLAG(status, PCI_PCIX_STATUS_533MHZ));
441 cap_pcix_bridge(struct device *d, int where)
443 static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
445 u32 status, upstcr, downstcr;
447 printf("PCI-X bridge device\n");
452 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
455 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
456 printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
457 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
458 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
459 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
460 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
461 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
462 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
463 sec_clock_freq[(secstatus >> 6) & 7]);
464 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
465 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
466 ((status >> 8) & 0xff),
467 ((status >> 3) & 0x1f),
468 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
469 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
470 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
471 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
472 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
473 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
474 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
475 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
476 printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
477 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
478 (upstcr >> 16) & 0xffff);
479 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
480 printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
481 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
482 (downstcr >> 16) & 0xffff);
486 cap_pcix(struct device *d, int where)
488 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
490 case PCI_HEADER_TYPE_NORMAL:
491 cap_pcix_nobridge(d, where);
493 case PCI_HEADER_TYPE_BRIDGE:
494 cap_pcix_bridge(d, where);
500 ht_link_width(unsigned width)
502 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
503 return widths[width];
507 ht_link_freq(unsigned freq)
509 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
510 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
515 cap_ht_pri(struct device *d, int where, int cmd)
517 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
518 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
521 printf("HyperTransport: Slave or Primary Interface\n");
525 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
527 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
528 if (rid < 0x23 && rid > 0x11)
529 printf("\t\t!!! Possibly incomplete decoding\n");
532 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
534 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
536 (cmd & PCI_HT_PRI_CMD_BUID),
537 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
538 FLAG(cmd, PCI_HT_PRI_CMD_MH),
539 FLAG(cmd, PCI_HT_PRI_CMD_DD),
540 FLAG(cmd, PCI_HT_PRI_CMD_DUL));
541 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
543 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
545 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
547 FLAG(lctr0, PCI_HT_LCTR_CFLE),
548 FLAG(lctr0, PCI_HT_LCTR_CST),
549 FLAG(lctr0, PCI_HT_LCTR_CFE),
550 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
551 FLAG(lctr0, PCI_HT_LCTR_INIT),
552 FLAG(lctr0, PCI_HT_LCTR_EOC),
553 FLAG(lctr0, PCI_HT_LCTR_TXO),
554 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
555 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
556 FLAG(lctr0, PCI_HT_LCTR_LSEN),
557 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
558 FLAG(lctr0, PCI_HT_LCTR_64B));
559 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
561 fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
563 fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
565 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
566 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
567 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
568 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
569 FLAG(lcnf0, PCI_HT_LCNF_DFI),
570 FLAG(lcnf0, PCI_HT_LCNF_DFO),
571 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
572 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
573 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
575 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
577 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
579 FLAG(lctr1, PCI_HT_LCTR_CFLE),
580 FLAG(lctr1, PCI_HT_LCTR_CST),
581 FLAG(lctr1, PCI_HT_LCTR_CFE),
582 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
583 FLAG(lctr1, PCI_HT_LCTR_INIT),
584 FLAG(lctr1, PCI_HT_LCTR_EOC),
585 FLAG(lctr1, PCI_HT_LCTR_TXO),
586 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
587 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
588 FLAG(lctr1, PCI_HT_LCTR_LSEN),
589 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
590 FLAG(lctr1, PCI_HT_LCTR_64B));
591 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
593 fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
595 fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
597 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
598 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
599 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
600 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
601 FLAG(lcnf1, PCI_HT_LCNF_DFI),
602 FLAG(lcnf1, PCI_HT_LCNF_DFO),
603 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
604 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
605 printf("\t\tRevision ID: %u.%02u\n",
606 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
609 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
610 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
611 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
612 FLAG(lfrer0, PCI_HT_LFRER_PROT),
613 FLAG(lfrer0, PCI_HT_LFRER_OV),
614 FLAG(lfrer0, PCI_HT_LFRER_EOC),
615 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
616 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
617 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
618 FLAG(lfcap0, PCI_HT_LFCAP_200),
619 FLAG(lfcap0, PCI_HT_LFCAP_300),
620 FLAG(lfcap0, PCI_HT_LFCAP_400),
621 FLAG(lfcap0, PCI_HT_LFCAP_500),
622 FLAG(lfcap0, PCI_HT_LFCAP_600),
623 FLAG(lfcap0, PCI_HT_LFCAP_800),
624 FLAG(lfcap0, PCI_HT_LFCAP_1000),
625 FLAG(lfcap0, PCI_HT_LFCAP_1200),
626 FLAG(lfcap0, PCI_HT_LFCAP_1400),
627 FLAG(lfcap0, PCI_HT_LFCAP_1600),
628 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
629 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
630 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
631 FLAG(ftr, PCI_HT_FTR_ISOCFC),
632 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
633 FLAG(ftr, PCI_HT_FTR_CRCTM),
634 FLAG(ftr, PCI_HT_FTR_ECTLT),
635 FLAG(ftr, PCI_HT_FTR_64BA),
636 FLAG(ftr, PCI_HT_FTR_UIDRD));
637 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
638 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
639 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
640 FLAG(lfrer1, PCI_HT_LFRER_PROT),
641 FLAG(lfrer1, PCI_HT_LFRER_OV),
642 FLAG(lfrer1, PCI_HT_LFRER_EOC),
643 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
644 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
645 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
646 FLAG(lfcap1, PCI_HT_LFCAP_200),
647 FLAG(lfcap1, PCI_HT_LFCAP_300),
648 FLAG(lfcap1, PCI_HT_LFCAP_400),
649 FLAG(lfcap1, PCI_HT_LFCAP_500),
650 FLAG(lfcap1, PCI_HT_LFCAP_600),
651 FLAG(lfcap1, PCI_HT_LFCAP_800),
652 FLAG(lfcap1, PCI_HT_LFCAP_1000),
653 FLAG(lfcap1, PCI_HT_LFCAP_1200),
654 FLAG(lfcap1, PCI_HT_LFCAP_1400),
655 FLAG(lfcap1, PCI_HT_LFCAP_1600),
656 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
657 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
658 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
659 FLAG(eh, PCI_HT_EH_PFLE),
660 FLAG(eh, PCI_HT_EH_OFLE),
661 FLAG(eh, PCI_HT_EH_PFE),
662 FLAG(eh, PCI_HT_EH_OFE),
663 FLAG(eh, PCI_HT_EH_EOCFE),
664 FLAG(eh, PCI_HT_EH_RFE),
665 FLAG(eh, PCI_HT_EH_CRCFE),
666 FLAG(eh, PCI_HT_EH_SERRFE),
667 FLAG(eh, PCI_HT_EH_CF),
668 FLAG(eh, PCI_HT_EH_RE),
669 FLAG(eh, PCI_HT_EH_PNFE),
670 FLAG(eh, PCI_HT_EH_ONFE),
671 FLAG(eh, PCI_HT_EH_EOCNFE),
672 FLAG(eh, PCI_HT_EH_RNFE),
673 FLAG(eh, PCI_HT_EH_CRCNFE),
674 FLAG(eh, PCI_HT_EH_SERRNFE));
675 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
676 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
677 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
678 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
679 printf("\t\tBus Number: %02x\n", bn);
683 cap_ht_sec(struct device *d, int where, int cmd)
685 u16 lctr, lcnf, ftr, eh;
686 u8 rid, lfrer, lfcap, mbu, mlu;
689 printf("HyperTransport: Host or Secondary Interface\n");
693 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
695 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
696 if (rid < 0x23 && rid > 0x11)
697 printf("\t\t!!! Possibly incomplete decoding\n");
700 fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
702 fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
704 FLAG(cmd, PCI_HT_SEC_CMD_WR),
705 FLAG(cmd, PCI_HT_SEC_CMD_DE),
706 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
707 FLAG(cmd, PCI_HT_SEC_CMD_CS),
708 FLAG(cmd, PCI_HT_SEC_CMD_HH),
709 FLAG(cmd, PCI_HT_SEC_CMD_AS),
710 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
711 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
712 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
714 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
716 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
718 FLAG(lctr, PCI_HT_LCTR_CFLE),
719 FLAG(lctr, PCI_HT_LCTR_CST),
720 FLAG(lctr, PCI_HT_LCTR_CFE),
721 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
722 FLAG(lctr, PCI_HT_LCTR_INIT),
723 FLAG(lctr, PCI_HT_LCTR_EOC),
724 FLAG(lctr, PCI_HT_LCTR_TXO),
725 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
726 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
727 FLAG(lctr, PCI_HT_LCTR_LSEN),
728 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
729 FLAG(lctr, PCI_HT_LCTR_64B));
730 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
732 fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
734 fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
736 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
737 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
738 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
739 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
740 FLAG(lcnf, PCI_HT_LCNF_DFI),
741 FLAG(lcnf, PCI_HT_LCNF_DFO),
742 FLAG(lcnf, PCI_HT_LCNF_DFIE),
743 FLAG(lcnf, PCI_HT_LCNF_DFOE));
744 printf("\t\tRevision ID: %u.%02u\n",
745 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
748 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
749 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
750 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
751 FLAG(lfrer, PCI_HT_LFRER_PROT),
752 FLAG(lfrer, PCI_HT_LFRER_OV),
753 FLAG(lfrer, PCI_HT_LFRER_EOC),
754 FLAG(lfrer, PCI_HT_LFRER_CTLT));
755 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
756 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
757 FLAG(lfcap, PCI_HT_LFCAP_200),
758 FLAG(lfcap, PCI_HT_LFCAP_300),
759 FLAG(lfcap, PCI_HT_LFCAP_400),
760 FLAG(lfcap, PCI_HT_LFCAP_500),
761 FLAG(lfcap, PCI_HT_LFCAP_600),
762 FLAG(lfcap, PCI_HT_LFCAP_800),
763 FLAG(lfcap, PCI_HT_LFCAP_1000),
764 FLAG(lfcap, PCI_HT_LFCAP_1200),
765 FLAG(lfcap, PCI_HT_LFCAP_1400),
766 FLAG(lfcap, PCI_HT_LFCAP_1600),
767 FLAG(lfcap, PCI_HT_LFCAP_VEND));
768 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
769 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
770 FLAG(ftr, PCI_HT_FTR_ISOCFC),
771 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
772 FLAG(ftr, PCI_HT_FTR_CRCTM),
773 FLAG(ftr, PCI_HT_FTR_ECTLT),
774 FLAG(ftr, PCI_HT_FTR_64BA),
775 FLAG(ftr, PCI_HT_FTR_UIDRD),
776 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
777 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
778 if (ftr & PCI_HT_SEC_FTR_EXTRS)
780 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
781 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
782 FLAG(eh, PCI_HT_EH_PFLE),
783 FLAG(eh, PCI_HT_EH_OFLE),
784 FLAG(eh, PCI_HT_EH_PFE),
785 FLAG(eh, PCI_HT_EH_OFE),
786 FLAG(eh, PCI_HT_EH_EOCFE),
787 FLAG(eh, PCI_HT_EH_RFE),
788 FLAG(eh, PCI_HT_EH_CRCFE),
789 FLAG(eh, PCI_HT_EH_SERRFE),
790 FLAG(eh, PCI_HT_EH_CF),
791 FLAG(eh, PCI_HT_EH_RE),
792 FLAG(eh, PCI_HT_EH_PNFE),
793 FLAG(eh, PCI_HT_EH_ONFE),
794 FLAG(eh, PCI_HT_EH_EOCNFE),
795 FLAG(eh, PCI_HT_EH_RNFE),
796 FLAG(eh, PCI_HT_EH_CRCNFE),
797 FLAG(eh, PCI_HT_EH_SERRNFE));
798 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
799 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
800 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
805 cap_ht(struct device *d, int where, int cmd)
809 switch (cmd & PCI_HT_CMD_TYP_HI)
811 case PCI_HT_CMD_TYP_HI_PRI:
812 cap_ht_pri(d, where, cmd);
814 case PCI_HT_CMD_TYP_HI_SEC:
815 cap_ht_sec(d, where, cmd);
819 type = cmd & PCI_HT_CMD_TYP;
822 case PCI_HT_CMD_TYP_SW:
823 printf("HyperTransport: Switch\n");
825 case PCI_HT_CMD_TYP_IDC:
826 printf("HyperTransport: Interrupt Discovery and Configuration\n");
828 case PCI_HT_CMD_TYP_RID:
829 printf("HyperTransport: Revision ID: %u.%02u\n",
830 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
832 case PCI_HT_CMD_TYP_UIDC:
833 printf("HyperTransport: UnitID Clumping\n");
835 case PCI_HT_CMD_TYP_ECSA:
836 printf("HyperTransport: Extended Configuration Space Access\n");
838 case PCI_HT_CMD_TYP_AM:
839 printf("HyperTransport: Address Mapping\n");
841 case PCI_HT_CMD_TYP_MSIM:
842 printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
843 FLAG(cmd, PCI_HT_MSIM_CMD_EN),
844 FLAG(cmd, PCI_HT_MSIM_CMD_FIXD));
845 if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD))
848 if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8))
850 offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
851 offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
852 printf("\t\tMapping Address Base: %016llx\n", ((unsigned long long)offh << 32) | (offl & ~0xfffff));
855 case PCI_HT_CMD_TYP_DR:
856 printf("HyperTransport: DirectRoute\n");
858 case PCI_HT_CMD_TYP_VCS:
859 printf("HyperTransport: VCSet\n");
861 case PCI_HT_CMD_TYP_RM:
862 printf("HyperTransport: Retry Mode\n");
864 case PCI_HT_CMD_TYP_X86:
865 printf("HyperTransport: X86 (reserved)\n");
868 printf("HyperTransport: #%02x\n", type >> 11);
873 cap_msi(struct device *d, int where, int cap)
879 printf("Message Signalled Interrupts: Mask%c 64bit%c Queue=%d/%d Enable%c\n",
880 FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
881 FLAG(cap, PCI_MSI_FLAGS_64BIT),
882 (cap & PCI_MSI_FLAGS_QSIZE) >> 4,
883 (cap & PCI_MSI_FLAGS_QMASK) >> 1,
884 FLAG(cap, PCI_MSI_FLAGS_ENABLE));
887 is64 = cap & PCI_MSI_FLAGS_64BIT;
888 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
890 printf("\t\tAddress: ");
893 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
894 w = get_conf_word(d, where + PCI_MSI_DATA_64);
898 w = get_conf_word(d, where + PCI_MSI_DATA_32);
899 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
900 printf("%08x Data: %04x\n", t, w);
901 if (cap & PCI_MSI_FLAGS_MASK_BIT)
907 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
909 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
910 pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
914 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
916 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
917 pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
919 printf("\t\tMasking: %08x Pending: %08x\n", mask, pending);
923 static float power_limit(int value, int scale)
925 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
926 return value * scales[scale];
929 static const char *latency_l0s(int value)
931 static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
932 return latencies[value];
935 static const char *latency_l1(int value)
937 static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
938 return latencies[value];
941 static void cap_express_dev(struct device *d, int where, int type)
946 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
947 printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d, Latency L0s %s, L1 %s\n",
948 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
949 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
950 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
951 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
952 printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
953 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
954 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
955 printf(" AttnBtn%c AttnInd%c PwrInd%c",
956 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
957 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
958 printf(" RBE%c FLReset%c",
959 FLAG(t, PCI_EXP_DEVCAP_RBE),
960 FLAG(t, PCI_EXP_DEVCAP_FLRESET));
961 if (type == PCI_EXP_TYPE_UPSTREAM)
962 printf("SlotPowerLimit %fW",
963 power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
964 (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
967 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
968 printf("\t\tDevCtl:\tReport errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
969 FLAG(w, PCI_EXP_DEVCTL_CERE),
970 FLAG(w, PCI_EXP_DEVCTL_NFERE),
971 FLAG(w, PCI_EXP_DEVCTL_FERE),
972 FLAG(w, PCI_EXP_DEVCTL_URRE));
973 printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
974 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
975 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
976 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
977 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
978 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
979 if (type == PCI_EXP_TYPE_PCI_BRIDGE || type == PCI_EXP_TYPE_PCIE_BRIDGE)
980 printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
981 if (type == PCI_EXP_TYPE_ENDPOINT && (t & PCI_EXP_DEVCAP_FLRESET))
982 printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
983 printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
984 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
985 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
987 w = get_conf_word(d, where + PCI_EXP_DEVSTA);
988 printf("\t\tDevSta:\tCorrErr%c UncorrErr%c FatalErr%c UnsuppReq%c AuxPwr%c TransPend%c\n",
989 FLAG(w, PCI_EXP_DEVSTA_CED),
990 FLAG(w, PCI_EXP_DEVSTA_NFED),
991 FLAG(w, PCI_EXP_DEVSTA_FED),
992 FLAG(w, PCI_EXP_DEVSTA_URD),
993 FLAG(w, PCI_EXP_DEVSTA_AUXPD),
994 FLAG(w, PCI_EXP_DEVSTA_TRPND));
996 /* FIXME: Second set of control/status registers is not supported yet. */
999 static char *link_speed(int speed)
1012 static char *aspm_support(int code)
1025 static const char *aspm_enabled(int code)
1027 static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
1031 static void cap_express_link(struct device *d, int where, int type)
1036 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
1037 printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s, Latency L0 %s, L1 %s\n",
1039 link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
1040 aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
1041 latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
1042 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
1043 printf("\t\t\tClockPM%c Suprise%c LLActRep%c BwNot%c\n",
1044 FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
1045 FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
1046 FLAG(t, PCI_EXP_LNKCAP_DLLA),
1047 FLAG(t, PCI_EXP_LNKCAP_LBNC));
1049 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
1050 printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
1051 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
1052 (type == PCI_EXP_TYPE_LEG_END))
1053 printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
1054 printf(" Disabled%c Retrain%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
1055 FLAG(w, PCI_EXP_LNKCTL_DISABLE),
1056 FLAG(w, PCI_EXP_LNKCTL_RETRAIN),
1057 FLAG(w, PCI_EXP_LNKCTL_CLOCK),
1058 FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
1059 FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
1060 FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
1061 FLAG(w, PCI_EXP_LNKCTL_BWMIE),
1062 FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
1064 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
1065 printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
1066 link_speed(w & PCI_EXP_LNKSTA_SPEED),
1067 (w & PCI_EXP_LNKSTA_WIDTH) >> 4,
1068 FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
1069 FLAG(w, PCI_EXP_LNKSTA_TRAIN),
1070 FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
1071 FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
1072 FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
1073 FLAG(w, PCI_EXP_LNKSTA_AUTBW));
1076 static const char *indicator(int code)
1078 static const char *names[] = { "Unknown", "On", "Blink", "Off" };
1082 static void cap_express_slot(struct device *d, int where)
1087 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
1088 printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surpise%c\n",
1089 FLAG(t, PCI_EXP_SLTCAP_ATNB),
1090 FLAG(t, PCI_EXP_SLTCAP_PWRC),
1091 FLAG(t, PCI_EXP_SLTCAP_MRL),
1092 FLAG(t, PCI_EXP_SLTCAP_ATNI),
1093 FLAG(t, PCI_EXP_SLTCAP_PWRI),
1094 FLAG(t, PCI_EXP_SLTCAP_HPC),
1095 FLAG(t, PCI_EXP_SLTCAP_HPS));
1096 printf("\t\t\tSlot #%3x, PowerLimit %f; Interlock%c NoCompl%c\n",
1098 power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
1099 FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
1100 FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
1102 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
1103 printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
1104 FLAG(w, PCI_EXP_SLTCTL_ATNB),
1105 FLAG(w, PCI_EXP_SLTCTL_PWRF),
1106 FLAG(w, PCI_EXP_SLTCTL_MRLS),
1107 FLAG(w, PCI_EXP_SLTCTL_PRSD),
1108 FLAG(w, PCI_EXP_SLTCTL_CMDC),
1109 FLAG(w, PCI_EXP_SLTCTL_HPIE),
1110 FLAG(w, PCI_EXP_SLTCTL_LLCHG));
1111 printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
1112 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
1113 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
1114 FLAG(w, PCI_EXP_SLTCTL_PWRC),
1115 FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
1117 w = get_conf_word(d, where + PCI_EXP_SLTSTA);
1118 printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
1119 FLAG(w, PCI_EXP_SLTSTA_ATNB),
1120 FLAG(w, PCI_EXP_SLTSTA_PWRF),
1121 FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
1122 FLAG(w, PCI_EXP_SLTSTA_CMDC),
1123 FLAG(w, PCI_EXP_SLTSTA_PRES),
1124 FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
1125 printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
1126 FLAG(w, PCI_EXP_SLTSTA_MRLS),
1127 FLAG(w, PCI_EXP_SLTSTA_PRSD),
1128 FLAG(w, PCI_EXP_SLTSTA_LLCHG));
1131 static void cap_express_root(struct device *d, int where)
1133 u32 w = get_conf_word(d, where + PCI_EXP_RTCTL);
1134 printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
1135 FLAG(w, PCI_EXP_RTCTL_SECEE),
1136 FLAG(w, PCI_EXP_RTCTL_SENFEE),
1137 FLAG(w, PCI_EXP_RTCTL_SEFEE),
1138 FLAG(w, PCI_EXP_RTCTL_PMEIE),
1139 FLAG(w, PCI_EXP_RTCTL_CRSVIS));
1141 w = get_conf_word(d, where + PCI_EXP_RTCAP);
1142 printf("\t\tRootCap: CRSVisible%c\n",
1143 FLAG(w, PCI_EXP_RTCAP_CRSVIS));
1145 w = get_conf_word(d, where + PCI_EXP_RTSTA);
1146 printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
1147 w & PCI_EXP_RTSTA_PME_REQID,
1148 FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
1149 FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
1153 cap_express(struct device *d, int where, int cap)
1155 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1161 printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
1164 case PCI_EXP_TYPE_ENDPOINT:
1167 case PCI_EXP_TYPE_LEG_END:
1168 printf("Legacy Endpoint");
1170 case PCI_EXP_TYPE_ROOT_PORT:
1171 slot = cap & PCI_EXP_FLAGS_SLOT;
1172 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1174 case PCI_EXP_TYPE_UPSTREAM:
1175 printf("Upstream Port");
1177 case PCI_EXP_TYPE_DOWNSTREAM:
1178 slot = cap & PCI_EXP_FLAGS_SLOT;
1179 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1181 case PCI_EXP_TYPE_PCI_BRIDGE:
1182 printf("PCI/PCI-X Bridge");
1184 case PCI_EXP_TYPE_PCIE_BRIDGE:
1185 printf("PCI/PCI-X to PCI-Express Bridge");
1187 case PCI_EXP_TYPE_ROOT_INT_EP:
1188 printf("Root Complex Integrated Endpoint");
1190 case PCI_EXP_TYPE_ROOT_EC:
1191 printf("Root Complex Event Collector");
1194 printf("Unknown type %d", type);
1196 printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1203 if (type == PCI_EXP_TYPE_ROOT_PORT)
1205 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1208 cap_express_dev(d, where, type);
1209 cap_express_link(d, where, type);
1211 cap_express_slot(d, where);
1212 if (type == PCI_EXP_TYPE_ROOT_PORT)
1213 cap_express_root(d, where);
1217 cap_msix(struct device *d, int where, int cap)
1221 printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
1222 FLAG(cap, PCI_MSIX_ENABLE),
1223 FLAG(cap, PCI_MSIX_MASK),
1224 (cap & PCI_MSIX_TABSIZE) + 1);
1225 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1228 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1229 printf("\t\tVector table: BAR=%d offset=%08x\n",
1230 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1231 off = get_conf_long(d, where + PCI_MSIX_PBA);
1232 printf("\t\tPBA: BAR=%d offset=%08x\n",
1233 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1239 int esr = cap & 0xff;
1242 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1243 esr & PCI_SID_ESR_NSLOTS,
1244 FLAG(esr, PCI_SID_ESR_FIC),
1249 cap_ssvid(struct device *d, int where)
1251 u16 subsys_v, subsys_d;
1252 char ssnamebuf[256];
1254 if (!config_fetch(d, where, 8))
1256 subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR);
1257 subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE);
1258 printf("Subsystem: %s\n",
1259 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1260 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1261 d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
1265 cap_dsn(struct device *d, int where)
1268 if (!config_fetch(d, where + 4, 8))
1270 t1 = get_conf_long(d, where + 4);
1271 t2 = get_conf_long(d, where + 8);
1272 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
1273 t1 & 0xff, (t1 >> 8) & 0xff, (t1 >> 16) & 0xff, t1 >> 24,
1274 t2 & 0xff, (t2 >> 8) & 0xff, (t2 >> 16) & 0xff, t2 >> 24);
1278 cap_debug_port(int cap)
1280 int bar = cap >> 13;
1281 int pos = cap & 0x1fff;
1282 printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
1286 show_ext_caps(struct device *d)
1289 char been_there[0x1000];
1290 memset(been_there, 0, 0x1000);
1296 if (!config_fetch(d, where, 4))
1298 header = get_conf_long(d, where);
1301 id = header & 0xffff;
1302 printf("\tCapabilities: [%03x] ", where);
1303 if (been_there[where]++)
1305 printf("<chain looped>\n");
1310 case PCI_EXT_CAP_ID_AER:
1311 printf("Advanced Error Reporting <?>\n");
1313 case PCI_EXT_CAP_ID_VC:
1314 printf("Virtual Channel <?>\n");
1316 case PCI_EXT_CAP_ID_DSN:
1319 case PCI_EXT_CAP_ID_PB:
1320 printf("Power Budgeting <?>\n");
1322 case PCI_EXT_CAP_ID_RCLINK:
1323 printf("Root Complex Link <?>\n");
1325 case PCI_EXT_CAP_ID_RCILINK:
1326 printf("Root Complex Internal Link <?>\n");
1328 case PCI_EXT_CAP_ID_RCECOLL:
1329 printf("Root Complex Event Collector <?>\n");
1331 case PCI_EXT_CAP_ID_MFVC:
1332 printf("Multi-Function Virtual Channel <?>\n");
1334 case PCI_EXT_CAP_ID_RBCB:
1335 printf("Root Bridge Control Block <?>\n");
1337 case PCI_EXT_CAP_ID_VNDR:
1338 printf("Vendor Specific Information <?>\n");
1340 case PCI_EXT_CAP_ID_ACS:
1341 printf("Access Controls <?>\n");
1344 printf("#%02x\n", id);
1347 where = header >> 20;
1352 show_caps(struct device *d)
1354 int can_have_ext_caps = 0;
1356 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1358 int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
1359 byte been_there[256];
1360 memset(been_there, 0, 256);
1364 printf("\tCapabilities: ");
1365 if (!config_fetch(d, where, 4))
1367 puts("<access denied>");
1370 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1371 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1372 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1373 printf("[%02x] ", where);
1374 if (been_there[where]++)
1376 printf("<chain looped>\n");
1381 printf("<chain broken>\n");
1387 cap_pm(d, where, cap);
1389 case PCI_CAP_ID_AGP:
1390 cap_agp(d, where, cap);
1392 case PCI_CAP_ID_VPD:
1393 printf("Vital Product Data <?>\n");
1395 case PCI_CAP_ID_SLOTID:
1398 case PCI_CAP_ID_MSI:
1399 cap_msi(d, where, cap);
1401 case PCI_CAP_ID_CHSWP:
1402 printf("CompactPCI hot-swap <?>\n");
1404 case PCI_CAP_ID_PCIX:
1406 can_have_ext_caps = 1;
1409 cap_ht(d, where, cap);
1411 case PCI_CAP_ID_VNDR:
1412 printf("Vendor Specific Information <?>\n");
1414 case PCI_CAP_ID_DBG:
1415 cap_debug_port(cap);
1417 case PCI_CAP_ID_CCRC:
1418 printf("CompactPCI central resource control <?>\n");
1420 case PCI_CAP_ID_HOTPLUG:
1421 printf("Hot-plug capable\n");
1423 case PCI_CAP_ID_SSVID:
1424 cap_ssvid(d, where);
1426 case PCI_CAP_ID_AGP3:
1427 printf("AGP3 <?>\n");
1429 case PCI_CAP_ID_SECURE:
1430 printf("Secure device <?>\n");
1432 case PCI_CAP_ID_EXP:
1433 cap_express(d, where, cap);
1434 can_have_ext_caps = 1;
1436 case PCI_CAP_ID_MSIX:
1437 cap_msix(d, where, cap);
1439 case PCI_CAP_ID_SATA:
1440 printf("SATA HBA <?>\n");
1443 printf("PCIe advanced features <?>\n");
1446 printf("#%02x [%04x]\n", id, cap);
1451 if (can_have_ext_caps)
1455 /*** Verbose output ***/
1458 show_size(pciaddr_t x)
1464 printf("%d", (int) x);
1465 else if (x < 1048576)
1466 printf("%dK", (int)(x / 1024));
1467 else if (x < 0x80000000)
1468 printf("%dM", (int)(x / 1048576));
1470 printf(PCIADDR_T_FMT, x);
1475 show_bases(struct device *d, int cnt)
1477 struct pci_dev *p = d->dev;
1478 word cmd = get_conf_word(d, PCI_COMMAND);
1481 for(i=0; i<cnt; i++)
1483 pciaddr_t pos = p->base_addr[i];
1484 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
1485 u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
1486 if (flg == 0xffffffff)
1488 if (!pos && !flg && !len)
1491 printf("\tRegion %d: ", i);
1494 if (pos && !flg) /* Reported by the OS, but not by the device */
1496 printf("[virtual] ");
1499 if (flg & PCI_BASE_ADDRESS_SPACE_IO)
1501 pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
1502 printf("I/O ports at ");
1504 printf(PCIADDR_PORT_FMT, a);
1505 else if (flg & PCI_BASE_ADDRESS_IO_MASK)
1506 printf("<ignored>");
1508 printf("<unassigned>");
1509 if (!(cmd & PCI_COMMAND_IO))
1510 printf(" [disabled]");
1514 int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
1515 pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
1519 printf("Memory at ");
1520 if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
1524 printf("<invalid-64bit-slot>");
1530 z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
1533 u32 y = a & 0xffffffff;
1535 printf("%08x%08x", z, y);
1537 printf("<unassigned>");
1545 printf(PCIADDR_T_FMT, a);
1547 printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
1549 printf(" (%s, %sprefetchable)",
1550 (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
1551 (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
1552 (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
1553 (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
1554 if (!(cmd & PCI_COMMAND_MEMORY))
1555 printf(" [disabled]");
1563 show_rom(struct device *d, int reg)
1565 struct pci_dev *p = d->dev;
1566 pciaddr_t rom = p->rom_base_addr;
1567 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
1568 u32 flg = get_conf_long(d, reg);
1569 word cmd = get_conf_word(d, PCI_COMMAND);
1571 if (!rom && !flg && !len)
1574 if ((rom & PCI_ROM_ADDRESS_MASK) && !(flg & PCI_ROM_ADDRESS_MASK))
1576 printf("[virtual] ");
1579 printf("Expansion ROM at ");
1580 if (rom & PCI_ROM_ADDRESS_MASK)
1581 printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
1582 else if (flg & PCI_ROM_ADDRESS_MASK)
1583 printf("<ignored>");
1585 printf("<unassigned>");
1586 if (!(flg & PCI_ROM_ADDRESS_ENABLE))
1587 printf(" [disabled]");
1588 else if (!(cmd & PCI_COMMAND_MEMORY))
1589 printf(" [disabled by cmd]");
1595 show_htype0(struct device *d)
1598 show_rom(d, PCI_ROM_ADDRESS);
1603 show_htype1(struct device *d)
1605 u32 io_base = get_conf_byte(d, PCI_IO_BASE);
1606 u32 io_limit = get_conf_byte(d, PCI_IO_LIMIT);
1607 u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
1608 u32 mem_base = get_conf_word(d, PCI_MEMORY_BASE);
1609 u32 mem_limit = get_conf_word(d, PCI_MEMORY_LIMIT);
1610 u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
1611 u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE);
1612 u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT);
1613 u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
1614 word sec_stat = get_conf_word(d, PCI_SEC_STATUS);
1615 word brc = get_conf_word(d, PCI_BRIDGE_CONTROL);
1616 int verb = verbose > 2;
1619 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1620 get_conf_byte(d, PCI_PRIMARY_BUS),
1621 get_conf_byte(d, PCI_SECONDARY_BUS),
1622 get_conf_byte(d, PCI_SUBORDINATE_BUS),
1623 get_conf_byte(d, PCI_SEC_LATENCY_TIMER));
1625 if (io_type != (io_limit & PCI_IO_RANGE_TYPE_MASK) ||
1626 (io_type != PCI_IO_RANGE_TYPE_16 && io_type != PCI_IO_RANGE_TYPE_32))
1627 printf("\t!!! Unknown I/O range types %x/%x\n", io_base, io_limit);
1630 io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
1631 io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
1632 if (io_type == PCI_IO_RANGE_TYPE_32)
1634 io_base |= (get_conf_word(d, PCI_IO_BASE_UPPER16) << 16);
1635 io_limit |= (get_conf_word(d, PCI_IO_LIMIT_UPPER16) << 16);
1637 if (io_base <= io_limit || verb)
1638 printf("\tI/O behind bridge: %08x-%08x\n", io_base, io_limit+0xfff);
1641 if (mem_type != (mem_limit & PCI_MEMORY_RANGE_TYPE_MASK) ||
1643 printf("\t!!! Unknown memory range types %x/%x\n", mem_base, mem_limit);
1646 mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
1647 mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
1648 if (mem_base <= mem_limit || verb)
1649 printf("\tMemory behind bridge: %08x-%08x\n", mem_base, mem_limit + 0xfffff);
1652 if (pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
1653 (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64))
1654 printf("\t!!! Unknown prefetchable memory range types %x/%x\n", pref_base, pref_limit);
1657 pref_base = (pref_base & PCI_PREF_RANGE_MASK) << 16;
1658 pref_limit = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
1659 if (pref_base <= pref_limit || verb)
1661 if (pref_type == PCI_PREF_RANGE_TYPE_32)
1662 printf("\tPrefetchable memory behind bridge: %08x-%08x\n", pref_base, pref_limit + 0xfffff);
1664 printf("\tPrefetchable memory behind bridge: %08x%08x-%08x%08x\n",
1665 get_conf_long(d, PCI_PREF_BASE_UPPER32),
1667 get_conf_long(d, PCI_PREF_LIMIT_UPPER32),
1668 pref_limit + 0xfffff);
1673 printf("\tSecondary status: 66MHz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c\n",
1674 FLAG(sec_stat, PCI_STATUS_66MHZ),
1675 FLAG(sec_stat, PCI_STATUS_FAST_BACK),
1676 FLAG(sec_stat, PCI_STATUS_PARITY),
1677 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1678 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1679 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1680 FLAG(sec_stat, PCI_STATUS_SIG_TARGET_ABORT),
1681 FLAG(sec_stat, PCI_STATUS_REC_TARGET_ABORT),
1682 FLAG(sec_stat, PCI_STATUS_REC_MASTER_ABORT),
1683 FLAG(sec_stat, PCI_STATUS_SIG_SYSTEM_ERROR),
1684 FLAG(sec_stat, PCI_STATUS_DETECTED_PARITY));
1686 show_rom(d, PCI_ROM_ADDRESS1);
1690 printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
1691 FLAG(brc, PCI_BRIDGE_CTL_PARITY),
1692 FLAG(brc, PCI_BRIDGE_CTL_SERR),
1693 FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
1694 FLAG(brc, PCI_BRIDGE_CTL_VGA),
1695 FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
1696 FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
1697 FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
1698 printf("\t\tPriDiscTmr%c SecDiscTmr%c DiscTmrStat%c DiscTmrSERREn%c\n",
1699 FLAG(brc, PCI_BRIDGE_CTL_PRI_DISCARD_TIMER),
1700 FLAG(brc, PCI_BRIDGE_CTL_SEC_DISCARD_TIMER),
1701 FLAG(brc, PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS),
1702 FLAG(brc, PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN));
1709 show_htype2(struct device *d)
1712 word cmd = get_conf_word(d, PCI_COMMAND);
1713 word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
1715 int verb = verbose > 2;
1718 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1719 get_conf_byte(d, PCI_CB_PRIMARY_BUS),
1720 get_conf_byte(d, PCI_CB_CARD_BUS),
1721 get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
1722 get_conf_byte(d, PCI_CB_LATENCY_TIMER));
1726 u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
1727 u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
1728 if (limit > base || verb)
1729 printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
1730 (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
1731 (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
1736 u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
1737 u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
1738 if (!(base & PCI_IO_RANGE_TYPE_32))
1743 base &= PCI_CB_IO_RANGE_MASK;
1744 limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
1745 if (base <= limit || verb)
1746 printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
1747 (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
1750 if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
1751 printf("\tSecondary status: SERR\n");
1753 printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
1754 FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
1755 FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
1756 FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
1757 FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
1758 FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
1759 FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
1760 FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
1761 FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
1763 if (d->config_cached < 128)
1765 printf("\t<access denied to the rest>\n");
1769 exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
1771 printf("\t16-bit legacy interface ports at %04x\n", exca);
1775 show_verbose(struct device *d)
1777 struct pci_dev *p = d->dev;
1778 word status = get_conf_word(d, PCI_STATUS);
1779 word cmd = get_conf_word(d, PCI_COMMAND);
1780 word class = p->device_class;
1781 byte bist = get_conf_byte(d, PCI_BIST);
1782 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1783 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
1784 byte cache_line = get_conf_byte(d, PCI_CACHE_LINE_SIZE);
1785 byte max_lat, min_gnt;
1786 byte int_pin = get_conf_byte(d, PCI_INTERRUPT_PIN);
1787 unsigned int irq = p->irq;
1788 word subsys_v = 0, subsys_d = 0;
1789 char ssnamebuf[256];
1795 case PCI_HEADER_TYPE_NORMAL:
1796 if (class == PCI_CLASS_BRIDGE_PCI)
1797 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1798 max_lat = get_conf_byte(d, PCI_MAX_LAT);
1799 min_gnt = get_conf_byte(d, PCI_MIN_GNT);
1800 subsys_v = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1801 subsys_d = get_conf_word(d, PCI_SUBSYSTEM_ID);
1803 case PCI_HEADER_TYPE_BRIDGE:
1804 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1805 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1806 irq = int_pin = min_gnt = max_lat = 0;
1808 case PCI_HEADER_TYPE_CARDBUS:
1809 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1810 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1811 min_gnt = max_lat = 0;
1812 if (d->config_cached >= 128)
1814 subsys_v = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1815 subsys_d = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1819 printf("\t!!! Unknown header type %02x\n", htype);
1823 if (subsys_v && subsys_v != 0xffff)
1824 printf("\tSubsystem: %s\n",
1825 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1826 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1827 p->vendor_id, p->device_id, subsys_v, subsys_d));
1831 printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c DisINTx%c\n",
1832 FLAG(cmd, PCI_COMMAND_IO),
1833 FLAG(cmd, PCI_COMMAND_MEMORY),
1834 FLAG(cmd, PCI_COMMAND_MASTER),
1835 FLAG(cmd, PCI_COMMAND_SPECIAL),
1836 FLAG(cmd, PCI_COMMAND_INVALIDATE),
1837 FLAG(cmd, PCI_COMMAND_VGA_PALETTE),
1838 FLAG(cmd, PCI_COMMAND_PARITY),
1839 FLAG(cmd, PCI_COMMAND_WAIT),
1840 FLAG(cmd, PCI_COMMAND_SERR),
1841 FLAG(cmd, PCI_COMMAND_FAST_BACK),
1842 FLAG(cmd, PCI_COMMAND_DISABLE_INTx));
1843 printf("\tStatus: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c INTx%c\n",
1844 FLAG(status, PCI_STATUS_CAP_LIST),
1845 FLAG(status, PCI_STATUS_66MHZ),
1846 FLAG(status, PCI_STATUS_UDF),
1847 FLAG(status, PCI_STATUS_FAST_BACK),
1848 FLAG(status, PCI_STATUS_PARITY),
1849 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1850 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1851 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1852 FLAG(status, PCI_STATUS_SIG_TARGET_ABORT),
1853 FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
1854 FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
1855 FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
1856 FLAG(status, PCI_STATUS_DETECTED_PARITY),
1857 FLAG(status, PCI_STATUS_INTx));
1858 if (cmd & PCI_COMMAND_MASTER)
1860 printf("\tLatency: %d", latency);
1861 if (min_gnt || max_lat)
1865 printf("%dns min", min_gnt*250);
1866 if (min_gnt && max_lat)
1869 printf("%dns max", max_lat*250);
1873 printf(", Cache Line Size: %d bytes", cache_line * 4);
1877 printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n",
1878 (int_pin ? 'A' + int_pin - 1 : '?'), irq);
1882 printf("\tFlags: ");
1883 if (cmd & PCI_COMMAND_MASTER)
1884 printf("bus master, ");
1885 if (cmd & PCI_COMMAND_VGA_PALETTE)
1886 printf("VGA palette snoop, ");
1887 if (cmd & PCI_COMMAND_WAIT)
1888 printf("stepping, ");
1889 if (cmd & PCI_COMMAND_FAST_BACK)
1890 printf("fast Back2Back, ");
1891 if (status & PCI_STATUS_66MHZ)
1893 if (status & PCI_STATUS_UDF)
1894 printf("user-definable features, ");
1896 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1897 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1898 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??");
1899 if (cmd & PCI_COMMAND_MASTER)
1900 printf(", latency %d", latency);
1902 printf(", IRQ " PCIIRQ_FMT, irq);
1906 if (bist & PCI_BIST_CAPABLE)
1908 if (bist & PCI_BIST_START)
1909 printf("\tBIST is running\n");
1911 printf("\tBIST result: %02x\n", bist & PCI_BIST_CODE_MASK);
1916 case PCI_HEADER_TYPE_NORMAL:
1919 case PCI_HEADER_TYPE_BRIDGE:
1922 case PCI_HEADER_TYPE_CARDBUS:
1928 /*** Machine-readable dumps ***/
1931 show_hex_dump(struct device *d)
1933 unsigned int i, cnt;
1935 cnt = d->config_cached;
1936 if (opt_hex >= 3 && config_fetch(d, cnt, 256-cnt))
1939 if (opt_hex >= 4 && config_fetch(d, 256, 4096-256))
1943 for(i=0; i<cnt; i++)
1947 printf(" %02x", get_conf_byte(d, i));
1954 print_shell_escaped(char *c)
1959 if (*c == '"' || *c == '\\')
1967 show_machine(struct device *d)
1969 struct pci_dev *p = d->dev;
1971 word sv_id=0, sd_id=0;
1972 char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
1974 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
1976 case PCI_HEADER_TYPE_NORMAL:
1977 sv_id = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1978 sd_id = get_conf_word(d, PCI_SUBSYSTEM_ID);
1980 case PCI_HEADER_TYPE_CARDBUS:
1981 if (d->config_cached >= 128)
1983 sv_id = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1984 sd_id = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1991 printf((opt_machine >= 2) ? "Slot:\t" : "Device:\t");
1994 printf("Class:\t%s\n",
1995 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
1996 printf("Vendor:\t%s\n",
1997 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
1998 printf("Device:\t%s\n",
1999 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
2000 if (sv_id && sv_id != 0xffff)
2002 printf("SVendor:\t%s\n",
2003 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
2004 printf("SDevice:\t%s\n",
2005 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
2007 if (c = get_conf_byte(d, PCI_REVISION_ID))
2008 printf("Rev:\t%02x\n", c);
2009 if (c = get_conf_byte(d, PCI_CLASS_PROG))
2010 printf("ProgIf:\t%02x\n", c);
2015 print_shell_escaped(pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
2016 print_shell_escaped(pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
2017 print_shell_escaped(pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
2018 if (c = get_conf_byte(d, PCI_REVISION_ID))
2019 printf(" -r%02x", c);
2020 if (c = get_conf_byte(d, PCI_CLASS_PROG))
2021 printf(" -p%02x", c);
2022 if (sv_id && sv_id != 0xffff)
2024 print_shell_escaped(pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
2025 print_shell_escaped(pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
2028 printf(" \"\" \"\"");
2033 /*** Main show function ***/
2036 show_device(struct device *d)
2046 if (verbose || opt_hex)
2055 for(d=first_dev; d; d=d->next)
2059 /*** Tree output ***/
2062 struct bridge *chain; /* Single-linked list of bridges */
2063 struct bridge *next, *child; /* Tree of bridges */
2064 struct bus *first_bus; /* List of buses connected to this bridge */
2065 unsigned int domain;
2066 unsigned int primary, secondary, subordinate; /* Bus numbers */
2067 struct device *br_dev;
2071 unsigned int domain;
2072 unsigned int number;
2073 struct bus *sibling;
2074 struct device *first_dev, **last_dev;
2077 static struct bridge host_bridge = { NULL, NULL, NULL, NULL, 0, ~0, 0, ~0, NULL };
2080 find_bus(struct bridge *b, unsigned int domain, unsigned int n)
2084 for(bus=b->first_bus; bus; bus=bus->sibling)
2085 if (bus->domain == domain && bus->number == n)
2091 new_bus(struct bridge *b, unsigned int domain, unsigned int n)
2093 struct bus *bus = xmalloc(sizeof(struct bus));
2094 bus->domain = domain;
2096 bus->sibling = b->first_bus;
2097 bus->first_dev = NULL;
2098 bus->last_dev = &bus->first_dev;
2104 insert_dev(struct device *d, struct bridge *b)
2106 struct pci_dev *p = d->dev;
2109 if (! (bus = find_bus(b, p->domain, p->bus)))
2112 for(c=b->child; c; c=c->next)
2113 if (c->domain == p->domain && c->secondary <= p->bus && p->bus <= c->subordinate)
2118 bus = new_bus(b, p->domain, p->bus);
2120 /* Simple insertion at the end _does_ guarantee the correct order as the
2121 * original device list was sorted by (domain, bus, devfn) lexicographically
2122 * and all devices on the new list have the same bus number.
2125 bus->last_dev = &d->next;
2132 struct device *d, *d2;
2133 struct bridge **last_br, *b;
2135 /* Build list of bridges */
2137 last_br = &host_bridge.chain;
2138 for(d=first_dev; d; d=d->next)
2140 word class = d->dev->device_class;
2141 byte ht = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
2142 if (class == PCI_CLASS_BRIDGE_PCI &&
2143 (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS))
2145 b = xmalloc(sizeof(struct bridge));
2146 b->domain = d->dev->domain;
2147 if (ht == PCI_HEADER_TYPE_BRIDGE)
2149 b->primary = get_conf_byte(d, PCI_PRIMARY_BUS);
2150 b->secondary = get_conf_byte(d, PCI_SECONDARY_BUS);
2151 b->subordinate = get_conf_byte(d, PCI_SUBORDINATE_BUS);
2155 b->primary = get_conf_byte(d, PCI_CB_PRIMARY_BUS);
2156 b->secondary = get_conf_byte(d, PCI_CB_CARD_BUS);
2157 b->subordinate = get_conf_byte(d, PCI_CB_SUBORDINATE_BUS);
2160 last_br = &b->chain;
2161 b->next = b->child = NULL;
2162 b->first_bus = NULL;
2168 /* Create a bridge tree */
2170 for(b=&host_bridge; b; b=b->chain)
2172 struct bridge *c, *best;
2174 for(c=&host_bridge; c; c=c->chain)
2175 if (c != b && (c == &host_bridge || b->domain == c->domain) &&
2176 b->primary >= c->secondary && b->primary <= c->subordinate &&
2177 (!best || best->subordinate - best->primary > c->subordinate - c->primary))
2181 b->next = best->child;
2186 /* Insert secondary bus for each bridge */
2188 for(b=&host_bridge; b; b=b->chain)
2189 if (!find_bus(b, b->domain, b->secondary))
2190 new_bus(b, b->domain, b->secondary);
2192 /* Create bus structs and link devices */
2194 for(d=first_dev; d;)
2197 insert_dev(d, &host_bridge);
2203 print_it(char *line, char *p)
2207 fputs(line, stdout);
2208 for(p=line; *p; p++)
2209 if (*p == '+' || *p == '|')
2215 static void show_tree_bridge(struct bridge *, char *, char *);
2218 show_tree_dev(struct device *d, char *line, char *p)
2220 struct pci_dev *q = d->dev;
2224 p += sprintf(p, "%02x.%x", q->dev, q->func);
2225 for(b=&host_bridge; b; b=b->chain)
2228 if (b->secondary == b->subordinate)
2229 p += sprintf(p, "-[%04x:%02x]-", b->domain, b->secondary);
2231 p += sprintf(p, "-[%04x:%02x-%02x]-", b->domain, b->secondary, b->subordinate);
2232 show_tree_bridge(b, line, p);
2236 p += sprintf(p, " %s",
2237 pci_lookup_name(pacc, namebuf, sizeof(namebuf),
2238 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
2239 q->vendor_id, q->device_id));
2244 show_tree_bus(struct bus *b, char *line, char *p)
2248 else if (!b->first_dev->next)
2252 show_tree_dev(b->first_dev, line, p);
2256 struct device *d = b->first_dev;
2261 show_tree_dev(d, line, p+2);
2266 show_tree_dev(d, line, p+2);
2271 show_tree_bridge(struct bridge *b, char *line, char *p)
2274 if (!b->first_bus->sibling)
2276 if (b == &host_bridge)
2277 p += sprintf(p, "[%04x:%02x]-", b->domain, b->first_bus->number);
2278 show_tree_bus(b->first_bus, line, p);
2282 struct bus *u = b->first_bus;
2287 k = p + sprintf(p, "+-[%04x:%02x]-", u->domain, u->number);
2288 show_tree_bus(u, line, k);
2291 k = p + sprintf(p, "\\-[%04x:%02x]-", u->domain, u->number);
2292 show_tree_bus(u, line, k);
2302 show_tree_bridge(&host_bridge, line, line);
2305 /*** Bus mapping mode ***/
2308 struct bus_bridge *next;
2309 byte this, dev, func, first, last, bug;
2315 struct bus_bridge *bridges, *via;
2318 static struct bus_info *bus_info;
2321 map_bridge(struct bus_info *bi, struct device *d, int np, int ns, int nl)
2323 struct bus_bridge *b = xmalloc(sizeof(struct bus_bridge));
2324 struct pci_dev *p = d->dev;
2326 b->next = bi->bridges;
2328 b->this = get_conf_byte(d, np);
2331 b->first = get_conf_byte(d, ns);
2332 b->last = get_conf_byte(d, nl);
2333 printf("## %02x.%02x:%d is a bridge from %02x to %02x-%02x\n",
2334 p->bus, p->dev, p->func, b->this, b->first, b->last);
2335 if (b->this != p->bus)
2336 printf("!!! Bridge points to invalid primary bus.\n");
2337 if (b->first > b->last)
2339 printf("!!! Bridge points to invalid bus range.\n");
2348 int verbose = pacc->debugging;
2349 struct bus_info *bi = bus_info + bus;
2353 printf("Mapping bus %02x\n", bus);
2354 for(dev = 0; dev < 32; dev++)
2355 if (filter.slot < 0 || filter.slot == dev)
2358 for(func = 0; func < func_limit; func++)
2359 if (filter.func < 0 || filter.func == func)
2361 /* XXX: Bus mapping supports only domain 0 */
2362 struct pci_dev *p = pci_get_dev(pacc, 0, bus, dev, func);
2363 u16 vendor = pci_read_word(p, PCI_VENDOR_ID);
2364 if (vendor && vendor != 0xffff)
2366 if (!func && (pci_read_byte(p, PCI_HEADER_TYPE) & 0x80))
2369 printf("Discovered device %02x:%02x.%d\n", bus, dev, func);
2371 if (d = scan_device(p))
2374 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
2376 case PCI_HEADER_TYPE_BRIDGE:
2377 map_bridge(bi, d, PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS);
2379 case PCI_HEADER_TYPE_CARDBUS:
2380 map_bridge(bi, d, PCI_CB_PRIMARY_BUS, PCI_CB_CARD_BUS, PCI_CB_SUBORDINATE_BUS);
2386 printf("But it was filtered out.\n");
2394 do_map_bridges(int bus, int min, int max)
2396 struct bus_info *bi = bus_info + bus;
2397 struct bus_bridge *b;
2400 for(b=bi->bridges; b; b=b->next)
2402 if (bus_info[b->first].guestbook)
2404 else if (b->first < min || b->last > max)
2408 bus_info[b->first].via = b;
2409 do_map_bridges(b->first, b->first, b->last);
2419 printf("\nSummary of buses:\n\n");
2420 for(i=0; i<256; i++)
2421 if (bus_info[i].exists && !bus_info[i].guestbook)
2422 do_map_bridges(i, 0, 255);
2423 for(i=0; i<256; i++)
2425 struct bus_info *bi = bus_info + i;
2426 struct bus_bridge *b = bi->via;
2430 printf("%02x: ", i);
2432 printf("Entered via %02x:%02x.%d\n", b->this, b->dev, b->func);
2434 printf("Primary host bus\n");
2436 printf("Secondary host bus (?)\n");
2438 for(b=bi->bridges; b; b=b->next)
2440 printf("\t%02x.%d Bridge to %02x-%02x", b->dev, b->func, b->first, b->last);
2444 printf(" <overlap bug>");
2447 printf(" <crossing bug>");
2458 if (pacc->method == PCI_ACCESS_PROC_BUS_PCI ||
2459 pacc->method == PCI_ACCESS_DUMP)
2460 printf("WARNING: Bus mapping can be reliable only with direct hardware access enabled.\n\n");
2461 bus_info = xmalloc(sizeof(struct bus_info) * 256);
2462 memset(bus_info, 0, sizeof(struct bus_info) * 256);
2463 if (filter.bus >= 0)
2464 do_map_bus(filter.bus);
2468 for(bus=0; bus<256; bus++)
2477 main(int argc, char **argv)
2482 if (argc == 2 && !strcmp(argv[1], "--version"))
2484 puts("lspci version " PCIUTILS_VERSION);
2490 pci_filter_init(pacc, &filter);
2492 while ((i = getopt(argc, argv, options)) != -1)
2496 pacc->numeric_ids++;
2502 pacc->buscentric = 1;
2506 if (msg = pci_filter_parse_slot(&filter, optarg))
2510 if (msg = pci_filter_parse_id(&filter, optarg))
2520 pci_set_name_list_path(pacc, optarg, 0);
2532 if (parse_generic_option(i, pacc, optarg))
2535 fprintf(stderr, help_msg, pacc->id_file_name);
2555 return (seen_errors ? 2 : 0);