2 * The PCI Utilities -- List All PCI Devices
4 * Copyright (c) 1997--2004 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
19 static int verbose; /* Show detailed information */
20 static int buscentric_view; /* Show bus addresses/IRQ's instead of CPU-visible ones */
21 static int show_hex; /* Show contents of config space as hexadecimal numbers */
22 static struct pci_filter filter; /* Device filter */
23 static int show_tree; /* Show bus tree */
24 static int machine_readable; /* Generate machine-readable output */
25 static int map_mode; /* Bus mapping mode enabled */
27 static char options[] = "nvbxs:d:ti:mgM" GENERIC_OPTIONS ;
29 static char help_msg[] = "\
30 Usage: lspci [<switches>]\n\
33 -n\t\tShow numeric ID's\n\
34 -b\t\tBus-centric view (PCI addresses and IRQ's instead of those seen by the CPU)\n\
35 -x\t\tShow hex-dump of the standard portion of config space\n\
36 -xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n\
37 -xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n\
38 -s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n\
39 -d [<vendor>]:[<device>]\tShow only selected devices\n\
40 -t\t\tShow bus tree\n\
41 -m\t\tProduce machine-readable output\n\
42 -i <file>\tUse specified ID database instead of %s\n\
43 -M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
47 /* Communication with libpci */
49 static struct pci_access *pacc;
52 * If we aren't being compiled by GCC, use malloc() instead of alloca().
53 * This increases our memory footprint, but only slightly since we don't
61 /* Our view of the PCI bus */
66 unsigned int config_cnt, config_bufsize;
70 static struct device *first_dev;
73 config_fetch(struct device *d, unsigned int pos, unsigned int len)
75 unsigned int end = pos+len;
77 if (end <= d->config_cnt)
79 if (end > d->config_bufsize)
81 while (end > d->config_bufsize)
82 d->config_bufsize *= 2;
83 d->config = xrealloc(d->config, d->config_bufsize);
85 result = pci_read_block(d->dev, pos, d->config + pos, len);
86 if (result && pos == d->config_cnt)
91 static struct device *
92 scan_device(struct pci_dev *p)
96 if (!pci_filter_match(&filter, p))
98 d = xmalloc(sizeof(struct device));
101 d->config_cnt = d->config_bufsize = 64;
102 d->config = xmalloc(64);
103 if (!pci_read_block(p, 0, d->config, 64))
104 die("Unable to read the configuration space header.");
105 if ((d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
107 /* For cardbus bridges, we need to fetch 64 bytes more to get the
108 * full standard header... */
109 if (!config_fetch(d, 64, 64))
110 die("Unable to read cardbus bridge extension data.");
112 pci_setup_cache(p, d->config, d->config_cnt);
113 pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
124 for(p=pacc->devices; p; p=p->next)
125 if (d = scan_device(p))
132 /* Config space accesses */
135 get_conf_byte(struct device *d, unsigned int pos)
137 return d->config[pos];
141 get_conf_word(struct device *d, unsigned int pos)
143 return d->config[pos] | (d->config[pos+1] << 8);
147 get_conf_long(struct device *d, unsigned int pos)
149 return d->config[pos] |
150 (d->config[pos+1] << 8) |
151 (d->config[pos+2] << 16) |
152 (d->config[pos+3] << 24);
158 compare_them(const void *A, const void *B)
160 const struct pci_dev *a = (*(const struct device **)A)->dev;
161 const struct pci_dev *b = (*(const struct device **)B)->dev;
163 if (a->domain < b->domain)
165 if (a->domain > b->domain)
175 if (a->func < b->func)
177 if (a->func > b->func)
185 struct device **index, **h, **last_dev;
190 for(d=first_dev; d; d=d->next)
192 h = index = alloca(sizeof(struct device *) * cnt);
193 for(d=first_dev; d; d=d->next)
195 qsort(index, cnt, sizeof(struct device *), compare_them);
196 last_dev = &first_dev;
201 last_dev = &(*h)->next;
209 #define FLAG(x,y) ((x & y) ? '+' : '-')
212 show_slot_name(struct device *d)
214 struct pci_dev *p = d->dev;
217 printf("%04x:", p->domain);
218 printf("%02x:%02x.%d", p->bus, p->dev, p->func);
222 show_terse(struct device *d)
225 struct pci_dev *p = d->dev;
226 byte classbuf[128], devbuf[128];
230 pci_lookup_name(pacc, classbuf, sizeof(classbuf),
232 get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0),
233 pci_lookup_name(pacc, devbuf, sizeof(devbuf),
234 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
235 p->vendor_id, p->device_id, 0, 0));
236 if (c = get_conf_byte(d, PCI_REVISION_ID))
237 printf(" (rev %02x)", c);
241 c = get_conf_byte(d, PCI_CLASS_PROG);
242 x = pci_lookup_name(pacc, devbuf, sizeof(devbuf),
244 get_conf_word(d, PCI_CLASS_DEVICE), c, 0, 0);
247 printf(" (prog-if %02x", c);
257 show_size(pciaddr_t x)
263 printf("%d", (int) x);
264 else if (x < 1048576)
265 printf("%dK", (int)(x / 1024));
266 else if (x < 0x80000000)
267 printf("%dM", (int)(x / 1048576));
269 printf(PCIADDR_T_FMT, x);
274 show_bases(struct device *d, int cnt)
276 struct pci_dev *p = d->dev;
277 word cmd = get_conf_word(d, PCI_COMMAND);
282 pciaddr_t pos = p->base_addr[i];
283 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
284 u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
285 if (flg == 0xffffffff)
287 if (!pos && !flg && !len)
290 printf("\tRegion %d: ", i);
293 if (pos && !flg) /* Reported by the OS, but not by the device */
295 printf("[virtual] ");
298 if (flg & PCI_BASE_ADDRESS_SPACE_IO)
300 pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
301 printf("I/O ports at ");
303 printf(PCIADDR_PORT_FMT, a);
304 else if (flg & PCI_BASE_ADDRESS_IO_MASK)
307 printf("<unassigned>");
308 if (!(cmd & PCI_COMMAND_IO))
309 printf(" [disabled]");
313 int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
314 pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
318 printf("Memory at ");
319 if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
323 printf("<invalid-64bit-slot>");
329 z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
333 printf("%08x" PCIADDR_T_FMT, z, a);
335 printf("<unassigned>");
343 printf(PCIADDR_T_FMT, a);
345 printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
347 printf(" (%s, %sprefetchable)",
348 (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
349 (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
350 (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
351 (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
352 if (!(cmd & PCI_COMMAND_MEMORY))
353 printf(" [disabled]");
361 show_pm(struct device *d, int where, int cap)
364 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
366 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
369 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
370 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
371 FLAG(cap, PCI_PM_CAP_DSI),
372 FLAG(cap, PCI_PM_CAP_D1),
373 FLAG(cap, PCI_PM_CAP_D2),
374 pm_aux_current[(cap >> 6) & 7],
375 FLAG(cap, PCI_PM_CAP_PME_D0),
376 FLAG(cap, PCI_PM_CAP_PME_D1),
377 FLAG(cap, PCI_PM_CAP_PME_D2),
378 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
379 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
380 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
382 t = get_conf_word(d, where + PCI_PM_CTRL);
383 printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
384 t & PCI_PM_CTRL_STATE_MASK,
385 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
386 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
387 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
388 FLAG(t, PCI_PM_CTRL_PME_STATUS));
389 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
391 printf("\t\tBridge: PM%c B3%c\n",
392 FLAG(t, PCI_PM_BPCC_ENABLE),
393 FLAG(~t, PCI_PM_PPB_B2_B3));
397 format_agp_rate(int rate, char *buf, int agp3)
407 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
412 strcpy(buf, "<none>");
416 show_agp(struct device *d, int where, int cap)
423 ver = (cap >> 4) & 0x0f;
425 printf("AGP version %x.%x\n", ver, rev);
428 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
430 t = get_conf_long(d, where + PCI_AGP_STATUS);
431 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
433 format_agp_rate(t & 7, rate, agp3);
434 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
435 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
436 FLAG(t, PCI_AGP_STATUS_ISOCH),
437 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
438 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
439 FLAG(t, PCI_AGP_STATUS_SBA),
440 FLAG(t, PCI_AGP_STATUS_ITA_COH),
441 FLAG(t, PCI_AGP_STATUS_GART64),
442 FLAG(t, PCI_AGP_STATUS_HTRANS),
443 FLAG(t, PCI_AGP_STATUS_64BIT),
444 FLAG(t, PCI_AGP_STATUS_FW),
445 FLAG(t, PCI_AGP_STATUS_AGP3),
447 t = get_conf_long(d, where + PCI_AGP_COMMAND);
448 format_agp_rate(t & 7, rate, agp3);
449 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
450 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
451 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
452 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
453 FLAG(t, PCI_AGP_COMMAND_SBA),
454 FLAG(t, PCI_AGP_COMMAND_AGP),
455 FLAG(t, PCI_AGP_COMMAND_GART64),
456 FLAG(t, PCI_AGP_COMMAND_64BIT),
457 FLAG(t, PCI_AGP_COMMAND_FW),
462 show_pcix_nobridge(struct device *d, int where)
467 printf("PCI-X non-bridge device.\n");
472 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
475 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
476 status = get_conf_long(d, where + PCI_PCIX_STATUS);
477 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
478 FLAG(command, PCI_PCIX_COMMAND_DPERE),
479 FLAG(command, PCI_PCIX_COMMAND_ERO),
480 ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U),
481 ((command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U));
482 printf("\t\tStatus: Bus=%u Dev=%u Func=%u 64bit%c 133MHz%c SCD%c USC%c, DC=%s, DMMRBC=%u, DMOST=%u, DMCRS=%u, RSCEM%c\n",
483 ((status >> 8) & 0xffU), // bus
484 ((status >> 3) & 0x1fU), // dev
485 (status & PCI_PCIX_STATUS_FUNCTION), // function
486 FLAG(status, PCI_PCIX_STATUS_64BIT),
487 FLAG(status, PCI_PCIX_STATUS_133MHZ),
488 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
489 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
490 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
491 ((status >> 21) & 3U),
492 ((status >> 23) & 7U),
493 ((status >> 26) & 7U),
494 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS));
498 show_pcix_bridge(struct device *d, int where)
502 u32 status, upstcr, downstcr;
504 printf("PCI-X bridge device.\n");
509 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
512 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
513 printf("\t\tSecondary Status: 64bit%c, 133MHz%c, SCD%c, USC%c, SCO%c, SRD%c Freq=%d\n",
514 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
515 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
516 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
517 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
518 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
519 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
520 ((secstatus >> 6) & 7));
521 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
522 printf("\t\tStatus: Bus=%u Dev=%u Func=%u 64bit%c 133MHz%c SCD%c USC%c, SCO%c, SRD%c\n",
523 ((status >> 8) & 0xff), // bus
524 ((status >> 3) & 0x1f), // dev
525 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION), // function
526 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
527 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
528 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
529 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
530 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
531 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
532 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
533 printf("\t\t: Upstream: Capacity=%u, Commitment Limit=%u\n",
534 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
535 (upstcr >> 16) & 0xffff);
536 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
537 printf("\t\t: Downstream: Capacity=%u, Commitment Limit=%u\n",
538 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
539 (downstcr >> 16) & 0xffff);
543 show_pcix(struct device *d, int where)
545 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
547 case PCI_HEADER_TYPE_NORMAL:
548 show_pcix_nobridge(d, where);
550 case PCI_HEADER_TYPE_BRIDGE:
551 show_pcix_bridge(d, where);
557 ht_link_width(unsigned width)
559 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
560 return widths[width];
564 ht_link_freq(unsigned freq)
566 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
567 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
572 show_ht_pri(struct device *d, int where, int cmd)
574 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
575 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
577 printf("HyperTransport: Slave or Primary Interface\n");
581 printf("\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n",
582 (cmd & PCI_HT_PRI_CMD_BUID),
583 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
584 FLAG(cmd, PCI_HT_PRI_CMD_MH),
585 FLAG(cmd, PCI_HT_PRI_CMD_DD),
586 FLAG(cmd, PCI_HT_PRI_CMD_DUL));
587 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
589 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
590 printf("\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n",
591 FLAG(lctr0, PCI_HT_LCTR_CFLE),
592 FLAG(lctr0, PCI_HT_LCTR_CST),
593 FLAG(lctr0, PCI_HT_LCTR_CFE),
594 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
595 FLAG(lctr0, PCI_HT_LCTR_INIT),
596 FLAG(lctr0, PCI_HT_LCTR_EOC),
597 FLAG(lctr0, PCI_HT_LCTR_TXO),
598 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
599 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
600 FLAG(lctr0, PCI_HT_LCTR_LSEN),
601 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
602 FLAG(lctr0, PCI_HT_LCTR_64B));
603 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
604 printf("\t\tLink Config 0: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
605 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
606 FLAG(lcnf0, PCI_HT_LCNF_DFI),
607 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
608 FLAG(lcnf0, PCI_HT_LCNF_DFO),
609 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
610 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
611 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
612 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
613 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
614 printf("\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n",
615 FLAG(lctr1, PCI_HT_LCTR_CFLE),
616 FLAG(lctr1, PCI_HT_LCTR_CST),
617 FLAG(lctr1, PCI_HT_LCTR_CFE),
618 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
619 FLAG(lctr1, PCI_HT_LCTR_INIT),
620 FLAG(lctr1, PCI_HT_LCTR_EOC),
621 FLAG(lctr1, PCI_HT_LCTR_TXO),
622 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
623 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
624 FLAG(lctr1, PCI_HT_LCTR_LSEN),
625 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
626 FLAG(lctr1, PCI_HT_LCTR_64B));
627 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
628 printf("\t\tLink Config 1: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
629 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
630 FLAG(lcnf1, PCI_HT_LCNF_DFI),
631 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
632 FLAG(lcnf1, PCI_HT_LCNF_DFO),
633 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
634 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
635 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
636 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
637 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
638 printf("\t\tRevision ID: %u.%02u\n",
639 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
640 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
641 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
642 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
643 FLAG(lfrer0, PCI_HT_LFRER_PROT),
644 FLAG(lfrer0, PCI_HT_LFRER_OV),
645 FLAG(lfrer0, PCI_HT_LFRER_EOC),
646 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
647 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
648 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
649 FLAG(lfcap0, PCI_HT_LFCAP_200),
650 FLAG(lfcap0, PCI_HT_LFCAP_300),
651 FLAG(lfcap0, PCI_HT_LFCAP_400),
652 FLAG(lfcap0, PCI_HT_LFCAP_500),
653 FLAG(lfcap0, PCI_HT_LFCAP_600),
654 FLAG(lfcap0, PCI_HT_LFCAP_800),
655 FLAG(lfcap0, PCI_HT_LFCAP_1000),
656 FLAG(lfcap0, PCI_HT_LFCAP_1200),
657 FLAG(lfcap0, PCI_HT_LFCAP_1400),
658 FLAG(lfcap0, PCI_HT_LFCAP_1600),
659 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
660 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
661 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
662 FLAG(ftr, PCI_HT_FTR_ISOCFC),
663 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
664 FLAG(ftr, PCI_HT_FTR_CRCTM),
665 FLAG(ftr, PCI_HT_FTR_ECTLT),
666 FLAG(ftr, PCI_HT_FTR_64BA),
667 FLAG(ftr, PCI_HT_FTR_UIDRD));
668 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
669 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
670 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
671 FLAG(lfrer1, PCI_HT_LFRER_PROT),
672 FLAG(lfrer1, PCI_HT_LFRER_OV),
673 FLAG(lfrer1, PCI_HT_LFRER_EOC),
674 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
675 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
676 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
677 FLAG(lfcap1, PCI_HT_LFCAP_200),
678 FLAG(lfcap1, PCI_HT_LFCAP_300),
679 FLAG(lfcap1, PCI_HT_LFCAP_400),
680 FLAG(lfcap1, PCI_HT_LFCAP_500),
681 FLAG(lfcap1, PCI_HT_LFCAP_600),
682 FLAG(lfcap1, PCI_HT_LFCAP_800),
683 FLAG(lfcap1, PCI_HT_LFCAP_1000),
684 FLAG(lfcap1, PCI_HT_LFCAP_1200),
685 FLAG(lfcap1, PCI_HT_LFCAP_1400),
686 FLAG(lfcap1, PCI_HT_LFCAP_1600),
687 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
688 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
689 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
690 FLAG(eh, PCI_HT_EH_PFLE),
691 FLAG(eh, PCI_HT_EH_OFLE),
692 FLAG(eh, PCI_HT_EH_PFE),
693 FLAG(eh, PCI_HT_EH_OFE),
694 FLAG(eh, PCI_HT_EH_EOCFE),
695 FLAG(eh, PCI_HT_EH_RFE),
696 FLAG(eh, PCI_HT_EH_CRCFE),
697 FLAG(eh, PCI_HT_EH_SERRFE),
698 FLAG(eh, PCI_HT_EH_CF),
699 FLAG(eh, PCI_HT_EH_RE),
700 FLAG(eh, PCI_HT_EH_PNFE),
701 FLAG(eh, PCI_HT_EH_ONFE),
702 FLAG(eh, PCI_HT_EH_EOCNFE),
703 FLAG(eh, PCI_HT_EH_RNFE),
704 FLAG(eh, PCI_HT_EH_CRCNFE),
705 FLAG(eh, PCI_HT_EH_SERRNFE));
706 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
707 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
708 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
709 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
710 printf("\t\tBus Number: %02x\n", bn);
714 show_ht_sec(struct device *d, int where, int cmd)
716 u16 lctr, lcnf, ftr, eh;
717 u8 rid, lfrer, lfcap, mbu, mlu;
719 printf("HyperTransport: Host or Secondary Interface\n");
723 printf("\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n",
724 FLAG(cmd, PCI_HT_SEC_CMD_WR),
725 FLAG(cmd, PCI_HT_SEC_CMD_DE),
726 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
727 FLAG(cmd, PCI_HT_SEC_CMD_CS),
728 FLAG(cmd, PCI_HT_SEC_CMD_HH),
729 FLAG(cmd, PCI_HT_SEC_CMD_AS),
730 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
731 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
732 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
734 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
735 printf("\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n",
736 FLAG(lctr, PCI_HT_LCTR_CFLE),
737 FLAG(lctr, PCI_HT_LCTR_CST),
738 FLAG(lctr, PCI_HT_LCTR_CFE),
739 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
740 FLAG(lctr, PCI_HT_LCTR_INIT),
741 FLAG(lctr, PCI_HT_LCTR_EOC),
742 FLAG(lctr, PCI_HT_LCTR_TXO),
743 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
744 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
745 FLAG(lctr, PCI_HT_LCTR_LSEN),
746 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
747 FLAG(lctr, PCI_HT_LCTR_64B));
748 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
749 printf("\t\tLink Config: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
750 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
751 FLAG(lcnf, PCI_HT_LCNF_DFI),
752 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
753 FLAG(lcnf, PCI_HT_LCNF_DFO),
754 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
755 FLAG(lcnf, PCI_HT_LCNF_DFIE),
756 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
757 FLAG(lcnf, PCI_HT_LCNF_DFOE));
758 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
759 printf("\t\tRevision ID: %u.%02u\n",
760 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
761 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
762 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
763 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
764 FLAG(lfrer, PCI_HT_LFRER_PROT),
765 FLAG(lfrer, PCI_HT_LFRER_OV),
766 FLAG(lfrer, PCI_HT_LFRER_EOC),
767 FLAG(lfrer, PCI_HT_LFRER_CTLT));
768 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
769 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
770 FLAG(lfcap, PCI_HT_LFCAP_200),
771 FLAG(lfcap, PCI_HT_LFCAP_300),
772 FLAG(lfcap, PCI_HT_LFCAP_400),
773 FLAG(lfcap, PCI_HT_LFCAP_500),
774 FLAG(lfcap, PCI_HT_LFCAP_600),
775 FLAG(lfcap, PCI_HT_LFCAP_800),
776 FLAG(lfcap, PCI_HT_LFCAP_1000),
777 FLAG(lfcap, PCI_HT_LFCAP_1200),
778 FLAG(lfcap, PCI_HT_LFCAP_1400),
779 FLAG(lfcap, PCI_HT_LFCAP_1600),
780 FLAG(lfcap, PCI_HT_LFCAP_VEND));
781 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
782 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
783 FLAG(ftr, PCI_HT_FTR_ISOCFC),
784 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
785 FLAG(ftr, PCI_HT_FTR_CRCTM),
786 FLAG(ftr, PCI_HT_FTR_ECTLT),
787 FLAG(ftr, PCI_HT_FTR_64BA),
788 FLAG(ftr, PCI_HT_FTR_UIDRD),
789 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
790 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
791 if (ftr & PCI_HT_SEC_FTR_EXTRS)
793 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
794 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
795 FLAG(eh, PCI_HT_EH_PFLE),
796 FLAG(eh, PCI_HT_EH_OFLE),
797 FLAG(eh, PCI_HT_EH_PFE),
798 FLAG(eh, PCI_HT_EH_OFE),
799 FLAG(eh, PCI_HT_EH_EOCFE),
800 FLAG(eh, PCI_HT_EH_RFE),
801 FLAG(eh, PCI_HT_EH_CRCFE),
802 FLAG(eh, PCI_HT_EH_SERRFE),
803 FLAG(eh, PCI_HT_EH_CF),
804 FLAG(eh, PCI_HT_EH_RE),
805 FLAG(eh, PCI_HT_EH_PNFE),
806 FLAG(eh, PCI_HT_EH_ONFE),
807 FLAG(eh, PCI_HT_EH_EOCNFE),
808 FLAG(eh, PCI_HT_EH_RNFE),
809 FLAG(eh, PCI_HT_EH_CRCNFE),
810 FLAG(eh, PCI_HT_EH_SERRNFE));
811 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
812 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
813 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
818 show_ht(struct device *d, int where, int cmd)
822 switch (cmd & PCI_HT_CMD_TYP_HI)
824 case PCI_HT_CMD_TYP_HI_PRI:
825 show_ht_pri(d, where, cmd);
827 case PCI_HT_CMD_TYP_HI_SEC:
828 show_ht_sec(d, where, cmd);
832 type = cmd & PCI_HT_CMD_TYP;
835 case PCI_HT_CMD_TYP_SW:
836 printf("HyperTransport: Switch\n");
838 case PCI_HT_CMD_TYP_IDC:
839 printf("HyperTransport: Interrupt Discovery and Configuration\n");
841 case PCI_HT_CMD_TYP_RID:
842 printf("HyperTransport: Revision ID: %u.%02u\n",
843 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
845 case PCI_HT_CMD_TYP_UIDC:
846 printf("HyperTransport: UnitID Clumping\n");
848 case PCI_HT_CMD_TYP_ECSA:
849 printf("HyperTransport: Extended Configuration Space Access\n");
851 case PCI_HT_CMD_TYP_AM:
852 printf("HyperTransport: Address Mapping\n");
854 case PCI_HT_CMD_TYP_MSIM:
855 printf("HyperTransport: MSI Mapping\n");
857 case PCI_HT_CMD_TYP_DR:
858 printf("HyperTransport: DirectRoute\n");
860 case PCI_HT_CMD_TYP_VCS:
861 printf("HyperTransport: VCSet\n");
863 case PCI_HT_CMD_TYP_RM:
864 printf("HyperTransport: Retry Mode\n");
866 case PCI_HT_CMD_TYP_X86:
867 printf("HyperTransport: X86 (reserved)\n");
870 printf("HyperTransport: #%02x\n", type >> 11);
875 show_rom(struct device *d)
877 struct pci_dev *p = d->dev;
878 pciaddr_t rom = p->rom_base_addr;
879 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
883 printf("\tExpansion ROM at ");
884 if (rom & PCI_ROM_ADDRESS_MASK)
885 printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
887 printf("<unassigned>");
888 if (!(rom & PCI_ROM_ADDRESS_ENABLE))
889 printf(" [disabled]");
895 show_msi(struct device *d, int where, int cap)
901 printf("Message Signalled Interrupts: 64bit%c Queue=%d/%d Enable%c\n",
902 FLAG(cap, PCI_MSI_FLAGS_64BIT),
903 (cap & PCI_MSI_FLAGS_QSIZE) >> 4,
904 (cap & PCI_MSI_FLAGS_QMASK) >> 1,
905 FLAG(cap, PCI_MSI_FLAGS_ENABLE));
908 is64 = cap & PCI_MSI_FLAGS_64BIT;
909 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
911 printf("\t\tAddress: ");
914 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
915 w = get_conf_word(d, where + PCI_MSI_DATA_64);
919 w = get_conf_word(d, where + PCI_MSI_DATA_32);
920 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
921 printf("%08x Data: %04x\n", t, w);
924 static void show_vendor(void)
926 printf("Vendor Specific Information\n");
929 static void show_debug(void)
931 printf("Debug port\n");
934 static float power_limit(int value, int scale)
936 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
937 return value * scales[scale];
940 static const char *latency_l0s(int value)
942 static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
943 return latencies[value];
946 static const char *latency_l1(int value)
948 static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
949 return latencies[value];
952 static void show_express_dev(struct device *d, int where, int type)
957 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
958 printf("\t\tDevice: Supported: MaxPayload %d bytes, PhantFunc %d, ExtTag%c\n",
959 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
960 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
961 FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
962 printf("\t\tDevice: Latency L0s %s, L1 %s\n",
963 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
964 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
965 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
966 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
967 printf("\t\tDevice: AtnBtn%c AtnInd%c PwrInd%c\n",
968 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
969 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
970 if (type == PCI_EXP_TYPE_UPSTREAM)
971 printf("\t\tDevice: SlotPowerLimit %f\n",
972 power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
973 (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
975 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
976 printf("\t\tDevice: Errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
977 FLAG(w, PCI_EXP_DEVCTL_CERE),
978 FLAG(w, PCI_EXP_DEVCTL_NFERE),
979 FLAG(w, PCI_EXP_DEVCTL_FERE),
980 FLAG(w, PCI_EXP_DEVCTL_URRE));
981 printf("\t\tDevice: RlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c\n",
982 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
983 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
984 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
985 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
986 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
987 printf("\t\tDevice: MaxPayload %d bytes, MaxReadReq %d bytes\n",
988 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
989 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
992 static char *link_speed(int speed)
1003 static char *aspm_support(int code)
1016 static const char *aspm_enabled(int code)
1018 static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
1022 static void show_express_link(struct device *d, int where, int type)
1027 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
1028 printf("\t\tLink: Supported Speed %s, Width x%d, ASPM %s, Port %d\n",
1029 link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
1030 aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
1032 printf("\t\tLink: Latency L0s %s, L1 %s\n",
1033 latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
1034 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
1035 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
1036 printf("\t\tLink: ASPM %s", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
1037 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
1038 (type == PCI_EXP_TYPE_LEG_END))
1039 printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
1040 if (w & PCI_EXP_LNKCTL_DISABLE)
1041 printf(" Disabled");
1042 printf(" CommClk%c ExtSynch%c\n", FLAG(w, PCI_EXP_LNKCTL_CLOCK),
1043 FLAG(w, PCI_EXP_LNKCTL_XSYNCH));
1044 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
1045 printf("\t\tLink: Speed %s, Width x%d\n",
1046 link_speed(t & PCI_EXP_LNKSTA_SPEED), (t & PCI_EXP_LNKSTA_WIDTH) >> 4);
1049 static const char *indicator(int code)
1051 static const char *names[] = { "Unknown", "On", "Blink", "Off" };
1055 static void show_express_slot(struct device *d, int where)
1060 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
1061 printf("\t\tSlot: AtnBtn%c PwrCtrl%c MRL%c AtnInd%c PwrInd%c HotPlug%c Surpise%c\n",
1062 FLAG(t, PCI_EXP_SLTCAP_ATNB),
1063 FLAG(t, PCI_EXP_SLTCAP_PWRC),
1064 FLAG(t, PCI_EXP_SLTCAP_MRL),
1065 FLAG(t, PCI_EXP_SLTCAP_ATNI),
1066 FLAG(t, PCI_EXP_SLTCAP_PWRI),
1067 FLAG(t, PCI_EXP_SLTCAP_HPC),
1068 FLAG(t, PCI_EXP_SLTCAP_HPS));
1069 printf("\t\tSlot: Number %d, PowerLimit %f\n", t >> 19,
1070 power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7,
1071 (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15));
1072 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
1073 printf("\t\tSlot: Enabled AtnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c\n",
1074 FLAG(w, PCI_EXP_SLTCTL_ATNB),
1075 FLAG(w, PCI_EXP_SLTCTL_PWRF),
1076 FLAG(w, PCI_EXP_SLTCTL_MRLS),
1077 FLAG(w, PCI_EXP_SLTCTL_PRSD),
1078 FLAG(w, PCI_EXP_SLTCTL_CMDC),
1079 FLAG(w, PCI_EXP_SLTCTL_HPIE));
1080 printf("\t\tSlot: AttnInd %s, PwrInd %s, Power%c\n",
1081 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
1082 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
1083 FLAG(w, w & PCI_EXP_SLTCTL_PWRC));
1086 static void show_express_root(struct device *d, int where)
1088 u16 w = get_conf_word(d, where + PCI_EXP_RTCTL);
1089 printf("\t\tRoot: Correctable%c Non-Fatal%c Fatal%c PME%c\n",
1090 FLAG(w, PCI_EXP_RTCTL_SECEE),
1091 FLAG(w, PCI_EXP_RTCTL_SENFEE),
1092 FLAG(w, PCI_EXP_RTCTL_SEFEE),
1093 FLAG(w, PCI_EXP_RTCTL_PMEIE));
1097 show_express(struct device *d, int where, int cap)
1099 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1106 case PCI_EXP_TYPE_ENDPOINT:
1109 case PCI_EXP_TYPE_LEG_END:
1110 printf("Legacy Endpoint");
1112 case PCI_EXP_TYPE_ROOT_PORT:
1113 slot = cap & PCI_EXP_FLAGS_SLOT;
1114 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1116 case PCI_EXP_TYPE_UPSTREAM:
1117 printf("Upstream Port");
1119 case PCI_EXP_TYPE_DOWNSTREAM:
1120 slot = cap & PCI_EXP_FLAGS_SLOT;
1121 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1123 case PCI_EXP_TYPE_PCI_BRIDGE:
1124 printf("PCI/PCI-X Bridge");
1127 printf("Unknown type");
1129 printf(" IRQ %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1136 if (type == PCI_EXP_TYPE_ROOT_PORT)
1138 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1141 show_express_dev(d, where, type);
1142 show_express_link(d, where, type);
1144 show_express_slot(d, where);
1145 if (type == PCI_EXP_TYPE_ROOT_PORT)
1146 show_express_root(d, where);
1150 show_msix(struct device *d, int where, int cap)
1154 printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
1155 FLAG(cap, PCI_MSIX_ENABLE),
1156 FLAG(cap, PCI_MSIX_MASK),
1157 (cap & PCI_MSIX_TABSIZE) + 1);
1158 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1161 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1162 printf("\t\tVector table: BAR=%d offset=%08x\n",
1163 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1164 off = get_conf_long(d, where + PCI_MSIX_PBA);
1165 printf("\t\tPBA: BAR=%d offset=%08x\n",
1166 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1170 show_slotid(int cap)
1172 int esr = cap & 0xff;
1175 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1176 esr & PCI_SID_ESR_NSLOTS,
1177 FLAG(esr, PCI_SID_ESR_FIC),
1182 show_aer(struct device *d, int where)
1184 printf("Advanced Error Reporting\n");
1188 show_vc(struct device *d, int where)
1190 printf("Virtual Channel\n");
1194 show_dsn(struct device *d, int where)
1197 if (!config_fetch(d, where + 4, 8))
1199 t1 = get_conf_long(d, where + 4);
1200 t2 = get_conf_long(d, where + 8);
1201 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
1202 t1 & 0xff, (t1 >> 8) & 0xff, (t1 >> 16) & 0xff, t1 >> 24,
1203 t2 & 0xff, (t2 >> 8) & 0xff, (t2 >> 16) & 0xff, t2 >> 24);
1207 show_pb(struct device *d, int where)
1209 printf("Power Budgeting\n");
1213 show_ext_caps(struct device *d)
1221 if (!config_fetch(d, where, 4))
1223 header = get_conf_long(d, where);
1226 id = header & 0xffff;
1227 printf("\tCapabilities: [%03x] ", where);
1230 case PCI_EXT_CAP_ID_AER:
1233 case PCI_EXT_CAP_ID_VC:
1236 case PCI_EXT_CAP_ID_DSN:
1239 case PCI_EXT_CAP_ID_PB:
1243 printf("Unknown (%d)\n", id);
1246 where = header >> 20;
1251 show_caps(struct device *d)
1253 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1255 int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
1259 printf("\tCapabilities: ");
1260 if (!config_fetch(d, where, 4))
1262 puts("<available only to root>");
1265 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1266 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1267 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1268 printf("[%02x] ", where);
1271 printf("<chain broken>\n");
1277 show_pm(d, where, cap);
1279 case PCI_CAP_ID_AGP:
1280 show_agp(d, where, cap);
1282 case PCI_CAP_ID_VPD:
1283 printf("Vital Product Data\n");
1285 case PCI_CAP_ID_SLOTID:
1288 case PCI_CAP_ID_MSI:
1289 show_msi(d, where, cap);
1291 case PCI_CAP_ID_PCIX:
1292 show_pcix(d, where);
1295 show_ht(d, where, cap);
1297 case PCI_CAP_ID_VNDR:
1300 case PCI_CAP_ID_DBG:
1303 case PCI_CAP_ID_EXP:
1304 show_express(d, where, cap);
1306 case PCI_CAP_ID_MSIX:
1307 show_msix(d, where, cap);
1310 printf("#%02x [%04x]\n", id, cap);
1319 show_htype0(struct device *d)
1327 show_htype1(struct device *d)
1329 u32 io_base = get_conf_byte(d, PCI_IO_BASE);
1330 u32 io_limit = get_conf_byte(d, PCI_IO_LIMIT);
1331 u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
1332 u32 mem_base = get_conf_word(d, PCI_MEMORY_BASE);
1333 u32 mem_limit = get_conf_word(d, PCI_MEMORY_LIMIT);
1334 u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
1335 u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE);
1336 u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT);
1337 u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
1338 word sec_stat = get_conf_word(d, PCI_SEC_STATUS);
1339 word brc = get_conf_word(d, PCI_BRIDGE_CONTROL);
1340 int verb = verbose > 2;
1343 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1344 get_conf_byte(d, PCI_PRIMARY_BUS),
1345 get_conf_byte(d, PCI_SECONDARY_BUS),
1346 get_conf_byte(d, PCI_SUBORDINATE_BUS),
1347 get_conf_byte(d, PCI_SEC_LATENCY_TIMER));
1349 if (io_type != (io_limit & PCI_IO_RANGE_TYPE_MASK) ||
1350 (io_type != PCI_IO_RANGE_TYPE_16 && io_type != PCI_IO_RANGE_TYPE_32))
1351 printf("\t!!! Unknown I/O range types %x/%x\n", io_base, io_limit);
1354 io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
1355 io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
1356 if (io_type == PCI_IO_RANGE_TYPE_32)
1358 io_base |= (get_conf_word(d, PCI_IO_BASE_UPPER16) << 16);
1359 io_limit |= (get_conf_word(d, PCI_IO_LIMIT_UPPER16) << 16);
1361 if (io_base <= io_limit || verb)
1362 printf("\tI/O behind bridge: %08x-%08x\n", io_base, io_limit+0xfff);
1365 if (mem_type != (mem_limit & PCI_MEMORY_RANGE_TYPE_MASK) ||
1367 printf("\t!!! Unknown memory range types %x/%x\n", mem_base, mem_limit);
1370 mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
1371 mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
1372 if (mem_base <= mem_limit || verb)
1373 printf("\tMemory behind bridge: %08x-%08x\n", mem_base, mem_limit + 0xfffff);
1376 if (pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
1377 (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64))
1378 printf("\t!!! Unknown prefetchable memory range types %x/%x\n", pref_base, pref_limit);
1381 pref_base = (pref_base & PCI_PREF_RANGE_MASK) << 16;
1382 pref_limit = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
1383 if (pref_base <= pref_limit || verb)
1385 if (pref_type == PCI_PREF_RANGE_TYPE_32)
1386 printf("\tPrefetchable memory behind bridge: %08x-%08x\n", pref_base, pref_limit + 0xfffff);
1388 printf("\tPrefetchable memory behind bridge: %08x%08x-%08x%08x\n",
1389 get_conf_long(d, PCI_PREF_BASE_UPPER32),
1391 get_conf_long(d, PCI_PREF_LIMIT_UPPER32),
1397 printf("\tSecondary status: 66Mhz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c\n",
1398 FLAG(sec_stat, PCI_STATUS_66MHZ),
1399 FLAG(sec_stat, PCI_STATUS_FAST_BACK),
1400 FLAG(sec_stat, PCI_STATUS_PARITY),
1401 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1402 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1403 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1404 FLAG(sec_stat, PCI_STATUS_SIG_TARGET_ABORT),
1405 FLAG(sec_stat, PCI_STATUS_REC_TARGET_ABORT),
1406 FLAG(sec_stat, PCI_STATUS_REC_MASTER_ABORT),
1407 FLAG(sec_stat, PCI_STATUS_SIG_SYSTEM_ERROR),
1408 FLAG(sec_stat, PCI_STATUS_DETECTED_PARITY));
1413 printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
1414 FLAG(brc, PCI_BRIDGE_CTL_PARITY),
1415 FLAG(brc, PCI_BRIDGE_CTL_SERR),
1416 FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
1417 FLAG(brc, PCI_BRIDGE_CTL_VGA),
1418 FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
1419 FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
1420 FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
1426 show_htype2(struct device *d)
1429 word cmd = get_conf_word(d, PCI_COMMAND);
1430 word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
1431 word exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
1432 int verb = verbose > 2;
1435 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1436 get_conf_byte(d, PCI_CB_PRIMARY_BUS),
1437 get_conf_byte(d, PCI_CB_CARD_BUS),
1438 get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
1439 get_conf_byte(d, PCI_CB_LATENCY_TIMER));
1443 u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
1444 u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
1445 if (limit > base || verb)
1446 printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
1447 (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
1448 (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
1453 u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
1454 u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
1455 if (!(base & PCI_IO_RANGE_TYPE_32))
1460 base &= PCI_CB_IO_RANGE_MASK;
1461 limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
1462 if (base <= limit || verb)
1463 printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
1464 (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
1467 if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
1468 printf("\tSecondary status: SERR\n");
1470 printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
1471 FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
1472 FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
1473 FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
1474 FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
1475 FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
1476 FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
1477 FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
1478 FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
1480 printf("\t16-bit legacy interface ports at %04x\n", exca);
1484 show_verbose(struct device *d)
1486 struct pci_dev *p = d->dev;
1487 word status = get_conf_word(d, PCI_STATUS);
1488 word cmd = get_conf_word(d, PCI_COMMAND);
1489 word class = get_conf_word(d, PCI_CLASS_DEVICE);
1490 byte bist = get_conf_byte(d, PCI_BIST);
1491 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1492 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
1493 byte cache_line = get_conf_byte(d, PCI_CACHE_LINE_SIZE);
1494 byte max_lat, min_gnt;
1495 byte int_pin = get_conf_byte(d, PCI_INTERRUPT_PIN);
1496 unsigned int irq = p->irq;
1497 word subsys_v, subsys_d;
1498 char ssnamebuf[256];
1504 case PCI_HEADER_TYPE_NORMAL:
1505 if (class == PCI_CLASS_BRIDGE_PCI)
1506 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1507 max_lat = get_conf_byte(d, PCI_MAX_LAT);
1508 min_gnt = get_conf_byte(d, PCI_MIN_GNT);
1509 subsys_v = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1510 subsys_d = get_conf_word(d, PCI_SUBSYSTEM_ID);
1512 case PCI_HEADER_TYPE_BRIDGE:
1513 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1514 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1515 irq = int_pin = min_gnt = max_lat = 0;
1516 subsys_v = subsys_d = 0;
1518 case PCI_HEADER_TYPE_CARDBUS:
1519 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1520 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1521 min_gnt = max_lat = 0;
1522 subsys_v = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1523 subsys_d = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1526 printf("\t!!! Unknown header type %02x\n", htype);
1530 if (subsys_v && subsys_v != 0xffff)
1531 printf("\tSubsystem: %s\n",
1532 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1533 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1534 p->vendor_id, p->device_id, subsys_v, subsys_d));
1538 printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c\n",
1539 FLAG(cmd, PCI_COMMAND_IO),
1540 FLAG(cmd, PCI_COMMAND_MEMORY),
1541 FLAG(cmd, PCI_COMMAND_MASTER),
1542 FLAG(cmd, PCI_COMMAND_SPECIAL),
1543 FLAG(cmd, PCI_COMMAND_INVALIDATE),
1544 FLAG(cmd, PCI_COMMAND_VGA_PALETTE),
1545 FLAG(cmd, PCI_COMMAND_PARITY),
1546 FLAG(cmd, PCI_COMMAND_WAIT),
1547 FLAG(cmd, PCI_COMMAND_SERR),
1548 FLAG(cmd, PCI_COMMAND_FAST_BACK));
1549 printf("\tStatus: Cap%c 66Mhz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c\n",
1550 FLAG(status, PCI_STATUS_CAP_LIST),
1551 FLAG(status, PCI_STATUS_66MHZ),
1552 FLAG(status, PCI_STATUS_UDF),
1553 FLAG(status, PCI_STATUS_FAST_BACK),
1554 FLAG(status, PCI_STATUS_PARITY),
1555 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1556 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1557 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1558 FLAG(status, PCI_STATUS_SIG_TARGET_ABORT),
1559 FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
1560 FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
1561 FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
1562 FLAG(status, PCI_STATUS_DETECTED_PARITY));
1563 if (cmd & PCI_COMMAND_MASTER)
1565 printf("\tLatency: %d", latency);
1566 if (min_gnt || max_lat)
1570 printf("%dns min", min_gnt*250);
1571 if (min_gnt && max_lat)
1574 printf("%dns max", max_lat*250);
1578 printf(", Cache Line Size %02x", cache_line);
1582 printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n",
1583 (int_pin ? 'A' + int_pin - 1 : '?'), irq);
1587 printf("\tFlags: ");
1588 if (cmd & PCI_COMMAND_MASTER)
1589 printf("bus master, ");
1590 if (cmd & PCI_COMMAND_VGA_PALETTE)
1591 printf("VGA palette snoop, ");
1592 if (cmd & PCI_COMMAND_WAIT)
1593 printf("stepping, ");
1594 if (cmd & PCI_COMMAND_FAST_BACK)
1595 printf("fast Back2Back, ");
1596 if (status & PCI_STATUS_66MHZ)
1598 if (status & PCI_STATUS_UDF)
1599 printf("user-definable features, ");
1601 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1602 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1603 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??");
1604 if (cmd & PCI_COMMAND_MASTER)
1605 printf(", latency %d", latency);
1607 printf(", IRQ " PCIIRQ_FMT, irq);
1611 if (bist & PCI_BIST_CAPABLE)
1613 if (bist & PCI_BIST_START)
1614 printf("\tBIST is running\n");
1616 printf("\tBIST result: %02x\n", bist & PCI_BIST_CODE_MASK);
1621 case PCI_HEADER_TYPE_NORMAL:
1624 case PCI_HEADER_TYPE_BRIDGE:
1627 case PCI_HEADER_TYPE_CARDBUS:
1634 show_hex_dump(struct device *d)
1636 unsigned int i, cnt;
1638 cnt = d->config_cnt;
1639 if (show_hex >= 3 && config_fetch(d, cnt, 256-cnt))
1642 if (show_hex >= 4 && config_fetch(d, 256, 4096-256))
1646 for(i=0; i<cnt; i++)
1650 printf(" %02x", get_conf_byte(d, i));
1657 show_machine(struct device *d)
1659 struct pci_dev *p = d->dev;
1661 word sv_id=0, sd_id=0;
1662 char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
1664 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
1666 case PCI_HEADER_TYPE_NORMAL:
1667 sv_id = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1668 sd_id = get_conf_word(d, PCI_SUBSYSTEM_ID);
1670 case PCI_HEADER_TYPE_CARDBUS:
1671 sv_id = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1672 sd_id = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1678 printf("Device:\t");
1681 printf("Class:\t%s\n",
1682 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0));
1683 printf("Vendor:\t%s\n",
1684 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, 0, 0));
1685 printf("Device:\t%s\n",
1686 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, 0, 0));
1687 if (sv_id && sv_id != 0xffff)
1689 printf("SVendor:\t%s\n",
1690 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, sv_id, sd_id));
1691 printf("SDevice:\t%s\n",
1692 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1694 if (c = get_conf_byte(d, PCI_REVISION_ID))
1695 printf("Rev:\t%02x\n", c);
1696 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1697 printf("ProgIf:\t%02x\n", c);
1702 printf(" \"%s\" \"%s\" \"%s\"",
1703 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS,
1704 get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0),
1705 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR,
1706 p->vendor_id, p->device_id, 0, 0),
1707 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE,
1708 p->vendor_id, p->device_id, 0, 0));
1709 if (c = get_conf_byte(d, PCI_REVISION_ID))
1710 printf(" -r%02x", c);
1711 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1712 printf(" -p%02x", c);
1713 if (sv_id && sv_id != 0xffff)
1714 printf(" \"%s\" \"%s\"",
1715 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, sv_id, sd_id),
1716 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1718 printf(" \"\" \"\"");
1724 show_device(struct device *d)
1726 if (machine_readable)
1734 if (verbose || show_hex)
1743 for(d=first_dev; d; d=d->next)
1750 struct bridge *chain; /* Single-linked list of bridges */
1751 struct bridge *next, *child; /* Tree of bridges */
1752 struct bus *first_bus; /* List of busses connected to this bridge */
1753 unsigned int domain;
1754 unsigned int primary, secondary, subordinate; /* Bus numbers */
1755 struct device *br_dev;
1759 unsigned int domain;
1760 unsigned int number;
1761 struct bus *sibling;
1762 struct device *first_dev, **last_dev;
1765 static struct bridge host_bridge = { NULL, NULL, NULL, NULL, 0, ~0, 0, ~0, NULL };
1768 find_bus(struct bridge *b, unsigned int domain, unsigned int n)
1772 for(bus=b->first_bus; bus; bus=bus->sibling)
1773 if (bus->domain == domain && bus->number == n)
1779 new_bus(struct bridge *b, unsigned int domain, unsigned int n)
1781 struct bus *bus = xmalloc(sizeof(struct bus));
1783 bus = xmalloc(sizeof(struct bus));
1784 bus->domain = domain;
1786 bus->sibling = b->first_bus;
1787 bus->first_dev = NULL;
1788 bus->last_dev = &bus->first_dev;
1794 insert_dev(struct device *d, struct bridge *b)
1796 struct pci_dev *p = d->dev;
1799 if (! (bus = find_bus(b, p->domain, p->bus)))
1802 for(c=b->child; c; c=c->next)
1803 if (c->domain == p->domain && c->secondary <= p->bus && p->bus <= c->subordinate)
1808 bus = new_bus(b, p->domain, p->bus);
1810 /* Simple insertion at the end _does_ guarantee the correct order as the
1811 * original device list was sorted by (domain, bus, devfn) lexicographically
1812 * and all devices on the new list have the same bus number.
1815 bus->last_dev = &d->next;
1822 struct device *d, *d2;
1823 struct bridge **last_br, *b;
1825 /* Build list of bridges */
1827 last_br = &host_bridge.chain;
1828 for(d=first_dev; d; d=d->next)
1830 word class = get_conf_word(d, PCI_CLASS_DEVICE);
1831 byte ht = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1832 if (class == PCI_CLASS_BRIDGE_PCI &&
1833 (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS))
1835 b = xmalloc(sizeof(struct bridge));
1836 b->domain = d->dev->domain;
1837 if (ht == PCI_HEADER_TYPE_BRIDGE)
1839 b->primary = get_conf_byte(d, PCI_CB_PRIMARY_BUS);
1840 b->secondary = get_conf_byte(d, PCI_CB_CARD_BUS);
1841 b->subordinate = get_conf_byte(d, PCI_CB_SUBORDINATE_BUS);
1845 b->primary = get_conf_byte(d, PCI_PRIMARY_BUS);
1846 b->secondary = get_conf_byte(d, PCI_SECONDARY_BUS);
1847 b->subordinate = get_conf_byte(d, PCI_SUBORDINATE_BUS);
1850 last_br = &b->chain;
1851 b->next = b->child = NULL;
1852 b->first_bus = NULL;
1858 /* Create a bridge tree */
1860 for(b=&host_bridge; b; b=b->chain)
1862 struct bridge *c, *best;
1864 for(c=&host_bridge; c; c=c->chain)
1865 if (c != b && (c == &host_bridge || b->domain == c->domain) &&
1866 b->primary >= c->secondary && b->primary <= c->subordinate &&
1867 (!best || best->subordinate - best->primary > c->subordinate - c->primary))
1871 b->next = best->child;
1876 /* Insert secondary bus for each bridge */
1878 for(b=&host_bridge; b; b=b->chain)
1879 if (!find_bus(b, b->domain, b->secondary))
1880 new_bus(b, b->domain, b->secondary);
1882 /* Create bus structs and link devices */
1884 for(d=first_dev; d;)
1887 insert_dev(d, &host_bridge);
1893 print_it(byte *line, byte *p)
1897 fputs(line, stdout);
1898 for(p=line; *p; p++)
1899 if (*p == '+' || *p == '|')
1905 static void show_tree_bridge(struct bridge *, byte *, byte *);
1908 show_tree_dev(struct device *d, byte *line, byte *p)
1910 struct pci_dev *q = d->dev;
1914 p += sprintf(p, "%02x.%x", q->dev, q->func);
1915 for(b=&host_bridge; b; b=b->chain)
1918 if (b->secondary == b->subordinate)
1919 p += sprintf(p, "-[%04x:%02x]-", b->domain, b->secondary);
1921 p += sprintf(p, "-[%04x:%02x-%02x]-", b->domain, b->secondary, b->subordinate);
1922 show_tree_bridge(b, line, p);
1926 p += sprintf(p, " %s",
1927 pci_lookup_name(pacc, namebuf, sizeof(namebuf),
1928 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1929 q->vendor_id, q->device_id, 0, 0));
1934 show_tree_bus(struct bus *b, byte *line, byte *p)
1938 else if (!b->first_dev->next)
1942 show_tree_dev(b->first_dev, line, p);
1946 struct device *d = b->first_dev;
1951 show_tree_dev(d, line, p+2);
1956 show_tree_dev(d, line, p+2);
1961 show_tree_bridge(struct bridge *b, byte *line, byte *p)
1964 if (!b->first_bus->sibling)
1966 if (b == &host_bridge)
1967 p += sprintf(p, "[%04x:%02x]-", b->domain, b->first_bus->number);
1968 show_tree_bus(b->first_bus, line, p);
1972 struct bus *u = b->first_bus;
1977 k = p + sprintf(p, "+-[%04x:%02x]-", u->domain, u->number);
1978 show_tree_bus(u, line, k);
1981 k = p + sprintf(p, "\\-[%04x:%02x]-", u->domain, u->number);
1982 show_tree_bus(u, line, k);
1992 show_tree_bridge(&host_bridge, line, line);
1995 /* Bus mapping mode */
1998 struct bus_bridge *next;
1999 byte this, dev, func, first, last, bug;
2005 struct bus_bridge *bridges, *via;
2008 static struct bus_info *bus_info;
2011 map_bridge(struct bus_info *bi, struct device *d, int np, int ns, int nl)
2013 struct bus_bridge *b = xmalloc(sizeof(struct bus_bridge));
2014 struct pci_dev *p = d->dev;
2016 b->next = bi->bridges;
2018 b->this = get_conf_byte(d, np);
2021 b->first = get_conf_byte(d, ns);
2022 b->last = get_conf_byte(d, nl);
2023 printf("## %02x.%02x:%d is a bridge from %02x to %02x-%02x\n",
2024 p->bus, p->dev, p->func, b->this, b->first, b->last);
2025 if (b->this != p->bus)
2026 printf("!!! Bridge points to invalid primary bus.\n");
2027 if (b->first > b->last)
2029 printf("!!! Bridge points to invalid bus range.\n");
2038 int verbose = pacc->debugging;
2039 struct bus_info *bi = bus_info + bus;
2043 printf("Mapping bus %02x\n", bus);
2044 for(dev = 0; dev < 32; dev++)
2045 if (filter.slot < 0 || filter.slot == dev)
2048 for(func = 0; func < func_limit; func++)
2049 if (filter.func < 0 || filter.func == func)
2051 /* XXX: Bus mapping supports only domain 0 */
2052 struct pci_dev *p = pci_get_dev(pacc, 0, bus, dev, func);
2053 u16 vendor = pci_read_word(p, PCI_VENDOR_ID);
2054 if (vendor && vendor != 0xffff)
2056 if (!func && (pci_read_byte(p, PCI_HEADER_TYPE) & 0x80))
2059 printf("Discovered device %02x:%02x.%d\n", bus, dev, func);
2061 if (d = scan_device(p))
2064 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
2066 case PCI_HEADER_TYPE_BRIDGE:
2067 map_bridge(bi, d, PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS);
2069 case PCI_HEADER_TYPE_CARDBUS:
2070 map_bridge(bi, d, PCI_CB_PRIMARY_BUS, PCI_CB_CARD_BUS, PCI_CB_SUBORDINATE_BUS);
2076 printf("But it was filtered out.\n");
2084 do_map_bridges(int bus, int min, int max)
2086 struct bus_info *bi = bus_info + bus;
2087 struct bus_bridge *b;
2090 for(b=bi->bridges; b; b=b->next)
2092 if (bus_info[b->first].guestbook)
2094 else if (b->first < min || b->last > max)
2098 bus_info[b->first].via = b;
2099 do_map_bridges(b->first, b->first, b->last);
2109 printf("\nSummary of buses:\n\n");
2110 for(i=0; i<256; i++)
2111 if (bus_info[i].exists && !bus_info[i].guestbook)
2112 do_map_bridges(i, 0, 255);
2113 for(i=0; i<256; i++)
2115 struct bus_info *bi = bus_info + i;
2116 struct bus_bridge *b = bi->via;
2120 printf("%02x: ", i);
2122 printf("Entered via %02x:%02x.%d\n", b->this, b->dev, b->func);
2124 printf("Primary host bus\n");
2126 printf("Secondary host bus (?)\n");
2128 for(b=bi->bridges; b; b=b->next)
2130 printf("\t%02x.%d Bridge to %02x-%02x", b->dev, b->func, b->first, b->last);
2134 printf(" <overlap bug>");
2137 printf(" <crossing bug>");
2148 if (pacc->method == PCI_ACCESS_PROC_BUS_PCI ||
2149 pacc->method == PCI_ACCESS_DUMP)
2150 printf("WARNING: Bus mapping can be reliable only with direct hardware access enabled.\n\n");
2151 bus_info = xmalloc(sizeof(struct bus_info) * 256);
2152 bzero(bus_info, sizeof(struct bus_info) * 256);
2153 if (filter.bus >= 0)
2154 do_map_bus(filter.bus);
2158 for(bus=0; bus<256; bus++)
2167 main(int argc, char **argv)
2172 if (argc == 2 && !strcmp(argv[1], "--version"))
2174 puts("lspci version " PCIUTILS_VERSION);
2180 pci_filter_init(pacc, &filter);
2182 while ((i = getopt(argc, argv, options)) != -1)
2186 pacc->numeric_ids = 1;
2192 pacc->buscentric = 1;
2193 buscentric_view = 1;
2196 if (msg = pci_filter_parse_slot(&filter, optarg))
2200 if (msg = pci_filter_parse_id(&filter, optarg))
2210 pacc->id_file_name = optarg;
2219 if (parse_generic_option(i, pacc, optarg))
2222 fprintf(stderr, help_msg, pacc->id_file_name);