2 * The PCI Utilities -- List All PCI Devices
4 * Copyright (c) 1997--2008 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
15 #define PCIUTILS_LSPCI
20 static int verbose; /* Show detailed information */
21 static int opt_buscentric; /* Show bus addresses/IRQ's instead of CPU-visible ones */
22 static int opt_hex; /* Show contents of config space as hexadecimal numbers */
23 static struct pci_filter filter; /* Device filter */
24 static int opt_tree; /* Show bus tree */
25 static int opt_machine; /* Generate machine-readable output */
26 static int opt_map_mode; /* Bus mapping mode enabled */
27 static int opt_domains; /* Show domain numbers (0=disabled, 1=auto-detected, 2=requested) */
28 static int opt_kernel; /* Show kernel drivers */
29 static int opt_query_dns; /* Query the DNS (0=disabled, 1=enabled, 2=refresh cache) */
30 static int opt_query_all; /* Query the DNS for all entries */
31 static char *opt_pcimap; /* Override path to Linux modules.pcimap */
33 const char program_name[] = "lspci";
35 static char options[] = "nvbxs:d:ti:mgp:qkMDQ" GENERIC_OPTIONS ;
37 static char help_msg[] =
38 "Usage: lspci [<switches>]\n"
40 "Basic display modes:\n"
41 "-mm\t\tProduce machine-readable output (single -m for an obsolete format)\n"
42 "-t\t\tShow bus tree\n"
45 "-v\t\tBe verbose (-vv for very verbose)\n"
47 "-k\t\tShow kernel drivers handling each device\n"
49 "-x\t\tShow hex-dump of the standard part of the config space\n"
50 "-xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n"
51 "-xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n"
52 "-b\t\tBus-centric view (addresses and IRQ's as seen by the bus)\n"
53 "-D\t\tAlways show domain numbers\n"
55 "Resolving of device ID's to names:\n"
56 "-n\t\tShow numeric ID's\n"
57 "-nn\t\tShow both textual and numeric ID's (names & numbers)\n"
59 "-q\t\tQuery the PCI ID database for unknown ID's via DNS\n"
60 "-qq\t\tAs above, but re-query locally cached entries\n"
61 "-Q\t\tQuery the PCI ID database for all ID's via DNS\n"
64 "Selection of devices:\n"
65 "-s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n"
66 "-d [<vendor>]:[<device>]\t\t\tShow only devices with specified ID's\n"
69 "-i <file>\tUse specified ID database instead of %s\n"
71 "-p <file>\tLook up kernel modules in a given file instead of default modules.pcimap\n"
73 "-M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
75 "PCI access options:\n"
79 /*** Communication with libpci ***/
81 static struct pci_access *pacc;
84 * If we aren't being compiled by GCC, use xmalloc() instead of alloca().
85 * This increases our memory footprint, but only slightly since we don't
88 #if defined (__FreeBSD__) || defined (__NetBSD__) || defined (__OpenBSD__) || defined (__DragonFly__)
89 /* alloca() is defined in stdlib.h */
90 #elif defined(__GNUC__) && !defined(PCI_OS_WINDOWS)
94 #define alloca xmalloc
97 /*** Our view of the PCI bus ***/
102 unsigned int config_cached, config_bufsize;
103 byte *config; /* Cached configuration space data */
104 byte *present; /* Maps which configuration bytes are present */
107 static struct device *first_dev;
108 static int seen_errors;
111 config_fetch(struct device *d, unsigned int pos, unsigned int len)
113 unsigned int end = pos+len;
116 while (pos < d->config_bufsize && len && d->present[pos])
118 while (pos+len <= d->config_bufsize && len && d->present[pos+len-1])
123 if (end > d->config_bufsize)
125 int orig_size = d->config_bufsize;
126 while (end > d->config_bufsize)
127 d->config_bufsize *= 2;
128 d->config = xrealloc(d->config, d->config_bufsize);
129 d->present = xrealloc(d->present, d->config_bufsize);
130 memset(d->present + orig_size, 0, d->config_bufsize - orig_size);
132 result = pci_read_block(d->dev, pos, d->config + pos, len);
134 memset(d->present + pos, 1, len);
138 static struct device *
139 scan_device(struct pci_dev *p)
143 if (p->domain && !opt_domains)
145 if (!pci_filter_match(&filter, p))
147 d = xmalloc(sizeof(struct device));
148 memset(d, 0, sizeof(*d));
150 d->config_cached = d->config_bufsize = 64;
151 d->config = xmalloc(64);
152 d->present = xmalloc(64);
153 memset(d->present, 1, 64);
154 if (!pci_read_block(p, 0, d->config, 64))
156 fprintf(stderr, "lspci: Unable to read the standard configuration space header of device %04x:%02x:%02x.%d\n",
157 p->domain, p->bus, p->dev, p->func);
161 if ((d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
163 /* For cardbus bridges, we need to fetch 64 bytes more to get the
164 * full standard header... */
165 if (config_fetch(d, 64, 64))
166 d->config_cached += 64;
168 pci_setup_cache(p, d->config, d->config_cached);
169 pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_CLASS | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
180 for(p=pacc->devices; p; p=p->next)
181 if (d = scan_device(p))
188 /*** Config space accesses ***/
191 check_conf_range(struct device *d, unsigned int pos, unsigned int len)
194 if (!d->present[pos])
195 die("Internal bug: Accessing non-read configuration byte at position %x", pos);
201 get_conf_byte(struct device *d, unsigned int pos)
203 check_conf_range(d, pos, 1);
204 return d->config[pos];
208 get_conf_word(struct device *d, unsigned int pos)
210 check_conf_range(d, pos, 2);
211 return d->config[pos] | (d->config[pos+1] << 8);
215 get_conf_long(struct device *d, unsigned int pos)
217 check_conf_range(d, pos, 4);
218 return d->config[pos] |
219 (d->config[pos+1] << 8) |
220 (d->config[pos+2] << 16) |
221 (d->config[pos+3] << 24);
227 compare_them(const void *A, const void *B)
229 const struct pci_dev *a = (*(const struct device **)A)->dev;
230 const struct pci_dev *b = (*(const struct device **)B)->dev;
232 if (a->domain < b->domain)
234 if (a->domain > b->domain)
244 if (a->func < b->func)
246 if (a->func > b->func)
254 struct device **index, **h, **last_dev;
259 for(d=first_dev; d; d=d->next)
261 h = index = alloca(sizeof(struct device *) * cnt);
262 for(d=first_dev; d; d=d->next)
264 qsort(index, cnt, sizeof(struct device *), compare_them);
265 last_dev = &first_dev;
270 last_dev = &(*h)->next;
276 /*** Normal output ***/
278 #define FLAG(x,y) ((x & y) ? '+' : '-')
281 show_slot_name(struct device *d)
283 struct pci_dev *p = d->dev;
285 if (!opt_machine ? opt_domains : (p->domain || opt_domains >= 2))
286 printf("%04x:", p->domain);
287 printf("%02x:%02x.%d", p->bus, p->dev, p->func);
291 show_terse(struct device *d)
294 struct pci_dev *p = d->dev;
295 char classbuf[128], devbuf[128];
299 pci_lookup_name(pacc, classbuf, sizeof(classbuf),
302 pci_lookup_name(pacc, devbuf, sizeof(devbuf),
303 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
304 p->vendor_id, p->device_id));
305 if (c = get_conf_byte(d, PCI_REVISION_ID))
306 printf(" (rev %02x)", c);
310 c = get_conf_byte(d, PCI_CLASS_PROG);
311 x = pci_lookup_name(pacc, devbuf, sizeof(devbuf),
312 PCI_LOOKUP_PROGIF | PCI_LOOKUP_NO_NUMBERS,
316 printf(" (prog-if %02x", c);
326 get_subid(struct device *d, word *subvp, word *subdp)
328 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
330 if (htype == PCI_HEADER_TYPE_NORMAL)
332 *subvp = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
333 *subdp = get_conf_word(d, PCI_SUBSYSTEM_ID);
335 else if (htype == PCI_HEADER_TYPE_CARDBUS && d->config_cached >= 128)
337 *subvp = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
338 *subdp = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
341 *subvp = *subdp = 0xffff;
344 /*** Capabilities ***/
347 cap_pm(struct device *d, int where, int cap)
350 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
352 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
355 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
356 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
357 FLAG(cap, PCI_PM_CAP_DSI),
358 FLAG(cap, PCI_PM_CAP_D1),
359 FLAG(cap, PCI_PM_CAP_D2),
360 pm_aux_current[(cap >> 6) & 7],
361 FLAG(cap, PCI_PM_CAP_PME_D0),
362 FLAG(cap, PCI_PM_CAP_PME_D1),
363 FLAG(cap, PCI_PM_CAP_PME_D2),
364 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
365 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
366 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
368 t = get_conf_word(d, where + PCI_PM_CTRL);
369 printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
370 t & PCI_PM_CTRL_STATE_MASK,
371 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
372 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
373 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
374 FLAG(t, PCI_PM_CTRL_PME_STATUS));
375 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
377 printf("\t\tBridge: PM%c B3%c\n",
378 FLAG(t, PCI_PM_BPCC_ENABLE),
379 FLAG(~t, PCI_PM_PPB_B2_B3));
383 format_agp_rate(int rate, char *buf, int agp3)
393 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
398 strcpy(buf, "<none>");
402 cap_agp(struct device *d, int where, int cap)
409 ver = (cap >> 4) & 0x0f;
411 printf("AGP version %x.%x\n", ver, rev);
414 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
416 t = get_conf_long(d, where + PCI_AGP_STATUS);
417 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
419 format_agp_rate(t & 7, rate, agp3);
420 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
421 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
422 FLAG(t, PCI_AGP_STATUS_ISOCH),
423 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
424 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
425 FLAG(t, PCI_AGP_STATUS_SBA),
426 FLAG(t, PCI_AGP_STATUS_ITA_COH),
427 FLAG(t, PCI_AGP_STATUS_GART64),
428 FLAG(t, PCI_AGP_STATUS_HTRANS),
429 FLAG(t, PCI_AGP_STATUS_64BIT),
430 FLAG(t, PCI_AGP_STATUS_FW),
431 FLAG(t, PCI_AGP_STATUS_AGP3),
433 t = get_conf_long(d, where + PCI_AGP_COMMAND);
434 format_agp_rate(t & 7, rate, agp3);
435 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
436 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
437 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
438 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
439 FLAG(t, PCI_AGP_COMMAND_SBA),
440 FLAG(t, PCI_AGP_COMMAND_AGP),
441 FLAG(t, PCI_AGP_COMMAND_GART64),
442 FLAG(t, PCI_AGP_COMMAND_64BIT),
443 FLAG(t, PCI_AGP_COMMAND_FW),
448 cap_pcix_nobridge(struct device *d, int where)
452 static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
454 printf("PCI-X non-bridge device\n");
459 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
462 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
463 status = get_conf_long(d, where + PCI_PCIX_STATUS);
464 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
465 FLAG(command, PCI_PCIX_COMMAND_DPERE),
466 FLAG(command, PCI_PCIX_COMMAND_ERO),
467 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
468 max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
469 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
470 ((status >> 8) & 0xff),
471 ((status >> 3) & 0x1f),
472 (status & PCI_PCIX_STATUS_FUNCTION),
473 FLAG(status, PCI_PCIX_STATUS_64BIT),
474 FLAG(status, PCI_PCIX_STATUS_133MHZ),
475 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
476 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
477 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
478 1 << (9 + ((status >> 21) & 3U)),
479 max_outstanding[(status >> 23) & 7U],
480 1 << (3 + ((status >> 26) & 7U)),
481 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
482 FLAG(status, PCI_PCIX_STATUS_266MHZ),
483 FLAG(status, PCI_PCIX_STATUS_533MHZ));
487 cap_pcix_bridge(struct device *d, int where)
489 static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
491 u32 status, upstcr, downstcr;
493 printf("PCI-X bridge device\n");
498 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
501 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
502 printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
503 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
504 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
505 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
506 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
507 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
508 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
509 sec_clock_freq[(secstatus >> 6) & 7]);
510 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
511 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
512 ((status >> 8) & 0xff),
513 ((status >> 3) & 0x1f),
514 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
515 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
516 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
517 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
518 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
519 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
520 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
521 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
522 printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
523 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
524 (upstcr >> 16) & 0xffff);
525 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
526 printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
527 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
528 (downstcr >> 16) & 0xffff);
532 cap_pcix(struct device *d, int where)
534 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
536 case PCI_HEADER_TYPE_NORMAL:
537 cap_pcix_nobridge(d, where);
539 case PCI_HEADER_TYPE_BRIDGE:
540 cap_pcix_bridge(d, where);
546 ht_link_width(unsigned width)
548 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
549 return widths[width];
553 ht_link_freq(unsigned freq)
555 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
556 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
561 cap_ht_pri(struct device *d, int where, int cmd)
563 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
564 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
567 printf("HyperTransport: Slave or Primary Interface\n");
571 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
573 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
574 if (rid < 0x23 && rid > 0x11)
575 printf("\t\t!!! Possibly incomplete decoding\n");
578 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
580 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
582 (cmd & PCI_HT_PRI_CMD_BUID),
583 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
584 FLAG(cmd, PCI_HT_PRI_CMD_MH),
585 FLAG(cmd, PCI_HT_PRI_CMD_DD),
586 FLAG(cmd, PCI_HT_PRI_CMD_DUL));
587 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
589 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
591 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
593 FLAG(lctr0, PCI_HT_LCTR_CFLE),
594 FLAG(lctr0, PCI_HT_LCTR_CST),
595 FLAG(lctr0, PCI_HT_LCTR_CFE),
596 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
597 FLAG(lctr0, PCI_HT_LCTR_INIT),
598 FLAG(lctr0, PCI_HT_LCTR_EOC),
599 FLAG(lctr0, PCI_HT_LCTR_TXO),
600 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
601 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
602 FLAG(lctr0, PCI_HT_LCTR_LSEN),
603 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
604 FLAG(lctr0, PCI_HT_LCTR_64B));
605 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
607 fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
609 fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
611 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
612 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
613 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
614 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
615 FLAG(lcnf0, PCI_HT_LCNF_DFI),
616 FLAG(lcnf0, PCI_HT_LCNF_DFO),
617 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
618 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
619 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
621 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
623 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
625 FLAG(lctr1, PCI_HT_LCTR_CFLE),
626 FLAG(lctr1, PCI_HT_LCTR_CST),
627 FLAG(lctr1, PCI_HT_LCTR_CFE),
628 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
629 FLAG(lctr1, PCI_HT_LCTR_INIT),
630 FLAG(lctr1, PCI_HT_LCTR_EOC),
631 FLAG(lctr1, PCI_HT_LCTR_TXO),
632 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
633 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
634 FLAG(lctr1, PCI_HT_LCTR_LSEN),
635 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
636 FLAG(lctr1, PCI_HT_LCTR_64B));
637 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
639 fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
641 fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
643 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
644 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
645 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
646 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
647 FLAG(lcnf1, PCI_HT_LCNF_DFI),
648 FLAG(lcnf1, PCI_HT_LCNF_DFO),
649 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
650 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
651 printf("\t\tRevision ID: %u.%02u\n",
652 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
655 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
656 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
657 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
658 FLAG(lfrer0, PCI_HT_LFRER_PROT),
659 FLAG(lfrer0, PCI_HT_LFRER_OV),
660 FLAG(lfrer0, PCI_HT_LFRER_EOC),
661 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
662 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
663 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
664 FLAG(lfcap0, PCI_HT_LFCAP_200),
665 FLAG(lfcap0, PCI_HT_LFCAP_300),
666 FLAG(lfcap0, PCI_HT_LFCAP_400),
667 FLAG(lfcap0, PCI_HT_LFCAP_500),
668 FLAG(lfcap0, PCI_HT_LFCAP_600),
669 FLAG(lfcap0, PCI_HT_LFCAP_800),
670 FLAG(lfcap0, PCI_HT_LFCAP_1000),
671 FLAG(lfcap0, PCI_HT_LFCAP_1200),
672 FLAG(lfcap0, PCI_HT_LFCAP_1400),
673 FLAG(lfcap0, PCI_HT_LFCAP_1600),
674 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
675 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
676 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
677 FLAG(ftr, PCI_HT_FTR_ISOCFC),
678 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
679 FLAG(ftr, PCI_HT_FTR_CRCTM),
680 FLAG(ftr, PCI_HT_FTR_ECTLT),
681 FLAG(ftr, PCI_HT_FTR_64BA),
682 FLAG(ftr, PCI_HT_FTR_UIDRD));
683 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
684 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
685 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
686 FLAG(lfrer1, PCI_HT_LFRER_PROT),
687 FLAG(lfrer1, PCI_HT_LFRER_OV),
688 FLAG(lfrer1, PCI_HT_LFRER_EOC),
689 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
690 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
691 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
692 FLAG(lfcap1, PCI_HT_LFCAP_200),
693 FLAG(lfcap1, PCI_HT_LFCAP_300),
694 FLAG(lfcap1, PCI_HT_LFCAP_400),
695 FLAG(lfcap1, PCI_HT_LFCAP_500),
696 FLAG(lfcap1, PCI_HT_LFCAP_600),
697 FLAG(lfcap1, PCI_HT_LFCAP_800),
698 FLAG(lfcap1, PCI_HT_LFCAP_1000),
699 FLAG(lfcap1, PCI_HT_LFCAP_1200),
700 FLAG(lfcap1, PCI_HT_LFCAP_1400),
701 FLAG(lfcap1, PCI_HT_LFCAP_1600),
702 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
703 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
704 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
705 FLAG(eh, PCI_HT_EH_PFLE),
706 FLAG(eh, PCI_HT_EH_OFLE),
707 FLAG(eh, PCI_HT_EH_PFE),
708 FLAG(eh, PCI_HT_EH_OFE),
709 FLAG(eh, PCI_HT_EH_EOCFE),
710 FLAG(eh, PCI_HT_EH_RFE),
711 FLAG(eh, PCI_HT_EH_CRCFE),
712 FLAG(eh, PCI_HT_EH_SERRFE),
713 FLAG(eh, PCI_HT_EH_CF),
714 FLAG(eh, PCI_HT_EH_RE),
715 FLAG(eh, PCI_HT_EH_PNFE),
716 FLAG(eh, PCI_HT_EH_ONFE),
717 FLAG(eh, PCI_HT_EH_EOCNFE),
718 FLAG(eh, PCI_HT_EH_RNFE),
719 FLAG(eh, PCI_HT_EH_CRCNFE),
720 FLAG(eh, PCI_HT_EH_SERRNFE));
721 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
722 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
723 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
724 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
725 printf("\t\tBus Number: %02x\n", bn);
729 cap_ht_sec(struct device *d, int where, int cmd)
731 u16 lctr, lcnf, ftr, eh;
732 u8 rid, lfrer, lfcap, mbu, mlu;
735 printf("HyperTransport: Host or Secondary Interface\n");
739 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
741 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
742 if (rid < 0x23 && rid > 0x11)
743 printf("\t\t!!! Possibly incomplete decoding\n");
746 fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
748 fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
750 FLAG(cmd, PCI_HT_SEC_CMD_WR),
751 FLAG(cmd, PCI_HT_SEC_CMD_DE),
752 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
753 FLAG(cmd, PCI_HT_SEC_CMD_CS),
754 FLAG(cmd, PCI_HT_SEC_CMD_HH),
755 FLAG(cmd, PCI_HT_SEC_CMD_AS),
756 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
757 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
758 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
760 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
762 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
764 FLAG(lctr, PCI_HT_LCTR_CFLE),
765 FLAG(lctr, PCI_HT_LCTR_CST),
766 FLAG(lctr, PCI_HT_LCTR_CFE),
767 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
768 FLAG(lctr, PCI_HT_LCTR_INIT),
769 FLAG(lctr, PCI_HT_LCTR_EOC),
770 FLAG(lctr, PCI_HT_LCTR_TXO),
771 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
772 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
773 FLAG(lctr, PCI_HT_LCTR_LSEN),
774 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
775 FLAG(lctr, PCI_HT_LCTR_64B));
776 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
778 fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
780 fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
782 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
783 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
784 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
785 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
786 FLAG(lcnf, PCI_HT_LCNF_DFI),
787 FLAG(lcnf, PCI_HT_LCNF_DFO),
788 FLAG(lcnf, PCI_HT_LCNF_DFIE),
789 FLAG(lcnf, PCI_HT_LCNF_DFOE));
790 printf("\t\tRevision ID: %u.%02u\n",
791 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
794 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
795 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
796 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
797 FLAG(lfrer, PCI_HT_LFRER_PROT),
798 FLAG(lfrer, PCI_HT_LFRER_OV),
799 FLAG(lfrer, PCI_HT_LFRER_EOC),
800 FLAG(lfrer, PCI_HT_LFRER_CTLT));
801 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
802 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
803 FLAG(lfcap, PCI_HT_LFCAP_200),
804 FLAG(lfcap, PCI_HT_LFCAP_300),
805 FLAG(lfcap, PCI_HT_LFCAP_400),
806 FLAG(lfcap, PCI_HT_LFCAP_500),
807 FLAG(lfcap, PCI_HT_LFCAP_600),
808 FLAG(lfcap, PCI_HT_LFCAP_800),
809 FLAG(lfcap, PCI_HT_LFCAP_1000),
810 FLAG(lfcap, PCI_HT_LFCAP_1200),
811 FLAG(lfcap, PCI_HT_LFCAP_1400),
812 FLAG(lfcap, PCI_HT_LFCAP_1600),
813 FLAG(lfcap, PCI_HT_LFCAP_VEND));
814 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
815 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
816 FLAG(ftr, PCI_HT_FTR_ISOCFC),
817 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
818 FLAG(ftr, PCI_HT_FTR_CRCTM),
819 FLAG(ftr, PCI_HT_FTR_ECTLT),
820 FLAG(ftr, PCI_HT_FTR_64BA),
821 FLAG(ftr, PCI_HT_FTR_UIDRD),
822 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
823 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
824 if (ftr & PCI_HT_SEC_FTR_EXTRS)
826 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
827 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
828 FLAG(eh, PCI_HT_EH_PFLE),
829 FLAG(eh, PCI_HT_EH_OFLE),
830 FLAG(eh, PCI_HT_EH_PFE),
831 FLAG(eh, PCI_HT_EH_OFE),
832 FLAG(eh, PCI_HT_EH_EOCFE),
833 FLAG(eh, PCI_HT_EH_RFE),
834 FLAG(eh, PCI_HT_EH_CRCFE),
835 FLAG(eh, PCI_HT_EH_SERRFE),
836 FLAG(eh, PCI_HT_EH_CF),
837 FLAG(eh, PCI_HT_EH_RE),
838 FLAG(eh, PCI_HT_EH_PNFE),
839 FLAG(eh, PCI_HT_EH_ONFE),
840 FLAG(eh, PCI_HT_EH_EOCNFE),
841 FLAG(eh, PCI_HT_EH_RNFE),
842 FLAG(eh, PCI_HT_EH_CRCNFE),
843 FLAG(eh, PCI_HT_EH_SERRNFE));
844 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
845 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
846 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
851 cap_ht(struct device *d, int where, int cmd)
855 switch (cmd & PCI_HT_CMD_TYP_HI)
857 case PCI_HT_CMD_TYP_HI_PRI:
858 cap_ht_pri(d, where, cmd);
860 case PCI_HT_CMD_TYP_HI_SEC:
861 cap_ht_sec(d, where, cmd);
865 type = cmd & PCI_HT_CMD_TYP;
868 case PCI_HT_CMD_TYP_SW:
869 printf("HyperTransport: Switch\n");
871 case PCI_HT_CMD_TYP_IDC:
872 printf("HyperTransport: Interrupt Discovery and Configuration\n");
874 case PCI_HT_CMD_TYP_RID:
875 printf("HyperTransport: Revision ID: %u.%02u\n",
876 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
878 case PCI_HT_CMD_TYP_UIDC:
879 printf("HyperTransport: UnitID Clumping\n");
881 case PCI_HT_CMD_TYP_ECSA:
882 printf("HyperTransport: Extended Configuration Space Access\n");
884 case PCI_HT_CMD_TYP_AM:
885 printf("HyperTransport: Address Mapping\n");
887 case PCI_HT_CMD_TYP_MSIM:
888 printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
889 FLAG(cmd, PCI_HT_MSIM_CMD_EN),
890 FLAG(cmd, PCI_HT_MSIM_CMD_FIXD));
891 if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD))
894 if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8))
896 offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
897 offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
898 printf("\t\tMapping Address Base: %016llx\n", ((unsigned long long)offh << 32) | (offl & ~0xfffff));
901 case PCI_HT_CMD_TYP_DR:
902 printf("HyperTransport: DirectRoute\n");
904 case PCI_HT_CMD_TYP_VCS:
905 printf("HyperTransport: VCSet\n");
907 case PCI_HT_CMD_TYP_RM:
908 printf("HyperTransport: Retry Mode\n");
910 case PCI_HT_CMD_TYP_X86:
911 printf("HyperTransport: X86 (reserved)\n");
914 printf("HyperTransport: #%02x\n", type >> 11);
919 cap_msi(struct device *d, int where, int cap)
925 printf("Message Signalled Interrupts: Mask%c 64bit%c Queue=%d/%d Enable%c\n",
926 FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
927 FLAG(cap, PCI_MSI_FLAGS_64BIT),
928 (cap & PCI_MSI_FLAGS_QSIZE) >> 4,
929 (cap & PCI_MSI_FLAGS_QMASK) >> 1,
930 FLAG(cap, PCI_MSI_FLAGS_ENABLE));
933 is64 = cap & PCI_MSI_FLAGS_64BIT;
934 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
936 printf("\t\tAddress: ");
939 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
940 w = get_conf_word(d, where + PCI_MSI_DATA_64);
944 w = get_conf_word(d, where + PCI_MSI_DATA_32);
945 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
946 printf("%08x Data: %04x\n", t, w);
947 if (cap & PCI_MSI_FLAGS_MASK_BIT)
953 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
955 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
956 pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
960 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
962 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
963 pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
965 printf("\t\tMasking: %08x Pending: %08x\n", mask, pending);
969 static float power_limit(int value, int scale)
971 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
972 return value * scales[scale];
975 static const char *latency_l0s(int value)
977 static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
978 return latencies[value];
981 static const char *latency_l1(int value)
983 static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
984 return latencies[value];
987 static void cap_express_dev(struct device *d, int where, int type)
992 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
993 printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d, Latency L0s %s, L1 %s\n",
994 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
995 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
996 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
997 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
998 printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
999 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
1000 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
1001 printf(" AttnBtn%c AttnInd%c PwrInd%c",
1002 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
1003 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
1004 printf(" RBE%c FLReset%c",
1005 FLAG(t, PCI_EXP_DEVCAP_RBE),
1006 FLAG(t, PCI_EXP_DEVCAP_FLRESET));
1007 if (type == PCI_EXP_TYPE_UPSTREAM)
1008 printf("SlotPowerLimit %fW",
1009 power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
1010 (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
1013 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
1014 printf("\t\tDevCtl:\tReport errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
1015 FLAG(w, PCI_EXP_DEVCTL_CERE),
1016 FLAG(w, PCI_EXP_DEVCTL_NFERE),
1017 FLAG(w, PCI_EXP_DEVCTL_FERE),
1018 FLAG(w, PCI_EXP_DEVCTL_URRE));
1019 printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
1020 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
1021 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
1022 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
1023 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
1024 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
1025 if (type == PCI_EXP_TYPE_PCI_BRIDGE || type == PCI_EXP_TYPE_PCIE_BRIDGE)
1026 printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
1027 if (type == PCI_EXP_TYPE_ENDPOINT && (t & PCI_EXP_DEVCAP_FLRESET))
1028 printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
1029 printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
1030 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
1031 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
1033 w = get_conf_word(d, where + PCI_EXP_DEVSTA);
1034 printf("\t\tDevSta:\tCorrErr%c UncorrErr%c FatalErr%c UnsuppReq%c AuxPwr%c TransPend%c\n",
1035 FLAG(w, PCI_EXP_DEVSTA_CED),
1036 FLAG(w, PCI_EXP_DEVSTA_NFED),
1037 FLAG(w, PCI_EXP_DEVSTA_FED),
1038 FLAG(w, PCI_EXP_DEVSTA_URD),
1039 FLAG(w, PCI_EXP_DEVSTA_AUXPD),
1040 FLAG(w, PCI_EXP_DEVSTA_TRPND));
1043 static char *link_speed(int speed)
1056 static char *aspm_support(int code)
1069 static const char *aspm_enabled(int code)
1071 static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
1075 static void cap_express_link(struct device *d, int where, int type)
1080 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
1081 printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s, Latency L0 %s, L1 %s\n",
1083 link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
1084 aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
1085 latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
1086 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
1087 printf("\t\t\tClockPM%c Suprise%c LLActRep%c BwNot%c\n",
1088 FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
1089 FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
1090 FLAG(t, PCI_EXP_LNKCAP_DLLA),
1091 FLAG(t, PCI_EXP_LNKCAP_LBNC));
1093 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
1094 printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
1095 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
1096 (type == PCI_EXP_TYPE_LEG_END))
1097 printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
1098 printf(" Disabled%c Retrain%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
1099 FLAG(w, PCI_EXP_LNKCTL_DISABLE),
1100 FLAG(w, PCI_EXP_LNKCTL_RETRAIN),
1101 FLAG(w, PCI_EXP_LNKCTL_CLOCK),
1102 FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
1103 FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
1104 FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
1105 FLAG(w, PCI_EXP_LNKCTL_BWMIE),
1106 FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
1108 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
1109 printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
1110 link_speed(w & PCI_EXP_LNKSTA_SPEED),
1111 (w & PCI_EXP_LNKSTA_WIDTH) >> 4,
1112 FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
1113 FLAG(w, PCI_EXP_LNKSTA_TRAIN),
1114 FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
1115 FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
1116 FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
1117 FLAG(w, PCI_EXP_LNKSTA_AUTBW));
1120 static const char *indicator(int code)
1122 static const char *names[] = { "Unknown", "On", "Blink", "Off" };
1126 static void cap_express_slot(struct device *d, int where)
1131 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
1132 printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surpise%c\n",
1133 FLAG(t, PCI_EXP_SLTCAP_ATNB),
1134 FLAG(t, PCI_EXP_SLTCAP_PWRC),
1135 FLAG(t, PCI_EXP_SLTCAP_MRL),
1136 FLAG(t, PCI_EXP_SLTCAP_ATNI),
1137 FLAG(t, PCI_EXP_SLTCAP_PWRI),
1138 FLAG(t, PCI_EXP_SLTCAP_HPC),
1139 FLAG(t, PCI_EXP_SLTCAP_HPS));
1140 printf("\t\t\tSlot #%3x, PowerLimit %f; Interlock%c NoCompl%c\n",
1142 power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
1143 FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
1144 FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
1146 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
1147 printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
1148 FLAG(w, PCI_EXP_SLTCTL_ATNB),
1149 FLAG(w, PCI_EXP_SLTCTL_PWRF),
1150 FLAG(w, PCI_EXP_SLTCTL_MRLS),
1151 FLAG(w, PCI_EXP_SLTCTL_PRSD),
1152 FLAG(w, PCI_EXP_SLTCTL_CMDC),
1153 FLAG(w, PCI_EXP_SLTCTL_HPIE),
1154 FLAG(w, PCI_EXP_SLTCTL_LLCHG));
1155 printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
1156 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
1157 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
1158 FLAG(w, PCI_EXP_SLTCTL_PWRC),
1159 FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
1161 w = get_conf_word(d, where + PCI_EXP_SLTSTA);
1162 printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
1163 FLAG(w, PCI_EXP_SLTSTA_ATNB),
1164 FLAG(w, PCI_EXP_SLTSTA_PWRF),
1165 FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
1166 FLAG(w, PCI_EXP_SLTSTA_CMDC),
1167 FLAG(w, PCI_EXP_SLTSTA_PRES),
1168 FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
1169 printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
1170 FLAG(w, PCI_EXP_SLTSTA_MRLS),
1171 FLAG(w, PCI_EXP_SLTSTA_PRSD),
1172 FLAG(w, PCI_EXP_SLTSTA_LLCHG));
1175 static void cap_express_root(struct device *d, int where)
1177 u32 w = get_conf_word(d, where + PCI_EXP_RTCTL);
1178 printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
1179 FLAG(w, PCI_EXP_RTCTL_SECEE),
1180 FLAG(w, PCI_EXP_RTCTL_SENFEE),
1181 FLAG(w, PCI_EXP_RTCTL_SEFEE),
1182 FLAG(w, PCI_EXP_RTCTL_PMEIE),
1183 FLAG(w, PCI_EXP_RTCTL_CRSVIS));
1185 w = get_conf_word(d, where + PCI_EXP_RTCAP);
1186 printf("\t\tRootCap: CRSVisible%c\n",
1187 FLAG(w, PCI_EXP_RTCAP_CRSVIS));
1189 w = get_conf_word(d, where + PCI_EXP_RTSTA);
1190 printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
1191 w & PCI_EXP_RTSTA_PME_REQID,
1192 FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
1193 FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
1196 static const char *cap_express_dev2_timeout_range(int type)
1198 /* Decode Completion Timeout Ranges. */
1202 return "Not Supported";
1216 return "Range ABCD";
1222 static const char *cap_express_dev2_timeout_value(int type)
1224 /* Decode Completion Timeout Value. */
1228 return "50us to 50ms";
1230 return "50us to 100us";
1232 return "1ms to 10ms";
1234 return "16ms to 55ms";
1236 return "65ms to 210ms";
1238 return "260ms to 900ms";
1240 return "1s to 3.5s";
1244 return "17s to 64s";
1250 static void cap_express_dev2(struct device *d, int where, int type)
1255 l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
1256 printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c",
1257 cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)),
1258 FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS));
1259 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1260 printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEV2_ARI));
1264 w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
1265 printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c",
1266 cap_express_dev2_timeout_value(PCI_EXP_DEV2_TIMEOUT_VALUE(w)),
1267 FLAG(w, PCI_EXP_DEV2_TIMEOUT_DIS));
1268 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1269 printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEV2_ARI));
1274 static const char *cap_express_link2_speed(int type)
1278 case 0: /* hardwire to 0 means only the 2.5GT/s is supported */
1288 static const char *cap_express_link2_deemphasis(int type)
1301 static const char *cap_express_link2_transmargin(int type)
1306 return "Normal Operating Range";
1308 return "800-1200mV(full-swing)/400-700mV(half-swing)";
1313 return "200-400mV(full-swing)/100-200mV(half-swing)";
1319 static void cap_express_link2(struct device *d, int where, int type UNUSED)
1323 w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
1324 printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c, Selectable De-emphasis: %s\n"
1325 "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
1326 "\t\t\t Compliance De-emphasis: %s\n",
1327 cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)),
1328 FLAG(w, PCI_EXP_LNKCTL2_CMPLNC),
1329 FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS),
1330 cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)),
1331 cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)),
1332 FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC),
1333 FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS),
1334 cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w)));
1336 w = get_conf_word(d, where + PCI_EXP_LNKSTA2);
1337 printf("\t\tLnkSta2: Current De-emphasis Level: %s\n",
1338 cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)));
1341 static void cap_express_slot2(struct device *d UNUSED, int where UNUSED)
1343 /* No capabilities that require this field in PCIe rev2.0 spec. */
1347 cap_express(struct device *d, int where, int cap)
1349 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1355 printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
1358 case PCI_EXP_TYPE_ENDPOINT:
1361 case PCI_EXP_TYPE_LEG_END:
1362 printf("Legacy Endpoint");
1364 case PCI_EXP_TYPE_ROOT_PORT:
1365 slot = cap & PCI_EXP_FLAGS_SLOT;
1366 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1368 case PCI_EXP_TYPE_UPSTREAM:
1369 printf("Upstream Port");
1371 case PCI_EXP_TYPE_DOWNSTREAM:
1372 slot = cap & PCI_EXP_FLAGS_SLOT;
1373 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1375 case PCI_EXP_TYPE_PCI_BRIDGE:
1376 printf("PCI/PCI-X Bridge");
1378 case PCI_EXP_TYPE_PCIE_BRIDGE:
1379 printf("PCI/PCI-X to PCI-Express Bridge");
1381 case PCI_EXP_TYPE_ROOT_INT_EP:
1382 printf("Root Complex Integrated Endpoint");
1384 case PCI_EXP_TYPE_ROOT_EC:
1385 printf("Root Complex Event Collector");
1388 printf("Unknown type %d", type);
1390 printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1397 if (type == PCI_EXP_TYPE_ROOT_PORT)
1399 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1402 cap_express_dev(d, where, type);
1403 cap_express_link(d, where, type);
1405 cap_express_slot(d, where);
1406 if (type == PCI_EXP_TYPE_ROOT_PORT)
1407 cap_express_root(d, where);
1409 if ((cap & PCI_EXP_FLAGS_VERS) < 2)
1415 if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size))
1418 cap_express_dev2(d, where, type);
1419 cap_express_link2(d, where, type);
1421 cap_express_slot2(d, where);
1425 cap_msix(struct device *d, int where, int cap)
1429 printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
1430 FLAG(cap, PCI_MSIX_ENABLE),
1431 FLAG(cap, PCI_MSIX_MASK),
1432 (cap & PCI_MSIX_TABSIZE) + 1);
1433 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1436 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1437 printf("\t\tVector table: BAR=%d offset=%08x\n",
1438 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1439 off = get_conf_long(d, where + PCI_MSIX_PBA);
1440 printf("\t\tPBA: BAR=%d offset=%08x\n",
1441 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1447 int esr = cap & 0xff;
1450 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1451 esr & PCI_SID_ESR_NSLOTS,
1452 FLAG(esr, PCI_SID_ESR_FIC),
1457 cap_ssvid(struct device *d, int where)
1459 u16 subsys_v, subsys_d;
1460 char ssnamebuf[256];
1462 if (!config_fetch(d, where, 8))
1464 subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR);
1465 subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE);
1466 printf("Subsystem: %s\n",
1467 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1468 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1469 d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
1473 cap_dsn(struct device *d, int where)
1476 if (!config_fetch(d, where + 4, 8))
1478 t1 = get_conf_long(d, where + 4);
1479 t2 = get_conf_long(d, where + 8);
1480 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
1481 t1 & 0xff, (t1 >> 8) & 0xff, (t1 >> 16) & 0xff, t1 >> 24,
1482 t2 & 0xff, (t2 >> 8) & 0xff, (t2 >> 16) & 0xff, t2 >> 24);
1486 cap_debug_port(int cap)
1488 int bar = cap >> 13;
1489 int pos = cap & 0x1fff;
1490 printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
1494 cap_aer(struct device *d, int where)
1498 printf("Advanced Error Reporting\n");
1499 if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 24))
1502 l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS);
1503 printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
1504 "MalfTLP%c ECRC%c UnsupReq%c ACSVoil%c\n",
1505 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
1506 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
1507 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
1508 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
1509 l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK);
1510 printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
1511 "MalfTLP%c ECRC%c UnsupReq%c ACSVoil%c\n",
1512 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
1513 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
1514 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
1515 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
1516 l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER);
1517 printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
1518 "MalfTLP%c ECRC%c UnsupReq%c ACSVoil%c\n",
1519 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
1520 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
1521 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
1522 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
1523 l = get_conf_long(d, where + PCI_ERR_COR_STATUS);
1524 printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n",
1525 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
1526 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
1527 l = get_conf_long(d, where + PCI_ERR_COR_MASK);
1528 printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n",
1529 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
1530 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
1531 l = get_conf_long(d, where + PCI_ERR_CAP);
1532 printf("\t\tAERCap:\tFirst Error Pointer: %02x, GenCap%c CGenEn%c ChkCap%c ChkEn%c\n",
1533 PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE),
1534 FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE));
1539 cap_acs(struct device *d, int where)
1543 printf("Access Control Services\n");
1544 if (!config_fetch(d, where + PCI_ACS_CAP, 4))
1547 w = get_conf_word(d, where + PCI_ACS_CAP);
1548 printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
1550 FLAG(w, PCI_ACS_CAP_VALID), FLAG(w, PCI_ACS_CAP_BLOCK), FLAG(w, PCI_ACS_CAP_REQ_RED),
1551 FLAG(w, PCI_ACS_CAP_CMPLT_RED), FLAG(w, PCI_ACS_CAP_FORWARD), FLAG(w, PCI_ACS_CAP_EGRESS),
1552 FLAG(w, PCI_ACS_CAP_TRANS));
1553 w = get_conf_word(d, where + PCI_ACS_CTRL);
1554 printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
1556 FLAG(w, PCI_ACS_CTRL_VALID), FLAG(w, PCI_ACS_CTRL_BLOCK), FLAG(w, PCI_ACS_CTRL_REQ_RED),
1557 FLAG(w, PCI_ACS_CTRL_CMPLT_RED), FLAG(w, PCI_ACS_CTRL_FORWARD), FLAG(w, PCI_ACS_CTRL_EGRESS),
1558 FLAG(w, PCI_ACS_CTRL_TRANS));
1562 show_ext_caps(struct device *d)
1565 char been_there[0x1000];
1566 memset(been_there, 0, 0x1000);
1572 if (!config_fetch(d, where, 4))
1574 header = get_conf_long(d, where);
1577 id = header & 0xffff;
1578 printf("\tCapabilities: [%03x] ", where);
1579 if (been_there[where]++)
1581 printf("<chain looped>\n");
1586 case PCI_EXT_CAP_ID_AER:
1589 case PCI_EXT_CAP_ID_VC:
1590 printf("Virtual Channel <?>\n");
1592 case PCI_EXT_CAP_ID_DSN:
1595 case PCI_EXT_CAP_ID_PB:
1596 printf("Power Budgeting <?>\n");
1598 case PCI_EXT_CAP_ID_RCLINK:
1599 printf("Root Complex Link <?>\n");
1601 case PCI_EXT_CAP_ID_RCILINK:
1602 printf("Root Complex Internal Link <?>\n");
1604 case PCI_EXT_CAP_ID_RCECOLL:
1605 printf("Root Complex Event Collector <?>\n");
1607 case PCI_EXT_CAP_ID_MFVC:
1608 printf("Multi-Function Virtual Channel <?>\n");
1610 case PCI_EXT_CAP_ID_RBCB:
1611 printf("Root Bridge Control Block <?>\n");
1613 case PCI_EXT_CAP_ID_VNDR:
1614 printf("Vendor Specific Information <?>\n");
1616 case PCI_EXT_CAP_ID_ACS:
1620 printf("#%02x\n", id);
1623 where = header >> 20;
1628 show_caps(struct device *d)
1630 int can_have_ext_caps = 0;
1632 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1634 int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
1635 byte been_there[256];
1636 memset(been_there, 0, 256);
1640 printf("\tCapabilities: ");
1641 if (!config_fetch(d, where, 4))
1643 puts("<access denied>");
1646 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1647 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1648 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1649 printf("[%02x] ", where);
1650 if (been_there[where]++)
1652 printf("<chain looped>\n");
1657 printf("<chain broken>\n");
1663 cap_pm(d, where, cap);
1665 case PCI_CAP_ID_AGP:
1666 cap_agp(d, where, cap);
1668 case PCI_CAP_ID_VPD:
1669 printf("Vital Product Data <?>\n");
1671 case PCI_CAP_ID_SLOTID:
1674 case PCI_CAP_ID_MSI:
1675 cap_msi(d, where, cap);
1677 case PCI_CAP_ID_CHSWP:
1678 printf("CompactPCI hot-swap <?>\n");
1680 case PCI_CAP_ID_PCIX:
1682 can_have_ext_caps = 1;
1685 cap_ht(d, where, cap);
1687 case PCI_CAP_ID_VNDR:
1688 printf("Vendor Specific Information <?>\n");
1690 case PCI_CAP_ID_DBG:
1691 cap_debug_port(cap);
1693 case PCI_CAP_ID_CCRC:
1694 printf("CompactPCI central resource control <?>\n");
1696 case PCI_CAP_ID_HOTPLUG:
1697 printf("Hot-plug capable\n");
1699 case PCI_CAP_ID_SSVID:
1700 cap_ssvid(d, where);
1702 case PCI_CAP_ID_AGP3:
1703 printf("AGP3 <?>\n");
1705 case PCI_CAP_ID_SECURE:
1706 printf("Secure device <?>\n");
1708 case PCI_CAP_ID_EXP:
1709 cap_express(d, where, cap);
1710 can_have_ext_caps = 1;
1712 case PCI_CAP_ID_MSIX:
1713 cap_msix(d, where, cap);
1715 case PCI_CAP_ID_SATA:
1716 printf("SATA HBA <?>\n");
1719 printf("PCIe advanced features <?>\n");
1722 printf("#%02x [%04x]\n", id, cap);
1727 if (can_have_ext_caps)
1731 /*** Kernel drivers ***/
1735 #include <sys/utsname.h>
1737 struct pcimap_entry {
1738 struct pcimap_entry *next;
1739 unsigned int vendor, device;
1740 unsigned int subvendor, subdevice;
1741 unsigned int class, class_mask;
1745 static struct pcimap_entry *pcimap_head;
1750 static int tried_pcimap;
1752 char *name, line[1024];
1759 if (name = opt_pcimap)
1761 f = fopen(name, "r");
1763 die("Cannot open pcimap file %s: %m", name);
1767 if (uname(&uts) < 0)
1768 die("uname() failed: %m");
1769 name = alloca(64 + strlen(uts.release));
1770 sprintf(name, "/lib/modules/%s/modules.pcimap", uts.release);
1771 f = fopen(name, "r");
1776 while (fgets(line, sizeof(line), f))
1778 char *c = strchr(line, '\n');
1779 struct pcimap_entry *e;
1782 die("Unterminated or too long line in %s", name);
1784 if (!line[0] || line[0] == '#')
1788 while (*c && *c != ' ' && *c != '\t')
1791 continue; /* FIXME: Emit warnings! */
1794 e = xmalloc(sizeof(*e) + strlen(line));
1795 if (sscanf(c, "%i%i%i%i%i%i",
1796 &e->vendor, &e->device,
1797 &e->subvendor, &e->subdevice,
1798 &e->class, &e->class_mask) != 6)
1800 e->next = pcimap_head;
1802 strcpy(e->module, line);
1808 match_pcimap(struct device *d, struct pcimap_entry *e)
1810 struct pci_dev *dev = d->dev;
1811 unsigned int class = get_conf_long(d, PCI_REVISION_ID) >> 8;
1814 #define MATCH(x, y) ((y) > 0xffff || (x) == (y))
1815 get_subid(d, &subv, &subd);
1817 MATCH(dev->vendor_id, e->vendor) &&
1818 MATCH(dev->device_id, e->device) &&
1819 MATCH(subv, e->subvendor) &&
1820 MATCH(subd, e->subdevice) &&
1821 (class & e->class_mask) == e->class;
1825 #define DRIVER_BUF_SIZE 1024
1828 find_driver(struct device *d, char *buf)
1830 struct pci_dev *dev = d->dev;
1831 char name[1024], *drv, *base;
1834 if (dev->access->method != PCI_ACCESS_SYS_BUS_PCI)
1837 base = pci_get_param(dev->access, "sysfs.path");
1838 if (!base || !base[0])
1841 n = snprintf(name, sizeof(name), "%s/devices/%04x:%02x:%02x.%d/driver",
1842 base, dev->domain, dev->bus, dev->dev, dev->func);
1843 if (n < 0 || n >= (int)sizeof(name))
1844 die("show_driver: sysfs device name too long, why?");
1846 n = readlink(name, buf, DRIVER_BUF_SIZE);
1849 if (n >= DRIVER_BUF_SIZE)
1850 return "<name-too-long>";
1853 if (drv = strrchr(buf, '/'))
1860 show_kernel(struct device *d)
1862 char buf[DRIVER_BUF_SIZE];
1864 struct pcimap_entry *e, *last = NULL;
1866 if (driver = find_driver(d, buf))
1867 printf("\tKernel driver in use: %s\n", driver);
1870 for (e=pcimap_head; e; e=e->next)
1871 if (match_pcimap(d, e) && (!last || strcmp(last->module, e->module)))
1873 printf("%s %s", (last ? "," : "\tKernel modules:"), e->module);
1881 show_kernel_machine(struct device *d)
1883 char buf[DRIVER_BUF_SIZE];
1885 struct pcimap_entry *e, *last = NULL;
1887 if (driver = find_driver(d, buf))
1888 printf("Driver:\t%s\n", driver);
1891 for (e=pcimap_head; e; e=e->next)
1892 if (match_pcimap(d, e) && (!last || strcmp(last->module, e->module)))
1894 printf("Module:\t%s\n", e->module);
1902 show_kernel(struct device *d UNUSED)
1907 show_kernel_machine(struct device *d UNUSED)
1913 /*** Verbose output ***/
1916 show_size(pciaddr_t x)
1922 printf("%d", (int) x);
1923 else if (x < 1048576)
1924 printf("%dK", (int)(x / 1024));
1925 else if (x < 0x80000000)
1926 printf("%dM", (int)(x / 1048576));
1928 printf(PCIADDR_T_FMT, x);
1933 show_bases(struct device *d, int cnt)
1935 struct pci_dev *p = d->dev;
1936 word cmd = get_conf_word(d, PCI_COMMAND);
1939 for(i=0; i<cnt; i++)
1941 pciaddr_t pos = p->base_addr[i];
1942 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
1943 u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
1944 if (flg == 0xffffffff)
1946 if (!pos && !flg && !len)
1949 printf("\tRegion %d: ", i);
1952 if (pos && !flg) /* Reported by the OS, but not by the device */
1954 printf("[virtual] ");
1957 if (flg & PCI_BASE_ADDRESS_SPACE_IO)
1959 pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
1960 printf("I/O ports at ");
1962 printf(PCIADDR_PORT_FMT, a);
1963 else if (flg & PCI_BASE_ADDRESS_IO_MASK)
1964 printf("<ignored>");
1966 printf("<unassigned>");
1967 if (!(cmd & PCI_COMMAND_IO))
1968 printf(" [disabled]");
1972 int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
1973 pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
1977 printf("Memory at ");
1978 if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
1982 printf("<invalid-64bit-slot>");
1988 z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
1991 u32 y = a & 0xffffffff;
1993 printf("%08x%08x", z, y);
1995 printf("<unassigned>");
2003 printf(PCIADDR_T_FMT, a);
2005 printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
2007 printf(" (%s, %sprefetchable)",
2008 (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
2009 (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
2010 (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
2011 (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
2012 if (!(cmd & PCI_COMMAND_MEMORY))
2013 printf(" [disabled]");
2021 show_rom(struct device *d, int reg)
2023 struct pci_dev *p = d->dev;
2024 pciaddr_t rom = p->rom_base_addr;
2025 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
2026 u32 flg = get_conf_long(d, reg);
2027 word cmd = get_conf_word(d, PCI_COMMAND);
2029 if (!rom && !flg && !len)
2032 if ((rom & PCI_ROM_ADDRESS_MASK) && !(flg & PCI_ROM_ADDRESS_MASK))
2034 printf("[virtual] ");
2037 printf("Expansion ROM at ");
2038 if (rom & PCI_ROM_ADDRESS_MASK)
2039 printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
2040 else if (flg & PCI_ROM_ADDRESS_MASK)
2041 printf("<ignored>");
2043 printf("<unassigned>");
2044 if (!(flg & PCI_ROM_ADDRESS_ENABLE))
2045 printf(" [disabled]");
2046 else if (!(cmd & PCI_COMMAND_MEMORY))
2047 printf(" [disabled by cmd]");
2053 show_htype0(struct device *d)
2056 show_rom(d, PCI_ROM_ADDRESS);
2061 show_htype1(struct device *d)
2063 u32 io_base = get_conf_byte(d, PCI_IO_BASE);
2064 u32 io_limit = get_conf_byte(d, PCI_IO_LIMIT);
2065 u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
2066 u32 mem_base = get_conf_word(d, PCI_MEMORY_BASE);
2067 u32 mem_limit = get_conf_word(d, PCI_MEMORY_LIMIT);
2068 u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
2069 u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE);
2070 u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT);
2071 u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
2072 word sec_stat = get_conf_word(d, PCI_SEC_STATUS);
2073 word brc = get_conf_word(d, PCI_BRIDGE_CONTROL);
2074 int verb = verbose > 2;
2077 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
2078 get_conf_byte(d, PCI_PRIMARY_BUS),
2079 get_conf_byte(d, PCI_SECONDARY_BUS),
2080 get_conf_byte(d, PCI_SUBORDINATE_BUS),
2081 get_conf_byte(d, PCI_SEC_LATENCY_TIMER));
2083 if (io_type != (io_limit & PCI_IO_RANGE_TYPE_MASK) ||
2084 (io_type != PCI_IO_RANGE_TYPE_16 && io_type != PCI_IO_RANGE_TYPE_32))
2085 printf("\t!!! Unknown I/O range types %x/%x\n", io_base, io_limit);
2088 io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
2089 io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
2090 if (io_type == PCI_IO_RANGE_TYPE_32)
2092 io_base |= (get_conf_word(d, PCI_IO_BASE_UPPER16) << 16);
2093 io_limit |= (get_conf_word(d, PCI_IO_LIMIT_UPPER16) << 16);
2095 if (io_base <= io_limit || verb)
2096 printf("\tI/O behind bridge: %08x-%08x\n", io_base, io_limit+0xfff);
2099 if (mem_type != (mem_limit & PCI_MEMORY_RANGE_TYPE_MASK) ||
2101 printf("\t!!! Unknown memory range types %x/%x\n", mem_base, mem_limit);
2104 mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
2105 mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
2106 if (mem_base <= mem_limit || verb)
2107 printf("\tMemory behind bridge: %08x-%08x\n", mem_base, mem_limit + 0xfffff);
2110 if (pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
2111 (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64))
2112 printf("\t!!! Unknown prefetchable memory range types %x/%x\n", pref_base, pref_limit);
2115 pref_base = (pref_base & PCI_PREF_RANGE_MASK) << 16;
2116 pref_limit = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
2117 if (pref_base <= pref_limit || verb)
2119 if (pref_type == PCI_PREF_RANGE_TYPE_32)
2120 printf("\tPrefetchable memory behind bridge: %08x-%08x\n", pref_base, pref_limit + 0xfffff);
2122 printf("\tPrefetchable memory behind bridge: %08x%08x-%08x%08x\n",
2123 get_conf_long(d, PCI_PREF_BASE_UPPER32),
2125 get_conf_long(d, PCI_PREF_LIMIT_UPPER32),
2126 pref_limit + 0xfffff);
2131 printf("\tSecondary status: 66MHz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c\n",
2132 FLAG(sec_stat, PCI_STATUS_66MHZ),
2133 FLAG(sec_stat, PCI_STATUS_FAST_BACK),
2134 FLAG(sec_stat, PCI_STATUS_PARITY),
2135 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
2136 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
2137 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
2138 FLAG(sec_stat, PCI_STATUS_SIG_TARGET_ABORT),
2139 FLAG(sec_stat, PCI_STATUS_REC_TARGET_ABORT),
2140 FLAG(sec_stat, PCI_STATUS_REC_MASTER_ABORT),
2141 FLAG(sec_stat, PCI_STATUS_SIG_SYSTEM_ERROR),
2142 FLAG(sec_stat, PCI_STATUS_DETECTED_PARITY));
2144 show_rom(d, PCI_ROM_ADDRESS1);
2148 printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
2149 FLAG(brc, PCI_BRIDGE_CTL_PARITY),
2150 FLAG(brc, PCI_BRIDGE_CTL_SERR),
2151 FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
2152 FLAG(brc, PCI_BRIDGE_CTL_VGA),
2153 FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
2154 FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
2155 FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
2156 printf("\t\tPriDiscTmr%c SecDiscTmr%c DiscTmrStat%c DiscTmrSERREn%c\n",
2157 FLAG(brc, PCI_BRIDGE_CTL_PRI_DISCARD_TIMER),
2158 FLAG(brc, PCI_BRIDGE_CTL_SEC_DISCARD_TIMER),
2159 FLAG(brc, PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS),
2160 FLAG(brc, PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN));
2167 show_htype2(struct device *d)
2170 word cmd = get_conf_word(d, PCI_COMMAND);
2171 word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
2173 int verb = verbose > 2;
2176 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
2177 get_conf_byte(d, PCI_CB_PRIMARY_BUS),
2178 get_conf_byte(d, PCI_CB_CARD_BUS),
2179 get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
2180 get_conf_byte(d, PCI_CB_LATENCY_TIMER));
2184 u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
2185 u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
2186 if (limit > base || verb)
2187 printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
2188 (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
2189 (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
2194 u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
2195 u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
2196 if (!(base & PCI_IO_RANGE_TYPE_32))
2201 base &= PCI_CB_IO_RANGE_MASK;
2202 limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
2203 if (base <= limit || verb)
2204 printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
2205 (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
2208 if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
2209 printf("\tSecondary status: SERR\n");
2211 printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
2212 FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
2213 FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
2214 FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
2215 FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
2216 FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
2217 FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
2218 FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
2219 FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
2221 if (d->config_cached < 128)
2223 printf("\t<access denied to the rest>\n");
2227 exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
2229 printf("\t16-bit legacy interface ports at %04x\n", exca);
2233 show_verbose(struct device *d)
2235 struct pci_dev *p = d->dev;
2236 word status = get_conf_word(d, PCI_STATUS);
2237 word cmd = get_conf_word(d, PCI_COMMAND);
2238 word class = p->device_class;
2239 byte bist = get_conf_byte(d, PCI_BIST);
2240 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
2241 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
2242 byte cache_line = get_conf_byte(d, PCI_CACHE_LINE_SIZE);
2243 byte max_lat, min_gnt;
2244 byte int_pin = get_conf_byte(d, PCI_INTERRUPT_PIN);
2245 unsigned int irq = p->irq;
2246 word subsys_v, subsys_d;
2247 char ssnamebuf[256];
2253 case PCI_HEADER_TYPE_NORMAL:
2254 if (class == PCI_CLASS_BRIDGE_PCI)
2255 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
2256 max_lat = get_conf_byte(d, PCI_MAX_LAT);
2257 min_gnt = get_conf_byte(d, PCI_MIN_GNT);
2259 case PCI_HEADER_TYPE_BRIDGE:
2260 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
2261 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
2262 irq = int_pin = min_gnt = max_lat = 0;
2264 case PCI_HEADER_TYPE_CARDBUS:
2265 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
2266 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
2267 min_gnt = max_lat = 0;
2270 printf("\t!!! Unknown header type %02x\n", htype);
2274 get_subid(d, &subsys_v, &subsys_d);
2275 if (subsys_v && subsys_v != 0xffff)
2276 printf("\tSubsystem: %s\n",
2277 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
2278 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
2279 p->vendor_id, p->device_id, subsys_v, subsys_d));
2283 printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c DisINTx%c\n",
2284 FLAG(cmd, PCI_COMMAND_IO),
2285 FLAG(cmd, PCI_COMMAND_MEMORY),
2286 FLAG(cmd, PCI_COMMAND_MASTER),
2287 FLAG(cmd, PCI_COMMAND_SPECIAL),
2288 FLAG(cmd, PCI_COMMAND_INVALIDATE),
2289 FLAG(cmd, PCI_COMMAND_VGA_PALETTE),
2290 FLAG(cmd, PCI_COMMAND_PARITY),
2291 FLAG(cmd, PCI_COMMAND_WAIT),
2292 FLAG(cmd, PCI_COMMAND_SERR),
2293 FLAG(cmd, PCI_COMMAND_FAST_BACK),
2294 FLAG(cmd, PCI_COMMAND_DISABLE_INTx));
2295 printf("\tStatus: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c INTx%c\n",
2296 FLAG(status, PCI_STATUS_CAP_LIST),
2297 FLAG(status, PCI_STATUS_66MHZ),
2298 FLAG(status, PCI_STATUS_UDF),
2299 FLAG(status, PCI_STATUS_FAST_BACK),
2300 FLAG(status, PCI_STATUS_PARITY),
2301 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
2302 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
2303 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
2304 FLAG(status, PCI_STATUS_SIG_TARGET_ABORT),
2305 FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
2306 FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
2307 FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
2308 FLAG(status, PCI_STATUS_DETECTED_PARITY),
2309 FLAG(status, PCI_STATUS_INTx));
2310 if (cmd & PCI_COMMAND_MASTER)
2312 printf("\tLatency: %d", latency);
2313 if (min_gnt || max_lat)
2317 printf("%dns min", min_gnt*250);
2318 if (min_gnt && max_lat)
2321 printf("%dns max", max_lat*250);
2325 printf(", Cache Line Size: %d bytes", cache_line * 4);
2329 printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n",
2330 (int_pin ? 'A' + int_pin - 1 : '?'), irq);
2334 printf("\tFlags: ");
2335 if (cmd & PCI_COMMAND_MASTER)
2336 printf("bus master, ");
2337 if (cmd & PCI_COMMAND_VGA_PALETTE)
2338 printf("VGA palette snoop, ");
2339 if (cmd & PCI_COMMAND_WAIT)
2340 printf("stepping, ");
2341 if (cmd & PCI_COMMAND_FAST_BACK)
2342 printf("fast Back2Back, ");
2343 if (status & PCI_STATUS_66MHZ)
2345 if (status & PCI_STATUS_UDF)
2346 printf("user-definable features, ");
2348 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
2349 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
2350 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??");
2351 if (cmd & PCI_COMMAND_MASTER)
2352 printf(", latency %d", latency);
2354 printf(", IRQ " PCIIRQ_FMT, irq);
2358 if (bist & PCI_BIST_CAPABLE)
2360 if (bist & PCI_BIST_START)
2361 printf("\tBIST is running\n");
2363 printf("\tBIST result: %02x\n", bist & PCI_BIST_CODE_MASK);
2368 case PCI_HEADER_TYPE_NORMAL:
2371 case PCI_HEADER_TYPE_BRIDGE:
2374 case PCI_HEADER_TYPE_CARDBUS:
2380 /*** Machine-readable dumps ***/
2383 show_hex_dump(struct device *d)
2385 unsigned int i, cnt;
2387 cnt = d->config_cached;
2388 if (opt_hex >= 3 && config_fetch(d, cnt, 256-cnt))
2391 if (opt_hex >= 4 && config_fetch(d, 256, 4096-256))
2395 for(i=0; i<cnt; i++)
2399 printf(" %02x", get_conf_byte(d, i));
2406 print_shell_escaped(char *c)
2411 if (*c == '"' || *c == '\\')
2419 show_machine(struct device *d)
2421 struct pci_dev *p = d->dev;
2424 char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
2426 get_subid(d, &sv_id, &sd_id);
2430 printf((opt_machine >= 2) ? "Slot:\t" : "Device:\t");
2433 printf("Class:\t%s\n",
2434 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
2435 printf("Vendor:\t%s\n",
2436 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
2437 printf("Device:\t%s\n",
2438 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
2439 if (sv_id && sv_id != 0xffff)
2441 printf("SVendor:\t%s\n",
2442 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
2443 printf("SDevice:\t%s\n",
2444 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
2446 if (c = get_conf_byte(d, PCI_REVISION_ID))
2447 printf("Rev:\t%02x\n", c);
2448 if (c = get_conf_byte(d, PCI_CLASS_PROG))
2449 printf("ProgIf:\t%02x\n", c);
2451 show_kernel_machine(d);
2456 print_shell_escaped(pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
2457 print_shell_escaped(pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
2458 print_shell_escaped(pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
2459 if (c = get_conf_byte(d, PCI_REVISION_ID))
2460 printf(" -r%02x", c);
2461 if (c = get_conf_byte(d, PCI_CLASS_PROG))
2462 printf(" -p%02x", c);
2463 if (sv_id && sv_id != 0xffff)
2465 print_shell_escaped(pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
2466 print_shell_escaped(pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
2469 printf(" \"\" \"\"");
2474 /*** Main show function ***/
2477 show_device(struct device *d)
2487 if (opt_kernel || verbose)
2492 if (verbose || opt_hex)
2501 for(d=first_dev; d; d=d->next)
2505 /*** Tree output ***/
2508 struct bridge *chain; /* Single-linked list of bridges */
2509 struct bridge *next, *child; /* Tree of bridges */
2510 struct bus *first_bus; /* List of buses connected to this bridge */
2511 unsigned int domain;
2512 unsigned int primary, secondary, subordinate; /* Bus numbers */
2513 struct device *br_dev;
2517 unsigned int domain;
2518 unsigned int number;
2519 struct bus *sibling;
2520 struct device *first_dev, **last_dev;
2523 static struct bridge host_bridge = { NULL, NULL, NULL, NULL, 0, ~0, 0, ~0, NULL };
2526 find_bus(struct bridge *b, unsigned int domain, unsigned int n)
2530 for(bus=b->first_bus; bus; bus=bus->sibling)
2531 if (bus->domain == domain && bus->number == n)
2537 new_bus(struct bridge *b, unsigned int domain, unsigned int n)
2539 struct bus *bus = xmalloc(sizeof(struct bus));
2540 bus->domain = domain;
2542 bus->sibling = b->first_bus;
2543 bus->first_dev = NULL;
2544 bus->last_dev = &bus->first_dev;
2550 insert_dev(struct device *d, struct bridge *b)
2552 struct pci_dev *p = d->dev;
2555 if (! (bus = find_bus(b, p->domain, p->bus)))
2558 for(c=b->child; c; c=c->next)
2559 if (c->domain == p->domain && c->secondary <= p->bus && p->bus <= c->subordinate)
2564 bus = new_bus(b, p->domain, p->bus);
2566 /* Simple insertion at the end _does_ guarantee the correct order as the
2567 * original device list was sorted by (domain, bus, devfn) lexicographically
2568 * and all devices on the new list have the same bus number.
2571 bus->last_dev = &d->next;
2578 struct device *d, *d2;
2579 struct bridge **last_br, *b;
2581 /* Build list of bridges */
2583 last_br = &host_bridge.chain;
2584 for(d=first_dev; d; d=d->next)
2586 word class = d->dev->device_class;
2587 byte ht = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
2588 if (class == PCI_CLASS_BRIDGE_PCI &&
2589 (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS))
2591 b = xmalloc(sizeof(struct bridge));
2592 b->domain = d->dev->domain;
2593 if (ht == PCI_HEADER_TYPE_BRIDGE)
2595 b->primary = get_conf_byte(d, PCI_PRIMARY_BUS);
2596 b->secondary = get_conf_byte(d, PCI_SECONDARY_BUS);
2597 b->subordinate = get_conf_byte(d, PCI_SUBORDINATE_BUS);
2601 b->primary = get_conf_byte(d, PCI_CB_PRIMARY_BUS);
2602 b->secondary = get_conf_byte(d, PCI_CB_CARD_BUS);
2603 b->subordinate = get_conf_byte(d, PCI_CB_SUBORDINATE_BUS);
2606 last_br = &b->chain;
2607 b->next = b->child = NULL;
2608 b->first_bus = NULL;
2614 /* Create a bridge tree */
2616 for(b=&host_bridge; b; b=b->chain)
2618 struct bridge *c, *best;
2620 for(c=&host_bridge; c; c=c->chain)
2621 if (c != b && (c == &host_bridge || b->domain == c->domain) &&
2622 b->primary >= c->secondary && b->primary <= c->subordinate &&
2623 (!best || best->subordinate - best->primary > c->subordinate - c->primary))
2627 b->next = best->child;
2632 /* Insert secondary bus for each bridge */
2634 for(b=&host_bridge; b; b=b->chain)
2635 if (!find_bus(b, b->domain, b->secondary))
2636 new_bus(b, b->domain, b->secondary);
2638 /* Create bus structs and link devices */
2640 for(d=first_dev; d;)
2643 insert_dev(d, &host_bridge);
2649 print_it(char *line, char *p)
2653 fputs(line, stdout);
2654 for(p=line; *p; p++)
2655 if (*p == '+' || *p == '|')
2661 static void show_tree_bridge(struct bridge *, char *, char *);
2664 show_tree_dev(struct device *d, char *line, char *p)
2666 struct pci_dev *q = d->dev;
2670 p += sprintf(p, "%02x.%x", q->dev, q->func);
2671 for(b=&host_bridge; b; b=b->chain)
2674 if (b->secondary == b->subordinate)
2675 p += sprintf(p, "-[%04x:%02x]-", b->domain, b->secondary);
2677 p += sprintf(p, "-[%04x:%02x-%02x]-", b->domain, b->secondary, b->subordinate);
2678 show_tree_bridge(b, line, p);
2682 p += sprintf(p, " %s",
2683 pci_lookup_name(pacc, namebuf, sizeof(namebuf),
2684 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
2685 q->vendor_id, q->device_id));
2690 show_tree_bus(struct bus *b, char *line, char *p)
2694 else if (!b->first_dev->next)
2698 show_tree_dev(b->first_dev, line, p);
2702 struct device *d = b->first_dev;
2707 show_tree_dev(d, line, p+2);
2712 show_tree_dev(d, line, p+2);
2717 show_tree_bridge(struct bridge *b, char *line, char *p)
2720 if (!b->first_bus->sibling)
2722 if (b == &host_bridge)
2723 p += sprintf(p, "[%04x:%02x]-", b->domain, b->first_bus->number);
2724 show_tree_bus(b->first_bus, line, p);
2728 struct bus *u = b->first_bus;
2733 k = p + sprintf(p, "+-[%04x:%02x]-", u->domain, u->number);
2734 show_tree_bus(u, line, k);
2737 k = p + sprintf(p, "\\-[%04x:%02x]-", u->domain, u->number);
2738 show_tree_bus(u, line, k);
2748 show_tree_bridge(&host_bridge, line, line);
2751 /*** Bus mapping mode ***/
2754 struct bus_bridge *next;
2755 byte this, dev, func, first, last, bug;
2761 struct bus_bridge *bridges, *via;
2764 static struct bus_info *bus_info;
2767 map_bridge(struct bus_info *bi, struct device *d, int np, int ns, int nl)
2769 struct bus_bridge *b = xmalloc(sizeof(struct bus_bridge));
2770 struct pci_dev *p = d->dev;
2772 b->next = bi->bridges;
2774 b->this = get_conf_byte(d, np);
2777 b->first = get_conf_byte(d, ns);
2778 b->last = get_conf_byte(d, nl);
2779 printf("## %02x.%02x:%d is a bridge from %02x to %02x-%02x\n",
2780 p->bus, p->dev, p->func, b->this, b->first, b->last);
2781 if (b->this != p->bus)
2782 printf("!!! Bridge points to invalid primary bus.\n");
2783 if (b->first > b->last)
2785 printf("!!! Bridge points to invalid bus range.\n");
2794 int verbose = pacc->debugging;
2795 struct bus_info *bi = bus_info + bus;
2799 printf("Mapping bus %02x\n", bus);
2800 for(dev = 0; dev < 32; dev++)
2801 if (filter.slot < 0 || filter.slot == dev)
2804 for(func = 0; func < func_limit; func++)
2805 if (filter.func < 0 || filter.func == func)
2807 /* XXX: Bus mapping supports only domain 0 */
2808 struct pci_dev *p = pci_get_dev(pacc, 0, bus, dev, func);
2809 u16 vendor = pci_read_word(p, PCI_VENDOR_ID);
2810 if (vendor && vendor != 0xffff)
2812 if (!func && (pci_read_byte(p, PCI_HEADER_TYPE) & 0x80))
2815 printf("Discovered device %02x:%02x.%d\n", bus, dev, func);
2817 if (d = scan_device(p))
2820 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
2822 case PCI_HEADER_TYPE_BRIDGE:
2823 map_bridge(bi, d, PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS);
2825 case PCI_HEADER_TYPE_CARDBUS:
2826 map_bridge(bi, d, PCI_CB_PRIMARY_BUS, PCI_CB_CARD_BUS, PCI_CB_SUBORDINATE_BUS);
2832 printf("But it was filtered out.\n");
2840 do_map_bridges(int bus, int min, int max)
2842 struct bus_info *bi = bus_info + bus;
2843 struct bus_bridge *b;
2846 for(b=bi->bridges; b; b=b->next)
2848 if (bus_info[b->first].guestbook)
2850 else if (b->first < min || b->last > max)
2854 bus_info[b->first].via = b;
2855 do_map_bridges(b->first, b->first, b->last);
2865 printf("\nSummary of buses:\n\n");
2866 for(i=0; i<256; i++)
2867 if (bus_info[i].exists && !bus_info[i].guestbook)
2868 do_map_bridges(i, 0, 255);
2869 for(i=0; i<256; i++)
2871 struct bus_info *bi = bus_info + i;
2872 struct bus_bridge *b = bi->via;
2876 printf("%02x: ", i);
2878 printf("Entered via %02x:%02x.%d\n", b->this, b->dev, b->func);
2880 printf("Primary host bus\n");
2882 printf("Secondary host bus (?)\n");
2884 for(b=bi->bridges; b; b=b->next)
2886 printf("\t%02x.%d Bridge to %02x-%02x", b->dev, b->func, b->first, b->last);
2890 printf(" <overlap bug>");
2893 printf(" <crossing bug>");
2904 if (pacc->method == PCI_ACCESS_PROC_BUS_PCI ||
2905 pacc->method == PCI_ACCESS_DUMP)
2906 printf("WARNING: Bus mapping can be reliable only with direct hardware access enabled.\n\n");
2907 bus_info = xmalloc(sizeof(struct bus_info) * 256);
2908 memset(bus_info, 0, sizeof(struct bus_info) * 256);
2909 if (filter.bus >= 0)
2910 do_map_bus(filter.bus);
2914 for(bus=0; bus<256; bus++)
2923 main(int argc, char **argv)
2928 if (argc == 2 && !strcmp(argv[1], "--version"))
2930 puts("lspci version " PCIUTILS_VERSION);
2936 pci_filter_init(pacc, &filter);
2938 while ((i = getopt(argc, argv, options)) != -1)
2942 pacc->numeric_ids++;
2948 pacc->buscentric = 1;
2952 if (msg = pci_filter_parse_slot(&filter, optarg))
2956 if (msg = pci_filter_parse_id(&filter, optarg))
2966 pci_set_name_list_path(pacc, optarg, 0);
2972 opt_pcimap = optarg;
2995 die("DNS queries are not available in this version");
2998 if (parse_generic_option(i, pacc, optarg))
3001 fprintf(stderr, help_msg, pacc->id_file_name);
3009 pacc->id_lookup_mode |= PCI_LOOKUP_NETWORK;
3010 if (opt_query_dns > 1)
3011 pacc->id_lookup_mode |= PCI_LOOKUP_REFRESH_CACHE;
3014 pacc->id_lookup_mode |= PCI_LOOKUP_NETWORK | PCI_LOOKUP_SKIP_LOCAL;
3030 return (seen_errors ? 2 : 0);