2 * The PCI Utilities -- List All PCI Devices
4 * Copyright (c) 1997--2020 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
18 int verbose; /* Show detailed information */
19 static int opt_hex; /* Show contents of config space as hexadecimal numbers */
20 struct pci_filter filter; /* Device filter */
21 static int opt_filter; /* Any filter was given */
22 static int opt_tree; /* Show bus tree */
23 static int opt_path; /* Show bridge path */
24 static int opt_machine; /* Generate machine-readable output */
25 static int opt_map_mode; /* Bus mapping mode enabled */
26 static int opt_domains; /* Show domain numbers (0=disabled, 1=auto-detected, 2=requested) */
27 static int opt_kernel; /* Show kernel drivers */
28 static int opt_query_dns; /* Query the DNS (0=disabled, 1=enabled, 2=refresh cache) */
29 static int opt_query_all; /* Query the DNS for all entries */
30 char *opt_pcimap; /* Override path to Linux modules.pcimap */
32 const char program_name[] = "lspci";
34 static char options[] = "nvbxs:d:tPi:mgp:qkMDQ" GENERIC_OPTIONS ;
36 static char help_msg[] =
37 "Usage: lspci [<switches>]\n"
39 "Basic display modes:\n"
40 "-mm\t\tProduce machine-readable output (single -m for an obsolete format)\n"
41 "-t\t\tShow bus tree\n"
44 "-v\t\tBe verbose (-vv or -vvv for higher verbosity)\n"
46 "-k\t\tShow kernel drivers handling each device\n"
48 "-x\t\tShow hex-dump of the standard part of the config space\n"
49 "-xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n"
50 "-xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n"
51 "-b\t\tBus-centric view (addresses and IRQ's as seen by the bus)\n"
52 "-D\t\tAlways show domain numbers\n"
53 "-P\t\tDisplay bridge path in addition to bus and device number\n"
54 "-PP\t\tDisplay bus path in addition to bus and device number\n"
56 "Resolving of device ID's to names:\n"
57 "-n\t\tShow numeric ID's\n"
58 "-nn\t\tShow both textual and numeric ID's (names & numbers)\n"
60 "-q\t\tQuery the PCI ID database for unknown ID's via DNS\n"
61 "-qq\t\tAs above, but re-query locally cached entries\n"
62 "-Q\t\tQuery the PCI ID database for all ID's via DNS\n"
65 "Selection of devices:\n"
66 "-s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n"
67 "-d [<vendor>]:[<device>][:<class>]\t\tShow only devices with specified ID's\n"
70 "-i <file>\tUse specified ID database instead of %s\n"
72 "-p <file>\tLook up kernel modules in a given file instead of default modules.pcimap\n"
74 "-M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
76 "PCI access options:\n"
80 /*** Our view of the PCI bus ***/
82 struct pci_access *pacc;
83 struct device *first_dev;
84 static int seen_errors;
85 static int need_topology;
88 config_fetch(struct device *d, unsigned int pos, unsigned int len)
90 unsigned int end = pos+len;
93 while (pos < d->config_bufsize && len && d->present[pos])
95 while (pos+len <= d->config_bufsize && len && d->present[pos+len-1])
100 if (end > d->config_bufsize)
102 int orig_size = d->config_bufsize;
103 while (end > d->config_bufsize)
104 d->config_bufsize *= 2;
105 d->config = xrealloc(d->config, d->config_bufsize);
106 d->present = xrealloc(d->present, d->config_bufsize);
107 memset(d->present + orig_size, 0, d->config_bufsize - orig_size);
109 result = pci_read_block(d->dev, pos, d->config + pos, len);
111 memset(d->present + pos, 1, len);
116 scan_device(struct pci_dev *p)
120 if (p->domain && !opt_domains)
122 if (!pci_filter_match(&filter, p) && !need_topology)
124 d = xmalloc(sizeof(struct device));
125 memset(d, 0, sizeof(*d));
127 d->no_config_access = p->no_config_access;
128 d->config_cached = d->config_bufsize = 64;
129 d->config = xmalloc(64);
130 d->present = xmalloc(64);
131 memset(d->present, 1, 64);
132 if (!d->no_config_access && !pci_read_block(p, 0, d->config, 64))
134 d->no_config_access = 1;
135 d->config_cached = d->config_bufsize = 0;
136 memset(d->present, 0, 64);
138 if (!d->no_config_access && (d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
140 /* For cardbus bridges, we need to fetch 64 bytes more to get the
141 * full standard header... */
142 if (config_fetch(d, 64, 64))
143 d->config_cached += 64;
145 pci_setup_cache(p, d->config, d->config_cached);
146 pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_CLASS | PCI_FILL_CLASS_EXT | PCI_FILL_SUBSYS | (need_topology ? PCI_FILL_PARENT : 0));
157 for (p=pacc->devices; p; p=p->next)
158 if (d = scan_device(p))
165 /*** Config space accesses ***/
168 check_conf_range(struct device *d, unsigned int pos, unsigned int len)
171 if (!d->present[pos])
172 die("Internal bug: Accessing non-read configuration byte at position %x", pos);
178 get_conf_byte(struct device *d, unsigned int pos)
180 check_conf_range(d, pos, 1);
181 return d->config[pos];
185 get_conf_word(struct device *d, unsigned int pos)
187 check_conf_range(d, pos, 2);
188 return d->config[pos] | (d->config[pos+1] << 8);
192 get_conf_long(struct device *d, unsigned int pos)
194 check_conf_range(d, pos, 4);
195 return d->config[pos] |
196 (d->config[pos+1] << 8) |
197 (d->config[pos+2] << 16) |
198 (d->config[pos+3] << 24);
204 compare_them(const void *A, const void *B)
206 const struct pci_dev *a = (*(const struct device **)A)->dev;
207 const struct pci_dev *b = (*(const struct device **)B)->dev;
209 if (a->domain < b->domain)
211 if (a->domain > b->domain)
221 if (a->func < b->func)
223 if (a->func > b->func)
231 struct device **index, **h, **last_dev;
236 for (d=first_dev; d; d=d->next)
238 h = index = alloca(sizeof(struct device *) * cnt);
239 for (d=first_dev; d; d=d->next)
241 qsort(index, cnt, sizeof(struct device *), compare_them);
242 last_dev = &first_dev;
247 last_dev = &(*h)->next;
253 /*** Normal output ***/
256 show_slot_path(struct device *d)
258 struct pci_dev *p = d->dev;
262 struct bus *bus = d->parent_bus;
263 struct bridge *br = bus->parent_bridge;
265 if (br && br->br_dev)
267 show_slot_path(br->br_dev);
269 printf("/%02x:%02x.%d", p->bus, p->dev, p->func);
271 printf("/%02x.%d", p->dev, p->func);
275 printf("%02x:%02x.%d", p->bus, p->dev, p->func);
279 show_slot_name(struct device *d)
281 struct pci_dev *p = d->dev;
283 if (!opt_machine ? opt_domains : (p->domain || opt_domains >= 2))
284 printf("%04x:", p->domain);
289 show_terse(struct device *d)
292 struct pci_dev *p = d->dev;
293 char classbuf[128], devbuf[128];
297 pci_lookup_name(pacc, classbuf, sizeof(classbuf),
300 pci_lookup_name(pacc, devbuf, sizeof(devbuf),
301 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
302 p->vendor_id, p->device_id));
303 if ((p->known_fields & PCI_FILL_CLASS_EXT) && p->rev_id)
304 printf(" (rev %02x)", p->rev_id);
308 c = (p->known_fields & PCI_FILL_CLASS_EXT) ? p->prog_if : 0;
309 x = pci_lookup_name(pacc, devbuf, sizeof(devbuf),
310 PCI_LOOKUP_PROGIF | PCI_LOOKUP_NO_NUMBERS,
314 printf(" (prog-if %02x", c);
322 if (verbose || opt_kernel)
326 pci_fill_info(p, PCI_FILL_LABEL);
329 printf("\tDeviceName: %s", p->label);
330 if ((p->known_fields & PCI_FILL_SUBSYS) &&
331 p->subsys_vendor_id && p->subsys_vendor_id != 0xffff)
332 printf("\tSubsystem: %s\n",
333 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
334 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
335 p->vendor_id, p->device_id, p->subsys_vendor_id, p->subsys_id));
339 /*** Verbose output ***/
344 static const char suffix[][2] = { "", "K", "M", "G", "T" };
348 for (i = 0; i < (sizeof(suffix) / sizeof(*suffix) - 1); i++) {
353 printf(" [size=%u%s]", (unsigned)x, suffix[i]);
357 show_range(const char *prefix, u64 base, u64 limit, int bits, int disabled)
359 printf("%s:", prefix);
360 if (base <= limit || verbose > 2)
361 printf(" %0*" PCI_U64_FMT_X "-%0*" PCI_U64_FMT_X, (bits+3)/4, base, (bits+3)/4, limit);
362 if (!disabled && base <= limit)
363 show_size(limit - base + 1);
365 printf(" [disabled]");
367 printf(" [%d-bit]", bits);
372 ioflg_to_pciflg(pciaddr_t ioflg)
376 if (ioflg & PCI_IORESOURCE_IO)
377 flg = PCI_BASE_ADDRESS_SPACE_IO;
378 else if (!(ioflg & PCI_IORESOURCE_MEM))
382 flg = PCI_BASE_ADDRESS_SPACE_MEMORY;
383 if (ioflg & PCI_IORESOURCE_MEM_64)
384 flg |= PCI_BASE_ADDRESS_MEM_TYPE_64;
386 flg |= PCI_BASE_ADDRESS_MEM_TYPE_32;
387 if (ioflg & PCI_IORESOURCE_PREFETCH)
388 flg |= PCI_BASE_ADDRESS_MEM_PREFETCH;
395 show_bases(struct device *d, int cnt, int without_config_data)
397 struct pci_dev *p = d->dev;
398 word cmd = without_config_data ? (PCI_COMMAND_IO | PCI_COMMAND_MEMORY) : get_conf_word(d, PCI_COMMAND);
401 for (i=0; i<cnt; i++)
403 pciaddr_t pos = p->base_addr[i];
404 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
405 pciaddr_t ioflg = (p->known_fields & PCI_FILL_IO_FLAGS) ? p->flags[i] : 0;
406 u32 flg = (p->known_fields & PCI_FILL_IO_FLAGS) ? ioflg_to_pciflg(ioflg) : without_config_data ? 0 : get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
412 if (flg == 0xffffffff)
414 if (!pos && !flg && !len)
418 printf("\tRegion %d: ", i);
422 /* Detect virtual regions, which are reported by the OS, but unassigned in the device */
423 if ((p->known_fields & PCI_FILL_IO_FLAGS) && !without_config_data)
425 /* Read address as seen by the hardware */
426 hw_lower = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
427 if ((hw_lower & PCI_BASE_ADDRESS_SPACE) == (ioflg_to_pciflg(ioflg) & PCI_BASE_ADDRESS_SPACE))
429 if ((ioflg & PCI_IORESOURCE_TYPE_BITS) == PCI_IORESOURCE_MEM &&
430 (hw_lower & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64)
435 hw_upper = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i + 1);
437 if (pos && !hw_lower && !hw_upper && !(ioflg & PCI_IORESOURCE_PCI_EA_BEI))
442 /* Print base address */
443 if (flg & PCI_BASE_ADDRESS_SPACE_IO)
445 pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
446 printf("I/O ports at ");
447 if (a || (cmd & PCI_COMMAND_IO))
448 printf(PCIADDR_PORT_FMT, a);
452 printf("<unassigned>");
454 printf(" [virtual]");
455 else if (!(cmd & PCI_COMMAND_IO))
456 printf(" [disabled]");
460 int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
461 pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
463 printf("Memory at ");
465 printf("<broken-64-bit-slot>");
467 printf(PCIADDR_T_FMT, a);
468 else if (hw_lower || hw_upper)
471 printf("<unassigned>");
472 printf(" (%s, %sprefetchable)",
473 (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
474 (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
475 (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
476 (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
478 printf(" [virtual]");
479 else if (!(cmd & PCI_COMMAND_MEMORY))
480 printf(" [disabled]");
483 if (ioflg & PCI_IORESOURCE_PCI_EA_BEI)
484 printf(" [enhanced]");
492 show_rom(struct device *d, int reg)
494 struct pci_dev *p = d->dev;
495 pciaddr_t rom = p->rom_base_addr;
496 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
497 pciaddr_t ioflg = (p->known_fields & PCI_FILL_IO_FLAGS) ? p->rom_flags : 0;
498 u32 flg = reg >= 0 ? get_conf_long(d, reg) : ioflg_to_pciflg(ioflg);
499 word cmd = reg >= 0 ? get_conf_word(d, PCI_COMMAND) : PCI_COMMAND_MEMORY;
502 if (!rom && !flg && !len)
505 if (reg >= 0 && (rom & PCI_ROM_ADDRESS_MASK) && !(flg & PCI_ROM_ADDRESS_MASK) && !(ioflg & PCI_IORESOURCE_PCI_EA_BEI))
511 printf("\tExpansion ROM at ");
512 if (rom & PCI_ROM_ADDRESS_MASK)
513 printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
514 else if (flg & PCI_ROM_ADDRESS_MASK)
517 printf("<unassigned>");
520 printf(" [virtual]");
522 if (!(flg & PCI_ROM_ADDRESS_ENABLE))
523 printf(" [disabled]");
524 else if (!virtual && !(cmd & PCI_COMMAND_MEMORY))
525 printf(" [disabled by cmd]");
527 if (ioflg & PCI_IORESOURCE_PCI_EA_BEI)
528 printf(" [enhanced]");
535 show_htype0(struct device *d)
538 show_rom(d, PCI_ROM_ADDRESS);
539 show_caps(d, PCI_CAPABILITY_LIST);
543 show_htype1(struct device *d)
545 struct pci_dev *p = d->dev;
546 u32 io_base = get_conf_byte(d, PCI_IO_BASE);
547 u32 io_limit = get_conf_byte(d, PCI_IO_LIMIT);
548 u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
549 u32 mem_base = get_conf_word(d, PCI_MEMORY_BASE);
550 u32 mem_limit = get_conf_word(d, PCI_MEMORY_LIMIT);
551 u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
552 u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE);
553 u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT);
554 u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
555 word sec_stat = get_conf_word(d, PCI_SEC_STATUS);
556 word brc = get_conf_word(d, PCI_BRIDGE_CONTROL);
557 int io_disabled = (p->known_fields & PCI_FILL_BRIDGE_BASES) && !p->bridge_size[0];
558 int mem_disabled = (p->known_fields & PCI_FILL_BRIDGE_BASES) && !p->bridge_size[1];
559 int pref_disabled = (p->known_fields & PCI_FILL_BRIDGE_BASES) && !p->bridge_size[2];
560 int io_bits, pref_bits;
563 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
564 get_conf_byte(d, PCI_PRIMARY_BUS),
565 get_conf_byte(d, PCI_SECONDARY_BUS),
566 get_conf_byte(d, PCI_SUBORDINATE_BUS),
567 get_conf_byte(d, PCI_SEC_LATENCY_TIMER));
569 if ((p->known_fields & PCI_FILL_BRIDGE_BASES) && !io_disabled)
571 io_base = p->bridge_base_addr[0] & PCI_IO_RANGE_MASK;
572 io_limit = io_base + p->bridge_size[0] - 1;
573 io_type = p->bridge_base_addr[0] & PCI_IO_RANGE_TYPE_MASK;
574 io_bits = (io_type == PCI_IO_RANGE_TYPE_32) ? 32 : 16;
575 show_range("\tI/O behind bridge", io_base, io_limit, io_bits, io_disabled);
577 else if (io_type != (io_limit & PCI_IO_RANGE_TYPE_MASK) ||
578 (io_type != PCI_IO_RANGE_TYPE_16 && io_type != PCI_IO_RANGE_TYPE_32))
579 printf("\t!!! Unknown I/O range types %x/%x\n", io_base, io_limit);
582 io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
583 io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
584 if (io_type == PCI_IO_RANGE_TYPE_32)
586 io_base |= (get_conf_word(d, PCI_IO_BASE_UPPER16) << 16);
587 io_limit |= (get_conf_word(d, PCI_IO_LIMIT_UPPER16) << 16);
589 /* I/O is unsupported if both base and limit are zeros and resource is disabled */
590 if (!(io_base == 0x0 && io_limit == 0x0 && io_disabled))
593 io_bits = (io_type == PCI_IO_RANGE_TYPE_32) ? 32 : 16;
594 show_range("\tI/O behind bridge", io_base, io_limit, io_bits, io_disabled);
598 if ((p->known_fields & PCI_FILL_BRIDGE_BASES) && !mem_disabled)
600 mem_base = p->bridge_base_addr[1] & PCI_MEMORY_RANGE_MASK;
601 mem_limit = mem_base + p->bridge_size[1] - 1;
602 show_range("\tMemory behind bridge", mem_base, mem_limit, 32, mem_disabled);
604 else if (mem_type != (mem_limit & PCI_MEMORY_RANGE_TYPE_MASK) ||
606 printf("\t!!! Unknown memory range types %x/%x\n", mem_base, mem_limit);
609 mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
610 mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
611 show_range("\tMemory behind bridge", mem_base, mem_limit + 0xfffff, 32, mem_disabled);
614 if ((p->known_fields & PCI_FILL_BRIDGE_BASES) && !pref_disabled)
616 u64 pref_base_64 = p->bridge_base_addr[2] & PCI_MEMORY_RANGE_MASK;
617 u64 pref_limit_64 = pref_base_64 + p->bridge_size[2] - 1;
618 pref_type = p->bridge_base_addr[2] & PCI_MEMORY_RANGE_TYPE_MASK;
619 pref_bits = (pref_type == PCI_PREF_RANGE_TYPE_64) ? 64 : 32;
620 show_range("\tPrefetchable memory behind bridge", pref_base_64, pref_limit_64, pref_bits, pref_disabled);
622 else if (pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
623 (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64))
624 printf("\t!!! Unknown prefetchable memory range types %x/%x\n", pref_base, pref_limit);
627 u64 pref_base_64 = (pref_base & PCI_PREF_RANGE_MASK) << 16;
628 u64 pref_limit_64 = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
629 if (pref_type == PCI_PREF_RANGE_TYPE_64)
631 pref_base_64 |= (u64) get_conf_long(d, PCI_PREF_BASE_UPPER32) << 32;
632 pref_limit_64 |= (u64) get_conf_long(d, PCI_PREF_LIMIT_UPPER32) << 32;
634 /* Prefetchable memory is unsupported if both base and limit are zeros and resource is disabled */
635 if (!(pref_base_64 == 0x0 && pref_limit_64 == 0x0 && pref_disabled))
637 pref_limit_64 += 0xfffff;
638 pref_bits = (pref_type == PCI_PREF_RANGE_TYPE_64) ? 64 : 32;
639 show_range("\tPrefetchable memory behind bridge", pref_base_64, pref_limit_64, pref_bits, pref_disabled);
644 printf("\tSecondary status: 66MHz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c\n",
645 FLAG(sec_stat, PCI_STATUS_66MHZ),
646 FLAG(sec_stat, PCI_STATUS_FAST_BACK),
647 FLAG(sec_stat, PCI_STATUS_PARITY),
648 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
649 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
650 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
651 FLAG(sec_stat, PCI_STATUS_SIG_TARGET_ABORT),
652 FLAG(sec_stat, PCI_STATUS_REC_TARGET_ABORT),
653 FLAG(sec_stat, PCI_STATUS_REC_MASTER_ABORT),
654 FLAG(sec_stat, PCI_STATUS_SIG_SYSTEM_ERROR),
655 FLAG(sec_stat, PCI_STATUS_DETECTED_PARITY));
657 show_rom(d, PCI_ROM_ADDRESS1);
661 printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c VGA16%c MAbort%c >Reset%c FastB2B%c\n",
662 FLAG(brc, PCI_BRIDGE_CTL_PARITY),
663 FLAG(brc, PCI_BRIDGE_CTL_SERR),
664 FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
665 FLAG(brc, PCI_BRIDGE_CTL_VGA),
666 FLAG(brc, PCI_BRIDGE_CTL_VGA_16BIT),
667 FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
668 FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
669 FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
670 printf("\t\tPriDiscTmr%c SecDiscTmr%c DiscTmrStat%c DiscTmrSERREn%c\n",
671 FLAG(brc, PCI_BRIDGE_CTL_PRI_DISCARD_TIMER),
672 FLAG(brc, PCI_BRIDGE_CTL_SEC_DISCARD_TIMER),
673 FLAG(brc, PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS),
674 FLAG(brc, PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN));
677 show_caps(d, PCI_CAPABILITY_LIST);
681 show_htype2(struct device *d)
684 word cmd = get_conf_word(d, PCI_COMMAND);
685 word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
687 int verb = verbose > 2;
690 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
691 get_conf_byte(d, PCI_CB_PRIMARY_BUS),
692 get_conf_byte(d, PCI_CB_CARD_BUS),
693 get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
694 get_conf_byte(d, PCI_CB_LATENCY_TIMER));
698 u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
699 u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
700 limit = limit + 0xfff;
701 if (base <= limit || verb)
702 printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
703 (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
704 (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
709 u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
710 u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
711 if (!(base & PCI_IO_RANGE_TYPE_32))
716 base &= PCI_CB_IO_RANGE_MASK;
717 limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
718 if (base <= limit || verb)
719 printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
720 (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
723 if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
724 printf("\tSecondary status: SERR\n");
726 printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
727 FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
728 FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
729 FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
730 FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
731 FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
732 FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
733 FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
734 FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
736 if (d->config_cached < 128)
738 printf("\t<access denied to the rest>\n");
742 exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
744 printf("\t16-bit legacy interface ports at %04x\n", exca);
745 show_caps(d, PCI_CB_CAPABILITY_LIST);
749 show_htype_unknown(struct device *d)
751 struct pci_dev *p = d->dev;
752 u64 base, limit, flags;
756 if (pacc->buscentric)
760 for (i = 0; i < 4; i++)
762 if (!p->bridge_base_addr[i])
764 base = p->bridge_base_addr[i];
765 limit = base + p->bridge_size[i] - 1;
766 flags = p->bridge_flags[i];
767 if (flags & PCI_IORESOURCE_IO)
769 bits = (flags & PCI_IORESOURCE_IO_16BIT_ADDR) ? 16 : 32;
770 str = "\tI/O behind bridge";
772 else if (flags & PCI_IORESOURCE_MEM)
774 bits = (flags & PCI_IORESOURCE_MEM_64) ? 64 : 32;
775 if (flags & PCI_IORESOURCE_PREFETCH)
776 str = "\tPrefetchable memory behind bridge";
778 str = "\tMemory behind bridge";
783 str = "\tUnknown resource behind bridge";
785 show_range(str, base, limit, bits, 0);
791 show_verbose(struct device *d)
793 struct pci_dev *p = d->dev;
794 int unknown_config_data = 0;
795 word class = p->device_class;
796 byte htype = d->no_config_access ? -1 : (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f);
798 byte max_lat, min_gnt;
799 char *dt_node, *iommu_group;
803 pci_fill_info(p, PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES |
804 PCI_FILL_PHYS_SLOT | PCI_FILL_NUMA_NODE | PCI_FILL_DT_NODE | PCI_FILL_IOMMU_GROUP |
805 PCI_FILL_BRIDGE_BASES | PCI_FILL_CLASS_EXT | PCI_FILL_SUBSYS);
809 case PCI_HEADER_TYPE_NORMAL:
810 if (class == PCI_CLASS_BRIDGE_PCI)
811 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
812 bist = get_conf_byte(d, PCI_BIST);
813 max_lat = get_conf_byte(d, PCI_MAX_LAT);
814 min_gnt = get_conf_byte(d, PCI_MIN_GNT);
816 case PCI_HEADER_TYPE_BRIDGE:
817 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
818 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
819 bist = get_conf_byte(d, PCI_BIST);
820 min_gnt = max_lat = 0;
822 case PCI_HEADER_TYPE_CARDBUS:
823 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
824 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
825 bist = get_conf_byte(d, PCI_BIST);
826 min_gnt = max_lat = 0;
829 if (!d->no_config_access)
830 printf("\t!!! Unknown header type %02x\n", htype);
832 min_gnt = max_lat = 0;
833 unknown_config_data = 1;
837 printf("\tPhysical Slot: %s\n", p->phy_slot);
839 if (dt_node = pci_get_string_property(p, PCI_FILL_DT_NODE))
840 printf("\tDevice tree node: %s\n", dt_node);
842 if (!unknown_config_data && verbose > 1)
844 word cmd = get_conf_word(d, PCI_COMMAND);
845 word status = get_conf_word(d, PCI_STATUS);
846 printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c DisINTx%c\n",
847 FLAG(cmd, PCI_COMMAND_IO),
848 FLAG(cmd, PCI_COMMAND_MEMORY),
849 FLAG(cmd, PCI_COMMAND_MASTER),
850 FLAG(cmd, PCI_COMMAND_SPECIAL),
851 FLAG(cmd, PCI_COMMAND_INVALIDATE),
852 FLAG(cmd, PCI_COMMAND_VGA_PALETTE),
853 FLAG(cmd, PCI_COMMAND_PARITY),
854 FLAG(cmd, PCI_COMMAND_WAIT),
855 FLAG(cmd, PCI_COMMAND_SERR),
856 FLAG(cmd, PCI_COMMAND_FAST_BACK),
857 FLAG(cmd, PCI_COMMAND_DISABLE_INTx));
858 printf("\tStatus: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c INTx%c\n",
859 FLAG(status, PCI_STATUS_CAP_LIST),
860 FLAG(status, PCI_STATUS_66MHZ),
861 FLAG(status, PCI_STATUS_UDF),
862 FLAG(status, PCI_STATUS_FAST_BACK),
863 FLAG(status, PCI_STATUS_PARITY),
864 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
865 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
866 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
867 FLAG(status, PCI_STATUS_SIG_TARGET_ABORT),
868 FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
869 FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
870 FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
871 FLAG(status, PCI_STATUS_DETECTED_PARITY),
872 FLAG(status, PCI_STATUS_INTx));
873 if (cmd & PCI_COMMAND_MASTER)
875 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
876 byte cache_line = get_conf_byte(d, PCI_CACHE_LINE_SIZE);
877 printf("\tLatency: %d", latency);
878 if (min_gnt || max_lat)
882 printf("%dns min", min_gnt*250);
883 if (min_gnt && max_lat)
886 printf("%dns max", max_lat*250);
890 printf(", Cache Line Size: %d bytes", cache_line * 4);
897 byte int_pin = unknown_config_data ? 0 : get_conf_byte(d, PCI_INTERRUPT_PIN);
898 if (int_pin || p->irq)
899 printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n",
900 (int_pin ? 'A' + int_pin - 1 : '?'), p->irq);
901 if (p->numa_node != -1)
902 printf("\tNUMA node: %d\n", p->numa_node);
903 if (iommu_group = pci_get_string_property(p, PCI_FILL_IOMMU_GROUP))
904 printf("\tIOMMU group: %s\n", iommu_group);
907 if (!unknown_config_data && verbose <= 1)
909 word cmd = get_conf_word(d, PCI_COMMAND);
910 word status = get_conf_word(d, PCI_STATUS);
911 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
913 if (cmd & PCI_COMMAND_MASTER)
914 printf("bus master, ");
915 if (cmd & PCI_COMMAND_VGA_PALETTE)
916 printf("VGA palette snoop, ");
917 if (cmd & PCI_COMMAND_WAIT)
918 printf("stepping, ");
919 if (cmd & PCI_COMMAND_FAST_BACK)
920 printf("fast Back2Back, ");
921 if (status & PCI_STATUS_66MHZ)
923 if (status & PCI_STATUS_UDF)
924 printf("user-definable features, ");
926 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
927 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
928 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??");
929 if (cmd & PCI_COMMAND_MASTER)
930 printf(", latency %d", latency);
932 printf(", IRQ " PCIIRQ_FMT, p->irq);
933 if (p->numa_node != -1)
934 printf(", NUMA node %d", p->numa_node);
935 if (iommu_group = pci_get_string_property(p, PCI_FILL_IOMMU_GROUP))
936 printf(", IOMMU group %s", iommu_group);
940 if (bist & PCI_BIST_CAPABLE)
942 if (bist & PCI_BIST_START)
943 printf("\tBIST is running\n");
945 printf("\tBIST result: %02x\n", bist & PCI_BIST_CODE_MASK);
950 case PCI_HEADER_TYPE_NORMAL:
953 case PCI_HEADER_TYPE_BRIDGE:
956 case PCI_HEADER_TYPE_CARDBUS:
960 show_htype_unknown(d);
964 /*** Machine-readable dumps ***/
967 show_hex_dump(struct device *d)
971 if (d->no_config_access)
973 printf("WARNING: Cannot show hex-dump of the config space\n");
977 cnt = d->config_cached;
978 if (opt_hex >= 3 && config_fetch(d, cnt, 256-cnt))
981 if (opt_hex >= 4 && config_fetch(d, 256, 4096-256))
985 for (i=0; i<cnt; i++)
989 printf(" %02x", get_conf_byte(d, i));
996 print_shell_escaped(char *c)
1001 if (*c == '"' || *c == '\\')
1009 show_machine(struct device *d)
1011 struct pci_dev *p = d->dev;
1012 char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
1013 char *dt_node, *iommu_group;
1017 pci_fill_info(p, PCI_FILL_PHYS_SLOT | PCI_FILL_NUMA_NODE | PCI_FILL_DT_NODE | PCI_FILL_IOMMU_GROUP);
1018 printf((opt_machine >= 2) ? "Slot:\t" : "Device:\t");
1021 printf("Class:\t%s\n",
1022 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
1023 printf("Vendor:\t%s\n",
1024 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
1025 printf("Device:\t%s\n",
1026 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
1027 if ((p->known_fields & PCI_FILL_SUBSYS) &&
1028 p->subsys_vendor_id && p->subsys_vendor_id != 0xffff)
1030 printf("SVendor:\t%s\n",
1031 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, p->subsys_vendor_id));
1032 printf("SDevice:\t%s\n",
1033 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, p->subsys_vendor_id, p->subsys_id));
1036 printf("PhySlot:\t%s\n", p->phy_slot);
1037 if ((p->known_fields & PCI_FILL_CLASS_EXT) && p->rev_id)
1038 printf("Rev:\t%02x\n", p->rev_id);
1039 if (p->known_fields & PCI_FILL_CLASS_EXT)
1040 printf("ProgIf:\t%02x\n", p->prog_if);
1042 show_kernel_machine(d);
1043 if (p->numa_node != -1)
1044 printf("NUMANode:\t%d\n", p->numa_node);
1045 if (dt_node = pci_get_string_property(p, PCI_FILL_DT_NODE))
1046 printf("DTNode:\t%s\n", dt_node);
1047 if (iommu_group = pci_get_string_property(p, PCI_FILL_IOMMU_GROUP))
1048 printf("IOMMUGroup:\t%s\n", iommu_group);
1053 print_shell_escaped(pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
1054 print_shell_escaped(pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
1055 print_shell_escaped(pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
1056 if ((p->known_fields & PCI_FILL_CLASS_EXT) && p->rev_id)
1057 printf(" -r%02x", p->rev_id);
1058 if (p->known_fields & PCI_FILL_CLASS_EXT)
1059 printf(" -p%02x", p->prog_if);
1060 if ((p->known_fields & PCI_FILL_SUBSYS) &&
1061 p->subsys_vendor_id && p->subsys_vendor_id != 0xffff)
1063 print_shell_escaped(pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, p->subsys_vendor_id));
1064 print_shell_escaped(pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, p->subsys_vendor_id, p->subsys_id));
1067 printf(" \"\" \"\"");
1072 /*** Main show function ***/
1075 show_device(struct device *d)
1085 if (opt_kernel || verbose)
1090 if (verbose || opt_hex)
1099 for (d=first_dev; d; d=d->next)
1100 if (pci_filter_match(&filter, d->dev))
1107 main(int argc, char **argv)
1112 if (argc == 2 && !strcmp(argv[1], "--version"))
1114 puts("lspci version " PCIUTILS_VERSION);
1120 pci_filter_init(pacc, &filter);
1122 while ((i = getopt(argc, argv, options)) != -1)
1126 pacc->numeric_ids++;
1132 pacc->buscentric = 1;
1135 if (msg = pci_filter_parse_slot(&filter, optarg))
1140 if (msg = pci_filter_parse_id(&filter, optarg))
1156 pci_set_name_list_path(pacc, optarg, 0);
1162 opt_pcimap = optarg;
1185 die("DNS queries are not available in this version");
1188 if (parse_generic_option(i, pacc, optarg))
1191 fprintf(stderr, help_msg, pacc->id_file_name);
1199 pacc->id_lookup_mode |= PCI_LOOKUP_NETWORK;
1200 if (opt_query_dns > 1)
1201 pacc->id_lookup_mode |= PCI_LOOKUP_REFRESH_CACHE;
1204 pacc->id_lookup_mode |= PCI_LOOKUP_NETWORK | PCI_LOOKUP_SKIP_LOCAL;
1210 die("Bus mapping mode does not recognize bus topology");
1220 show_forest(opt_filter ? &filter : NULL);
1224 show_kernel_cleanup();
1227 return (seen_errors ? 2 : 0);