2 * The PCI Utilities -- List All PCI Devices
4 * Copyright (c) 1997--2007 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
19 static int verbose; /* Show detailed information */
20 static int opt_buscentric; /* Show bus addresses/IRQ's instead of CPU-visible ones */
21 static int opt_hex; /* Show contents of config space as hexadecimal numbers */
22 static struct pci_filter filter; /* Device filter */
23 static int opt_tree; /* Show bus tree */
24 static int opt_machine; /* Generate machine-readable output */
25 static int opt_map_mode; /* Bus mapping mode enabled */
26 static int opt_domains; /* Show domain numbers (0=disabled, 1=auto-detected, 2=requested) */
27 static int opt_kernel; /* Show kernel drivers */
28 static char *opt_pcimap; /* Override path to Linux modules.pcimap */
30 const char program_name[] = "lspci";
32 static char options[] = "nvbxs:d:ti:mgp:kMD" GENERIC_OPTIONS ;
34 static char help_msg[] =
35 "Usage: lspci [<switches>]\n"
38 "-n\t\tShow numeric ID's\n"
39 "-nn\t\tShow both textual and numeric ID's (names & numbers)\n"
40 "-b\t\tBus-centric view (PCI addresses and IRQ's instead of those seen by the CPU)\n"
41 "-x\t\tShow hex-dump of the standard portion of config space\n"
42 "-xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n"
43 "-xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n"
44 "-s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n"
45 "-d [<vendor>]:[<device>]\tShow only selected devices\n"
46 "-t\t\tShow bus tree\n"
47 "-m\t\tProduce machine-readable output\n"
48 "-i <file>\tUse specified ID database instead of %s\n"
50 "-k\t\tShow kernel drivers handling each device\n"
51 "-p <file>\tLook up kernel modules in a given file instead of default modules.pcimap\n"
53 "-D\t\tAlways show domain numbers\n"
54 "-M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
58 /*** Communication with libpci ***/
60 static struct pci_access *pacc;
63 * If we aren't being compiled by GCC, use xmalloc() instead of alloca().
64 * This increases our memory footprint, but only slightly since we don't
67 #if defined (__FreeBSD__) || defined (__NetBSD__) || defined (__OpenBSD__) || defined (__DragonFly__)
68 /* alloca() is defined in stdlib.h */
69 #elif defined(__GNUC__) && !defined(PCI_OS_WINDOWS)
73 #define alloca xmalloc
76 /*** Our view of the PCI bus ***/
81 unsigned int config_cached, config_bufsize;
82 byte *config; /* Cached configuration space data */
83 byte *present; /* Maps which configuration bytes are present */
86 static struct device *first_dev;
87 static int seen_errors;
90 config_fetch(struct device *d, unsigned int pos, unsigned int len)
92 unsigned int end = pos+len;
95 while (pos < d->config_bufsize && len && d->present[pos])
97 while (pos+len <= d->config_bufsize && len && d->present[pos+len-1])
102 if (end > d->config_bufsize)
104 int orig_size = d->config_bufsize;
105 while (end > d->config_bufsize)
106 d->config_bufsize *= 2;
107 d->config = xrealloc(d->config, d->config_bufsize);
108 d->present = xrealloc(d->present, d->config_bufsize);
109 memset(d->present + orig_size, 0, d->config_bufsize - orig_size);
111 result = pci_read_block(d->dev, pos, d->config + pos, len);
113 memset(d->present + pos, 1, len);
117 static struct device *
118 scan_device(struct pci_dev *p)
122 if (p->domain && !opt_domains)
124 if (!pci_filter_match(&filter, p))
126 d = xmalloc(sizeof(struct device));
127 memset(d, 0, sizeof(*d));
129 d->config_cached = d->config_bufsize = 64;
130 d->config = xmalloc(64);
131 d->present = xmalloc(64);
132 memset(d->present, 1, 64);
133 if (!pci_read_block(p, 0, d->config, 64))
135 fprintf(stderr, "lspci: Unable to read the standard configuration space header of device %04x:%02x:%02x.%d\n",
136 p->domain, p->bus, p->dev, p->func);
140 if ((d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
142 /* For cardbus bridges, we need to fetch 64 bytes more to get the
143 * full standard header... */
144 if (config_fetch(d, 64, 64))
145 d->config_cached += 64;
147 pci_setup_cache(p, d->config, d->config_cached);
148 pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_CLASS | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
159 for(p=pacc->devices; p; p=p->next)
160 if (d = scan_device(p))
167 /*** Config space accesses ***/
170 check_conf_range(struct device *d, unsigned int pos, unsigned int len)
173 if (!d->present[pos])
174 die("Internal bug: Accessing non-read configuration byte at position %x", pos);
180 get_conf_byte(struct device *d, unsigned int pos)
182 check_conf_range(d, pos, 1);
183 return d->config[pos];
187 get_conf_word(struct device *d, unsigned int pos)
189 check_conf_range(d, pos, 2);
190 return d->config[pos] | (d->config[pos+1] << 8);
194 get_conf_long(struct device *d, unsigned int pos)
196 check_conf_range(d, pos, 4);
197 return d->config[pos] |
198 (d->config[pos+1] << 8) |
199 (d->config[pos+2] << 16) |
200 (d->config[pos+3] << 24);
206 compare_them(const void *A, const void *B)
208 const struct pci_dev *a = (*(const struct device **)A)->dev;
209 const struct pci_dev *b = (*(const struct device **)B)->dev;
211 if (a->domain < b->domain)
213 if (a->domain > b->domain)
223 if (a->func < b->func)
225 if (a->func > b->func)
233 struct device **index, **h, **last_dev;
238 for(d=first_dev; d; d=d->next)
240 h = index = alloca(sizeof(struct device *) * cnt);
241 for(d=first_dev; d; d=d->next)
243 qsort(index, cnt, sizeof(struct device *), compare_them);
244 last_dev = &first_dev;
249 last_dev = &(*h)->next;
255 /*** Normal output ***/
257 #define FLAG(x,y) ((x & y) ? '+' : '-')
260 show_slot_name(struct device *d)
262 struct pci_dev *p = d->dev;
264 if (!opt_machine ? opt_domains : (p->domain || opt_domains >= 2))
265 printf("%04x:", p->domain);
266 printf("%02x:%02x.%d", p->bus, p->dev, p->func);
270 show_terse(struct device *d)
273 struct pci_dev *p = d->dev;
274 char classbuf[128], devbuf[128];
278 pci_lookup_name(pacc, classbuf, sizeof(classbuf),
281 pci_lookup_name(pacc, devbuf, sizeof(devbuf),
282 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
283 p->vendor_id, p->device_id));
284 if (c = get_conf_byte(d, PCI_REVISION_ID))
285 printf(" (rev %02x)", c);
289 c = get_conf_byte(d, PCI_CLASS_PROG);
290 x = pci_lookup_name(pacc, devbuf, sizeof(devbuf),
291 PCI_LOOKUP_PROGIF | PCI_LOOKUP_NO_NUMBERS,
295 printf(" (prog-if %02x", c);
305 get_subid(struct device *d, word *subvp, word *subdp)
307 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
309 if (htype == PCI_HEADER_TYPE_NORMAL)
311 *subvp = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
312 *subdp = get_conf_word(d, PCI_SUBSYSTEM_ID);
314 else if (htype == PCI_HEADER_TYPE_CARDBUS && d->config_cached >= 128)
316 *subvp = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
317 *subdp = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
320 *subvp = *subdp = 0xffff;
323 /*** Capabilities ***/
326 cap_pm(struct device *d, int where, int cap)
329 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
331 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
334 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
335 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
336 FLAG(cap, PCI_PM_CAP_DSI),
337 FLAG(cap, PCI_PM_CAP_D1),
338 FLAG(cap, PCI_PM_CAP_D2),
339 pm_aux_current[(cap >> 6) & 7],
340 FLAG(cap, PCI_PM_CAP_PME_D0),
341 FLAG(cap, PCI_PM_CAP_PME_D1),
342 FLAG(cap, PCI_PM_CAP_PME_D2),
343 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
344 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
345 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
347 t = get_conf_word(d, where + PCI_PM_CTRL);
348 printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
349 t & PCI_PM_CTRL_STATE_MASK,
350 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
351 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
352 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
353 FLAG(t, PCI_PM_CTRL_PME_STATUS));
354 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
356 printf("\t\tBridge: PM%c B3%c\n",
357 FLAG(t, PCI_PM_BPCC_ENABLE),
358 FLAG(~t, PCI_PM_PPB_B2_B3));
362 format_agp_rate(int rate, char *buf, int agp3)
372 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
377 strcpy(buf, "<none>");
381 cap_agp(struct device *d, int where, int cap)
388 ver = (cap >> 4) & 0x0f;
390 printf("AGP version %x.%x\n", ver, rev);
393 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
395 t = get_conf_long(d, where + PCI_AGP_STATUS);
396 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
398 format_agp_rate(t & 7, rate, agp3);
399 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
400 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
401 FLAG(t, PCI_AGP_STATUS_ISOCH),
402 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
403 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
404 FLAG(t, PCI_AGP_STATUS_SBA),
405 FLAG(t, PCI_AGP_STATUS_ITA_COH),
406 FLAG(t, PCI_AGP_STATUS_GART64),
407 FLAG(t, PCI_AGP_STATUS_HTRANS),
408 FLAG(t, PCI_AGP_STATUS_64BIT),
409 FLAG(t, PCI_AGP_STATUS_FW),
410 FLAG(t, PCI_AGP_STATUS_AGP3),
412 t = get_conf_long(d, where + PCI_AGP_COMMAND);
413 format_agp_rate(t & 7, rate, agp3);
414 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
415 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
416 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
417 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
418 FLAG(t, PCI_AGP_COMMAND_SBA),
419 FLAG(t, PCI_AGP_COMMAND_AGP),
420 FLAG(t, PCI_AGP_COMMAND_GART64),
421 FLAG(t, PCI_AGP_COMMAND_64BIT),
422 FLAG(t, PCI_AGP_COMMAND_FW),
427 cap_pcix_nobridge(struct device *d, int where)
431 static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
433 printf("PCI-X non-bridge device\n");
438 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
441 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
442 status = get_conf_long(d, where + PCI_PCIX_STATUS);
443 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
444 FLAG(command, PCI_PCIX_COMMAND_DPERE),
445 FLAG(command, PCI_PCIX_COMMAND_ERO),
446 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
447 max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
448 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
449 ((status >> 8) & 0xff),
450 ((status >> 3) & 0x1f),
451 (status & PCI_PCIX_STATUS_FUNCTION),
452 FLAG(status, PCI_PCIX_STATUS_64BIT),
453 FLAG(status, PCI_PCIX_STATUS_133MHZ),
454 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
455 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
456 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
457 1 << (9 + ((status >> 21) & 3U)),
458 max_outstanding[(status >> 23) & 7U],
459 1 << (3 + ((status >> 26) & 7U)),
460 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
461 FLAG(status, PCI_PCIX_STATUS_266MHZ),
462 FLAG(status, PCI_PCIX_STATUS_533MHZ));
466 cap_pcix_bridge(struct device *d, int where)
468 static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
470 u32 status, upstcr, downstcr;
472 printf("PCI-X bridge device\n");
477 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
480 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
481 printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
482 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
483 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
484 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
485 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
486 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
487 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
488 sec_clock_freq[(secstatus >> 6) & 7]);
489 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
490 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
491 ((status >> 8) & 0xff),
492 ((status >> 3) & 0x1f),
493 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
494 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
495 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
496 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
497 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
498 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
499 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
500 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
501 printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
502 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
503 (upstcr >> 16) & 0xffff);
504 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
505 printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
506 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
507 (downstcr >> 16) & 0xffff);
511 cap_pcix(struct device *d, int where)
513 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
515 case PCI_HEADER_TYPE_NORMAL:
516 cap_pcix_nobridge(d, where);
518 case PCI_HEADER_TYPE_BRIDGE:
519 cap_pcix_bridge(d, where);
525 ht_link_width(unsigned width)
527 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
528 return widths[width];
532 ht_link_freq(unsigned freq)
534 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
535 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
540 cap_ht_pri(struct device *d, int where, int cmd)
542 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
543 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
546 printf("HyperTransport: Slave or Primary Interface\n");
550 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
552 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
553 if (rid < 0x23 && rid > 0x11)
554 printf("\t\t!!! Possibly incomplete decoding\n");
557 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
559 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
561 (cmd & PCI_HT_PRI_CMD_BUID),
562 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
563 FLAG(cmd, PCI_HT_PRI_CMD_MH),
564 FLAG(cmd, PCI_HT_PRI_CMD_DD),
565 FLAG(cmd, PCI_HT_PRI_CMD_DUL));
566 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
568 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
570 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
572 FLAG(lctr0, PCI_HT_LCTR_CFLE),
573 FLAG(lctr0, PCI_HT_LCTR_CST),
574 FLAG(lctr0, PCI_HT_LCTR_CFE),
575 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
576 FLAG(lctr0, PCI_HT_LCTR_INIT),
577 FLAG(lctr0, PCI_HT_LCTR_EOC),
578 FLAG(lctr0, PCI_HT_LCTR_TXO),
579 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
580 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
581 FLAG(lctr0, PCI_HT_LCTR_LSEN),
582 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
583 FLAG(lctr0, PCI_HT_LCTR_64B));
584 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
586 fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
588 fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
590 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
591 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
592 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
593 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
594 FLAG(lcnf0, PCI_HT_LCNF_DFI),
595 FLAG(lcnf0, PCI_HT_LCNF_DFO),
596 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
597 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
598 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
600 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
602 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
604 FLAG(lctr1, PCI_HT_LCTR_CFLE),
605 FLAG(lctr1, PCI_HT_LCTR_CST),
606 FLAG(lctr1, PCI_HT_LCTR_CFE),
607 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
608 FLAG(lctr1, PCI_HT_LCTR_INIT),
609 FLAG(lctr1, PCI_HT_LCTR_EOC),
610 FLAG(lctr1, PCI_HT_LCTR_TXO),
611 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
612 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
613 FLAG(lctr1, PCI_HT_LCTR_LSEN),
614 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
615 FLAG(lctr1, PCI_HT_LCTR_64B));
616 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
618 fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
620 fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
622 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
623 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
624 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
625 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
626 FLAG(lcnf1, PCI_HT_LCNF_DFI),
627 FLAG(lcnf1, PCI_HT_LCNF_DFO),
628 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
629 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
630 printf("\t\tRevision ID: %u.%02u\n",
631 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
634 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
635 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
636 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
637 FLAG(lfrer0, PCI_HT_LFRER_PROT),
638 FLAG(lfrer0, PCI_HT_LFRER_OV),
639 FLAG(lfrer0, PCI_HT_LFRER_EOC),
640 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
641 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
642 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
643 FLAG(lfcap0, PCI_HT_LFCAP_200),
644 FLAG(lfcap0, PCI_HT_LFCAP_300),
645 FLAG(lfcap0, PCI_HT_LFCAP_400),
646 FLAG(lfcap0, PCI_HT_LFCAP_500),
647 FLAG(lfcap0, PCI_HT_LFCAP_600),
648 FLAG(lfcap0, PCI_HT_LFCAP_800),
649 FLAG(lfcap0, PCI_HT_LFCAP_1000),
650 FLAG(lfcap0, PCI_HT_LFCAP_1200),
651 FLAG(lfcap0, PCI_HT_LFCAP_1400),
652 FLAG(lfcap0, PCI_HT_LFCAP_1600),
653 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
654 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
655 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
656 FLAG(ftr, PCI_HT_FTR_ISOCFC),
657 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
658 FLAG(ftr, PCI_HT_FTR_CRCTM),
659 FLAG(ftr, PCI_HT_FTR_ECTLT),
660 FLAG(ftr, PCI_HT_FTR_64BA),
661 FLAG(ftr, PCI_HT_FTR_UIDRD));
662 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
663 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
664 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
665 FLAG(lfrer1, PCI_HT_LFRER_PROT),
666 FLAG(lfrer1, PCI_HT_LFRER_OV),
667 FLAG(lfrer1, PCI_HT_LFRER_EOC),
668 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
669 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
670 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
671 FLAG(lfcap1, PCI_HT_LFCAP_200),
672 FLAG(lfcap1, PCI_HT_LFCAP_300),
673 FLAG(lfcap1, PCI_HT_LFCAP_400),
674 FLAG(lfcap1, PCI_HT_LFCAP_500),
675 FLAG(lfcap1, PCI_HT_LFCAP_600),
676 FLAG(lfcap1, PCI_HT_LFCAP_800),
677 FLAG(lfcap1, PCI_HT_LFCAP_1000),
678 FLAG(lfcap1, PCI_HT_LFCAP_1200),
679 FLAG(lfcap1, PCI_HT_LFCAP_1400),
680 FLAG(lfcap1, PCI_HT_LFCAP_1600),
681 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
682 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
683 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
684 FLAG(eh, PCI_HT_EH_PFLE),
685 FLAG(eh, PCI_HT_EH_OFLE),
686 FLAG(eh, PCI_HT_EH_PFE),
687 FLAG(eh, PCI_HT_EH_OFE),
688 FLAG(eh, PCI_HT_EH_EOCFE),
689 FLAG(eh, PCI_HT_EH_RFE),
690 FLAG(eh, PCI_HT_EH_CRCFE),
691 FLAG(eh, PCI_HT_EH_SERRFE),
692 FLAG(eh, PCI_HT_EH_CF),
693 FLAG(eh, PCI_HT_EH_RE),
694 FLAG(eh, PCI_HT_EH_PNFE),
695 FLAG(eh, PCI_HT_EH_ONFE),
696 FLAG(eh, PCI_HT_EH_EOCNFE),
697 FLAG(eh, PCI_HT_EH_RNFE),
698 FLAG(eh, PCI_HT_EH_CRCNFE),
699 FLAG(eh, PCI_HT_EH_SERRNFE));
700 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
701 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
702 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
703 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
704 printf("\t\tBus Number: %02x\n", bn);
708 cap_ht_sec(struct device *d, int where, int cmd)
710 u16 lctr, lcnf, ftr, eh;
711 u8 rid, lfrer, lfcap, mbu, mlu;
714 printf("HyperTransport: Host or Secondary Interface\n");
718 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
720 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
721 if (rid < 0x23 && rid > 0x11)
722 printf("\t\t!!! Possibly incomplete decoding\n");
725 fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
727 fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
729 FLAG(cmd, PCI_HT_SEC_CMD_WR),
730 FLAG(cmd, PCI_HT_SEC_CMD_DE),
731 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
732 FLAG(cmd, PCI_HT_SEC_CMD_CS),
733 FLAG(cmd, PCI_HT_SEC_CMD_HH),
734 FLAG(cmd, PCI_HT_SEC_CMD_AS),
735 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
736 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
737 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
739 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
741 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
743 FLAG(lctr, PCI_HT_LCTR_CFLE),
744 FLAG(lctr, PCI_HT_LCTR_CST),
745 FLAG(lctr, PCI_HT_LCTR_CFE),
746 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
747 FLAG(lctr, PCI_HT_LCTR_INIT),
748 FLAG(lctr, PCI_HT_LCTR_EOC),
749 FLAG(lctr, PCI_HT_LCTR_TXO),
750 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
751 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
752 FLAG(lctr, PCI_HT_LCTR_LSEN),
753 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
754 FLAG(lctr, PCI_HT_LCTR_64B));
755 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
757 fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
759 fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
761 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
762 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
763 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
764 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
765 FLAG(lcnf, PCI_HT_LCNF_DFI),
766 FLAG(lcnf, PCI_HT_LCNF_DFO),
767 FLAG(lcnf, PCI_HT_LCNF_DFIE),
768 FLAG(lcnf, PCI_HT_LCNF_DFOE));
769 printf("\t\tRevision ID: %u.%02u\n",
770 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
773 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
774 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
775 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
776 FLAG(lfrer, PCI_HT_LFRER_PROT),
777 FLAG(lfrer, PCI_HT_LFRER_OV),
778 FLAG(lfrer, PCI_HT_LFRER_EOC),
779 FLAG(lfrer, PCI_HT_LFRER_CTLT));
780 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
781 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
782 FLAG(lfcap, PCI_HT_LFCAP_200),
783 FLAG(lfcap, PCI_HT_LFCAP_300),
784 FLAG(lfcap, PCI_HT_LFCAP_400),
785 FLAG(lfcap, PCI_HT_LFCAP_500),
786 FLAG(lfcap, PCI_HT_LFCAP_600),
787 FLAG(lfcap, PCI_HT_LFCAP_800),
788 FLAG(lfcap, PCI_HT_LFCAP_1000),
789 FLAG(lfcap, PCI_HT_LFCAP_1200),
790 FLAG(lfcap, PCI_HT_LFCAP_1400),
791 FLAG(lfcap, PCI_HT_LFCAP_1600),
792 FLAG(lfcap, PCI_HT_LFCAP_VEND));
793 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
794 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
795 FLAG(ftr, PCI_HT_FTR_ISOCFC),
796 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
797 FLAG(ftr, PCI_HT_FTR_CRCTM),
798 FLAG(ftr, PCI_HT_FTR_ECTLT),
799 FLAG(ftr, PCI_HT_FTR_64BA),
800 FLAG(ftr, PCI_HT_FTR_UIDRD),
801 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
802 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
803 if (ftr & PCI_HT_SEC_FTR_EXTRS)
805 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
806 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
807 FLAG(eh, PCI_HT_EH_PFLE),
808 FLAG(eh, PCI_HT_EH_OFLE),
809 FLAG(eh, PCI_HT_EH_PFE),
810 FLAG(eh, PCI_HT_EH_OFE),
811 FLAG(eh, PCI_HT_EH_EOCFE),
812 FLAG(eh, PCI_HT_EH_RFE),
813 FLAG(eh, PCI_HT_EH_CRCFE),
814 FLAG(eh, PCI_HT_EH_SERRFE),
815 FLAG(eh, PCI_HT_EH_CF),
816 FLAG(eh, PCI_HT_EH_RE),
817 FLAG(eh, PCI_HT_EH_PNFE),
818 FLAG(eh, PCI_HT_EH_ONFE),
819 FLAG(eh, PCI_HT_EH_EOCNFE),
820 FLAG(eh, PCI_HT_EH_RNFE),
821 FLAG(eh, PCI_HT_EH_CRCNFE),
822 FLAG(eh, PCI_HT_EH_SERRNFE));
823 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
824 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
825 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
830 cap_ht(struct device *d, int where, int cmd)
834 switch (cmd & PCI_HT_CMD_TYP_HI)
836 case PCI_HT_CMD_TYP_HI_PRI:
837 cap_ht_pri(d, where, cmd);
839 case PCI_HT_CMD_TYP_HI_SEC:
840 cap_ht_sec(d, where, cmd);
844 type = cmd & PCI_HT_CMD_TYP;
847 case PCI_HT_CMD_TYP_SW:
848 printf("HyperTransport: Switch\n");
850 case PCI_HT_CMD_TYP_IDC:
851 printf("HyperTransport: Interrupt Discovery and Configuration\n");
853 case PCI_HT_CMD_TYP_RID:
854 printf("HyperTransport: Revision ID: %u.%02u\n",
855 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
857 case PCI_HT_CMD_TYP_UIDC:
858 printf("HyperTransport: UnitID Clumping\n");
860 case PCI_HT_CMD_TYP_ECSA:
861 printf("HyperTransport: Extended Configuration Space Access\n");
863 case PCI_HT_CMD_TYP_AM:
864 printf("HyperTransport: Address Mapping\n");
866 case PCI_HT_CMD_TYP_MSIM:
867 printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
868 FLAG(cmd, PCI_HT_MSIM_CMD_EN),
869 FLAG(cmd, PCI_HT_MSIM_CMD_FIXD));
870 if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD))
873 if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8))
875 offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
876 offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
877 printf("\t\tMapping Address Base: %016llx\n", ((unsigned long long)offh << 32) | (offl & ~0xfffff));
880 case PCI_HT_CMD_TYP_DR:
881 printf("HyperTransport: DirectRoute\n");
883 case PCI_HT_CMD_TYP_VCS:
884 printf("HyperTransport: VCSet\n");
886 case PCI_HT_CMD_TYP_RM:
887 printf("HyperTransport: Retry Mode\n");
889 case PCI_HT_CMD_TYP_X86:
890 printf("HyperTransport: X86 (reserved)\n");
893 printf("HyperTransport: #%02x\n", type >> 11);
898 cap_msi(struct device *d, int where, int cap)
904 printf("Message Signalled Interrupts: Mask%c 64bit%c Queue=%d/%d Enable%c\n",
905 FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
906 FLAG(cap, PCI_MSI_FLAGS_64BIT),
907 (cap & PCI_MSI_FLAGS_QSIZE) >> 4,
908 (cap & PCI_MSI_FLAGS_QMASK) >> 1,
909 FLAG(cap, PCI_MSI_FLAGS_ENABLE));
912 is64 = cap & PCI_MSI_FLAGS_64BIT;
913 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
915 printf("\t\tAddress: ");
918 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
919 w = get_conf_word(d, where + PCI_MSI_DATA_64);
923 w = get_conf_word(d, where + PCI_MSI_DATA_32);
924 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
925 printf("%08x Data: %04x\n", t, w);
926 if (cap & PCI_MSI_FLAGS_MASK_BIT)
932 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
934 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
935 pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
939 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
941 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
942 pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
944 printf("\t\tMasking: %08x Pending: %08x\n", mask, pending);
948 static float power_limit(int value, int scale)
950 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
951 return value * scales[scale];
954 static const char *latency_l0s(int value)
956 static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
957 return latencies[value];
960 static const char *latency_l1(int value)
962 static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
963 return latencies[value];
966 static void cap_express_dev(struct device *d, int where, int type)
971 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
972 printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d, Latency L0s %s, L1 %s\n",
973 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
974 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
975 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
976 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
977 printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
978 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
979 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
980 printf(" AttnBtn%c AttnInd%c PwrInd%c",
981 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
982 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
983 printf(" RBE%c FLReset%c",
984 FLAG(t, PCI_EXP_DEVCAP_RBE),
985 FLAG(t, PCI_EXP_DEVCAP_FLRESET));
986 if (type == PCI_EXP_TYPE_UPSTREAM)
987 printf("SlotPowerLimit %fW",
988 power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
989 (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
992 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
993 printf("\t\tDevCtl:\tReport errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
994 FLAG(w, PCI_EXP_DEVCTL_CERE),
995 FLAG(w, PCI_EXP_DEVCTL_NFERE),
996 FLAG(w, PCI_EXP_DEVCTL_FERE),
997 FLAG(w, PCI_EXP_DEVCTL_URRE));
998 printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
999 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
1000 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
1001 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
1002 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
1003 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
1004 if (type == PCI_EXP_TYPE_PCI_BRIDGE || type == PCI_EXP_TYPE_PCIE_BRIDGE)
1005 printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
1006 if (type == PCI_EXP_TYPE_ENDPOINT && (t & PCI_EXP_DEVCAP_FLRESET))
1007 printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
1008 printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
1009 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
1010 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
1012 w = get_conf_word(d, where + PCI_EXP_DEVSTA);
1013 printf("\t\tDevSta:\tCorrErr%c UncorrErr%c FatalErr%c UnsuppReq%c AuxPwr%c TransPend%c\n",
1014 FLAG(w, PCI_EXP_DEVSTA_CED),
1015 FLAG(w, PCI_EXP_DEVSTA_NFED),
1016 FLAG(w, PCI_EXP_DEVSTA_FED),
1017 FLAG(w, PCI_EXP_DEVSTA_URD),
1018 FLAG(w, PCI_EXP_DEVSTA_AUXPD),
1019 FLAG(w, PCI_EXP_DEVSTA_TRPND));
1021 /* FIXME: Second set of control/status registers is not supported yet. */
1024 static char *link_speed(int speed)
1037 static char *aspm_support(int code)
1050 static const char *aspm_enabled(int code)
1052 static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
1056 static void cap_express_link(struct device *d, int where, int type)
1061 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
1062 printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s, Latency L0 %s, L1 %s\n",
1064 link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
1065 aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
1066 latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
1067 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
1068 printf("\t\t\tClockPM%c Suprise%c LLActRep%c BwNot%c\n",
1069 FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
1070 FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
1071 FLAG(t, PCI_EXP_LNKCAP_DLLA),
1072 FLAG(t, PCI_EXP_LNKCAP_LBNC));
1074 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
1075 printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
1076 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
1077 (type == PCI_EXP_TYPE_LEG_END))
1078 printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
1079 printf(" Disabled%c Retrain%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
1080 FLAG(w, PCI_EXP_LNKCTL_DISABLE),
1081 FLAG(w, PCI_EXP_LNKCTL_RETRAIN),
1082 FLAG(w, PCI_EXP_LNKCTL_CLOCK),
1083 FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
1084 FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
1085 FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
1086 FLAG(w, PCI_EXP_LNKCTL_BWMIE),
1087 FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
1089 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
1090 printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
1091 link_speed(w & PCI_EXP_LNKSTA_SPEED),
1092 (w & PCI_EXP_LNKSTA_WIDTH) >> 4,
1093 FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
1094 FLAG(w, PCI_EXP_LNKSTA_TRAIN),
1095 FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
1096 FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
1097 FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
1098 FLAG(w, PCI_EXP_LNKSTA_AUTBW));
1101 static const char *indicator(int code)
1103 static const char *names[] = { "Unknown", "On", "Blink", "Off" };
1107 static void cap_express_slot(struct device *d, int where)
1112 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
1113 printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surpise%c\n",
1114 FLAG(t, PCI_EXP_SLTCAP_ATNB),
1115 FLAG(t, PCI_EXP_SLTCAP_PWRC),
1116 FLAG(t, PCI_EXP_SLTCAP_MRL),
1117 FLAG(t, PCI_EXP_SLTCAP_ATNI),
1118 FLAG(t, PCI_EXP_SLTCAP_PWRI),
1119 FLAG(t, PCI_EXP_SLTCAP_HPC),
1120 FLAG(t, PCI_EXP_SLTCAP_HPS));
1121 printf("\t\t\tSlot #%3x, PowerLimit %f; Interlock%c NoCompl%c\n",
1123 power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
1124 FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
1125 FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
1127 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
1128 printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
1129 FLAG(w, PCI_EXP_SLTCTL_ATNB),
1130 FLAG(w, PCI_EXP_SLTCTL_PWRF),
1131 FLAG(w, PCI_EXP_SLTCTL_MRLS),
1132 FLAG(w, PCI_EXP_SLTCTL_PRSD),
1133 FLAG(w, PCI_EXP_SLTCTL_CMDC),
1134 FLAG(w, PCI_EXP_SLTCTL_HPIE),
1135 FLAG(w, PCI_EXP_SLTCTL_LLCHG));
1136 printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
1137 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
1138 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
1139 FLAG(w, PCI_EXP_SLTCTL_PWRC),
1140 FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
1142 w = get_conf_word(d, where + PCI_EXP_SLTSTA);
1143 printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
1144 FLAG(w, PCI_EXP_SLTSTA_ATNB),
1145 FLAG(w, PCI_EXP_SLTSTA_PWRF),
1146 FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
1147 FLAG(w, PCI_EXP_SLTSTA_CMDC),
1148 FLAG(w, PCI_EXP_SLTSTA_PRES),
1149 FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
1150 printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
1151 FLAG(w, PCI_EXP_SLTSTA_MRLS),
1152 FLAG(w, PCI_EXP_SLTSTA_PRSD),
1153 FLAG(w, PCI_EXP_SLTSTA_LLCHG));
1156 static void cap_express_root(struct device *d, int where)
1158 u32 w = get_conf_word(d, where + PCI_EXP_RTCTL);
1159 printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
1160 FLAG(w, PCI_EXP_RTCTL_SECEE),
1161 FLAG(w, PCI_EXP_RTCTL_SENFEE),
1162 FLAG(w, PCI_EXP_RTCTL_SEFEE),
1163 FLAG(w, PCI_EXP_RTCTL_PMEIE),
1164 FLAG(w, PCI_EXP_RTCTL_CRSVIS));
1166 w = get_conf_word(d, where + PCI_EXP_RTCAP);
1167 printf("\t\tRootCap: CRSVisible%c\n",
1168 FLAG(w, PCI_EXP_RTCAP_CRSVIS));
1170 w = get_conf_word(d, where + PCI_EXP_RTSTA);
1171 printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
1172 w & PCI_EXP_RTSTA_PME_REQID,
1173 FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
1174 FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
1178 cap_express(struct device *d, int where, int cap)
1180 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1186 printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
1189 case PCI_EXP_TYPE_ENDPOINT:
1192 case PCI_EXP_TYPE_LEG_END:
1193 printf("Legacy Endpoint");
1195 case PCI_EXP_TYPE_ROOT_PORT:
1196 slot = cap & PCI_EXP_FLAGS_SLOT;
1197 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1199 case PCI_EXP_TYPE_UPSTREAM:
1200 printf("Upstream Port");
1202 case PCI_EXP_TYPE_DOWNSTREAM:
1203 slot = cap & PCI_EXP_FLAGS_SLOT;
1204 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1206 case PCI_EXP_TYPE_PCI_BRIDGE:
1207 printf("PCI/PCI-X Bridge");
1209 case PCI_EXP_TYPE_PCIE_BRIDGE:
1210 printf("PCI/PCI-X to PCI-Express Bridge");
1212 case PCI_EXP_TYPE_ROOT_INT_EP:
1213 printf("Root Complex Integrated Endpoint");
1215 case PCI_EXP_TYPE_ROOT_EC:
1216 printf("Root Complex Event Collector");
1219 printf("Unknown type %d", type);
1221 printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1228 if (type == PCI_EXP_TYPE_ROOT_PORT)
1230 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1233 cap_express_dev(d, where, type);
1234 cap_express_link(d, where, type);
1236 cap_express_slot(d, where);
1237 if (type == PCI_EXP_TYPE_ROOT_PORT)
1238 cap_express_root(d, where);
1242 cap_msix(struct device *d, int where, int cap)
1246 printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
1247 FLAG(cap, PCI_MSIX_ENABLE),
1248 FLAG(cap, PCI_MSIX_MASK),
1249 (cap & PCI_MSIX_TABSIZE) + 1);
1250 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1253 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1254 printf("\t\tVector table: BAR=%d offset=%08x\n",
1255 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1256 off = get_conf_long(d, where + PCI_MSIX_PBA);
1257 printf("\t\tPBA: BAR=%d offset=%08x\n",
1258 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1264 int esr = cap & 0xff;
1267 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1268 esr & PCI_SID_ESR_NSLOTS,
1269 FLAG(esr, PCI_SID_ESR_FIC),
1274 cap_ssvid(struct device *d, int where)
1276 u16 subsys_v, subsys_d;
1277 char ssnamebuf[256];
1279 if (!config_fetch(d, where, 8))
1281 subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR);
1282 subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE);
1283 printf("Subsystem: %s\n",
1284 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1285 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1286 d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
1290 cap_dsn(struct device *d, int where)
1293 if (!config_fetch(d, where + 4, 8))
1295 t1 = get_conf_long(d, where + 4);
1296 t2 = get_conf_long(d, where + 8);
1297 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
1298 t1 & 0xff, (t1 >> 8) & 0xff, (t1 >> 16) & 0xff, t1 >> 24,
1299 t2 & 0xff, (t2 >> 8) & 0xff, (t2 >> 16) & 0xff, t2 >> 24);
1303 cap_debug_port(int cap)
1305 int bar = cap >> 13;
1306 int pos = cap & 0x1fff;
1307 printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
1311 show_ext_caps(struct device *d)
1314 char been_there[0x1000];
1315 memset(been_there, 0, 0x1000);
1321 if (!config_fetch(d, where, 4))
1323 header = get_conf_long(d, where);
1326 id = header & 0xffff;
1327 printf("\tCapabilities: [%03x] ", where);
1328 if (been_there[where]++)
1330 printf("<chain looped>\n");
1335 case PCI_EXT_CAP_ID_AER:
1336 printf("Advanced Error Reporting <?>\n");
1338 case PCI_EXT_CAP_ID_VC:
1339 printf("Virtual Channel <?>\n");
1341 case PCI_EXT_CAP_ID_DSN:
1344 case PCI_EXT_CAP_ID_PB:
1345 printf("Power Budgeting <?>\n");
1347 case PCI_EXT_CAP_ID_RCLINK:
1348 printf("Root Complex Link <?>\n");
1350 case PCI_EXT_CAP_ID_RCILINK:
1351 printf("Root Complex Internal Link <?>\n");
1353 case PCI_EXT_CAP_ID_RCECOLL:
1354 printf("Root Complex Event Collector <?>\n");
1356 case PCI_EXT_CAP_ID_MFVC:
1357 printf("Multi-Function Virtual Channel <?>\n");
1359 case PCI_EXT_CAP_ID_RBCB:
1360 printf("Root Bridge Control Block <?>\n");
1362 case PCI_EXT_CAP_ID_VNDR:
1363 printf("Vendor Specific Information <?>\n");
1365 case PCI_EXT_CAP_ID_ACS:
1366 printf("Access Controls <?>\n");
1369 printf("#%02x\n", id);
1372 where = header >> 20;
1377 show_caps(struct device *d)
1379 int can_have_ext_caps = 0;
1381 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1383 int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
1384 byte been_there[256];
1385 memset(been_there, 0, 256);
1389 printf("\tCapabilities: ");
1390 if (!config_fetch(d, where, 4))
1392 puts("<access denied>");
1395 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1396 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1397 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1398 printf("[%02x] ", where);
1399 if (been_there[where]++)
1401 printf("<chain looped>\n");
1406 printf("<chain broken>\n");
1412 cap_pm(d, where, cap);
1414 case PCI_CAP_ID_AGP:
1415 cap_agp(d, where, cap);
1417 case PCI_CAP_ID_VPD:
1418 printf("Vital Product Data <?>\n");
1420 case PCI_CAP_ID_SLOTID:
1423 case PCI_CAP_ID_MSI:
1424 cap_msi(d, where, cap);
1426 case PCI_CAP_ID_CHSWP:
1427 printf("CompactPCI hot-swap <?>\n");
1429 case PCI_CAP_ID_PCIX:
1431 can_have_ext_caps = 1;
1434 cap_ht(d, where, cap);
1436 case PCI_CAP_ID_VNDR:
1437 printf("Vendor Specific Information <?>\n");
1439 case PCI_CAP_ID_DBG:
1440 cap_debug_port(cap);
1442 case PCI_CAP_ID_CCRC:
1443 printf("CompactPCI central resource control <?>\n");
1445 case PCI_CAP_ID_HOTPLUG:
1446 printf("Hot-plug capable\n");
1448 case PCI_CAP_ID_SSVID:
1449 cap_ssvid(d, where);
1451 case PCI_CAP_ID_AGP3:
1452 printf("AGP3 <?>\n");
1454 case PCI_CAP_ID_SECURE:
1455 printf("Secure device <?>\n");
1457 case PCI_CAP_ID_EXP:
1458 cap_express(d, where, cap);
1459 can_have_ext_caps = 1;
1461 case PCI_CAP_ID_MSIX:
1462 cap_msix(d, where, cap);
1464 case PCI_CAP_ID_SATA:
1465 printf("SATA HBA <?>\n");
1468 printf("PCIe advanced features <?>\n");
1471 printf("#%02x [%04x]\n", id, cap);
1476 if (can_have_ext_caps)
1480 /*** Kernel drivers ***/
1484 #include <sys/utsname.h>
1486 struct pcimap_entry {
1487 struct pcimap_entry *next;
1488 unsigned int vendor, device;
1489 unsigned int subvendor, subdevice;
1490 unsigned int class, class_mask;
1494 static struct pcimap_entry *pcimap_head;
1499 static int tried_pcimap;
1501 char *name, line[1024];
1508 if (name = opt_pcimap)
1510 f = fopen(name, "r");
1512 die("Cannot open pcimap file %s: %m", name);
1516 if (uname(&uts) < 0)
1517 die("uname() failed: %m");
1518 name = alloca(64 + strlen(uts.release));
1519 sprintf(name, "/lib/modules/%s/modules.pcimap", uts.release);
1520 f = fopen(name, "r");
1525 while (fgets(line, sizeof(line), f))
1527 char *c = strchr(line, '\n');
1528 struct pcimap_entry *e;
1531 die("Unterminated or too long line in %s", name);
1533 if (!line[0] || line[0] == '#')
1537 while (*c && *c != ' ' && *c != '\t')
1540 continue; /* FIXME: Emit warnings! */
1543 e = xmalloc(sizeof(*e) + strlen(line));
1544 if (sscanf(c, "%i%i%i%i%i%i",
1545 &e->vendor, &e->device,
1546 &e->subvendor, &e->subdevice,
1547 &e->class, &e->class_mask) != 6)
1549 e->next = pcimap_head;
1551 strcpy(e->module, line);
1557 match_pcimap(struct device *d, struct pcimap_entry *e)
1559 struct pci_dev *dev = d->dev;
1560 unsigned int class = get_conf_long(d, PCI_REVISION_ID) >> 8;
1563 #define MATCH(x, y) ((y) > 0xffff || (x) == (y))
1564 get_subid(d, &subv, &subd);
1566 MATCH(dev->vendor_id, e->vendor) &&
1567 MATCH(dev->device_id, e->device) &&
1568 MATCH(subv, e->subvendor) &&
1569 MATCH(subd, e->subdevice) &&
1570 (class & e->class_mask) == e->class;
1574 #define DRIVER_BUF_SIZE 1024
1577 find_driver(struct device *d, char *buf)
1579 struct pci_dev *dev = d->dev;
1580 char *base = dev->access->method_params[PCI_ACCESS_SYS_BUS_PCI];
1581 char name[1024], *drv;
1584 if (dev->access->method != PCI_ACCESS_SYS_BUS_PCI)
1587 n = snprintf(name, sizeof(name), "%s/devices/%04x:%02x:%02x.%d/driver",
1588 base, dev->domain, dev->bus, dev->dev, dev->func);
1589 if (n < 0 || n >= (int)sizeof(name))
1590 die("show_driver: sysfs device name too long, why?");
1592 n = readlink(name, buf, DRIVER_BUF_SIZE);
1595 if (n >= DRIVER_BUF_SIZE)
1596 return "<name-too-long>";
1599 if (drv = strrchr(buf, '/'))
1606 show_kernel(struct device *d)
1608 char buf[DRIVER_BUF_SIZE];
1610 struct pcimap_entry *e, *last = NULL;
1612 if (driver = find_driver(d, buf))
1613 printf("\tKernel driver in use: %s\n", driver);
1616 for (e=pcimap_head; e; e=e->next)
1617 if (match_pcimap(d, e) && (!last || strcmp(last->module, e->module)))
1619 printf("%s %s", (last ? "," : "\tKernel modules:"), e->module);
1627 show_kernel_machine(struct device *d)
1629 char buf[DRIVER_BUF_SIZE];
1631 struct pcimap_entry *e, *last = NULL;
1633 if (driver = find_driver(d, buf))
1634 printf("Driver:\t%s\n", driver);
1637 for (e=pcimap_head; e; e=e->next)
1638 if (match_pcimap(d, e) && (!last || strcmp(last->module, e->module)))
1640 printf("Module:\t%s\n", e->module);
1648 show_kernel(struct device *d UNUSED)
1653 show_kernel_machine(struct device *d UNUSED)
1659 /*** Verbose output ***/
1662 show_size(pciaddr_t x)
1668 printf("%d", (int) x);
1669 else if (x < 1048576)
1670 printf("%dK", (int)(x / 1024));
1671 else if (x < 0x80000000)
1672 printf("%dM", (int)(x / 1048576));
1674 printf(PCIADDR_T_FMT, x);
1679 show_bases(struct device *d, int cnt)
1681 struct pci_dev *p = d->dev;
1682 word cmd = get_conf_word(d, PCI_COMMAND);
1685 for(i=0; i<cnt; i++)
1687 pciaddr_t pos = p->base_addr[i];
1688 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
1689 u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
1690 if (flg == 0xffffffff)
1692 if (!pos && !flg && !len)
1695 printf("\tRegion %d: ", i);
1698 if (pos && !flg) /* Reported by the OS, but not by the device */
1700 printf("[virtual] ");
1703 if (flg & PCI_BASE_ADDRESS_SPACE_IO)
1705 pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
1706 printf("I/O ports at ");
1708 printf(PCIADDR_PORT_FMT, a);
1709 else if (flg & PCI_BASE_ADDRESS_IO_MASK)
1710 printf("<ignored>");
1712 printf("<unassigned>");
1713 if (!(cmd & PCI_COMMAND_IO))
1714 printf(" [disabled]");
1718 int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
1719 pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
1723 printf("Memory at ");
1724 if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
1728 printf("<invalid-64bit-slot>");
1734 z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
1737 u32 y = a & 0xffffffff;
1739 printf("%08x%08x", z, y);
1741 printf("<unassigned>");
1749 printf(PCIADDR_T_FMT, a);
1751 printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
1753 printf(" (%s, %sprefetchable)",
1754 (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
1755 (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
1756 (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
1757 (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
1758 if (!(cmd & PCI_COMMAND_MEMORY))
1759 printf(" [disabled]");
1767 show_rom(struct device *d, int reg)
1769 struct pci_dev *p = d->dev;
1770 pciaddr_t rom = p->rom_base_addr;
1771 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
1772 u32 flg = get_conf_long(d, reg);
1773 word cmd = get_conf_word(d, PCI_COMMAND);
1775 if (!rom && !flg && !len)
1778 if ((rom & PCI_ROM_ADDRESS_MASK) && !(flg & PCI_ROM_ADDRESS_MASK))
1780 printf("[virtual] ");
1783 printf("Expansion ROM at ");
1784 if (rom & PCI_ROM_ADDRESS_MASK)
1785 printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
1786 else if (flg & PCI_ROM_ADDRESS_MASK)
1787 printf("<ignored>");
1789 printf("<unassigned>");
1790 if (!(flg & PCI_ROM_ADDRESS_ENABLE))
1791 printf(" [disabled]");
1792 else if (!(cmd & PCI_COMMAND_MEMORY))
1793 printf(" [disabled by cmd]");
1799 show_htype0(struct device *d)
1802 show_rom(d, PCI_ROM_ADDRESS);
1807 show_htype1(struct device *d)
1809 u32 io_base = get_conf_byte(d, PCI_IO_BASE);
1810 u32 io_limit = get_conf_byte(d, PCI_IO_LIMIT);
1811 u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
1812 u32 mem_base = get_conf_word(d, PCI_MEMORY_BASE);
1813 u32 mem_limit = get_conf_word(d, PCI_MEMORY_LIMIT);
1814 u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
1815 u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE);
1816 u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT);
1817 u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
1818 word sec_stat = get_conf_word(d, PCI_SEC_STATUS);
1819 word brc = get_conf_word(d, PCI_BRIDGE_CONTROL);
1820 int verb = verbose > 2;
1823 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1824 get_conf_byte(d, PCI_PRIMARY_BUS),
1825 get_conf_byte(d, PCI_SECONDARY_BUS),
1826 get_conf_byte(d, PCI_SUBORDINATE_BUS),
1827 get_conf_byte(d, PCI_SEC_LATENCY_TIMER));
1829 if (io_type != (io_limit & PCI_IO_RANGE_TYPE_MASK) ||
1830 (io_type != PCI_IO_RANGE_TYPE_16 && io_type != PCI_IO_RANGE_TYPE_32))
1831 printf("\t!!! Unknown I/O range types %x/%x\n", io_base, io_limit);
1834 io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
1835 io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
1836 if (io_type == PCI_IO_RANGE_TYPE_32)
1838 io_base |= (get_conf_word(d, PCI_IO_BASE_UPPER16) << 16);
1839 io_limit |= (get_conf_word(d, PCI_IO_LIMIT_UPPER16) << 16);
1841 if (io_base <= io_limit || verb)
1842 printf("\tI/O behind bridge: %08x-%08x\n", io_base, io_limit+0xfff);
1845 if (mem_type != (mem_limit & PCI_MEMORY_RANGE_TYPE_MASK) ||
1847 printf("\t!!! Unknown memory range types %x/%x\n", mem_base, mem_limit);
1850 mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
1851 mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
1852 if (mem_base <= mem_limit || verb)
1853 printf("\tMemory behind bridge: %08x-%08x\n", mem_base, mem_limit + 0xfffff);
1856 if (pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
1857 (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64))
1858 printf("\t!!! Unknown prefetchable memory range types %x/%x\n", pref_base, pref_limit);
1861 pref_base = (pref_base & PCI_PREF_RANGE_MASK) << 16;
1862 pref_limit = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
1863 if (pref_base <= pref_limit || verb)
1865 if (pref_type == PCI_PREF_RANGE_TYPE_32)
1866 printf("\tPrefetchable memory behind bridge: %08x-%08x\n", pref_base, pref_limit + 0xfffff);
1868 printf("\tPrefetchable memory behind bridge: %08x%08x-%08x%08x\n",
1869 get_conf_long(d, PCI_PREF_BASE_UPPER32),
1871 get_conf_long(d, PCI_PREF_LIMIT_UPPER32),
1872 pref_limit + 0xfffff);
1877 printf("\tSecondary status: 66MHz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c\n",
1878 FLAG(sec_stat, PCI_STATUS_66MHZ),
1879 FLAG(sec_stat, PCI_STATUS_FAST_BACK),
1880 FLAG(sec_stat, PCI_STATUS_PARITY),
1881 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1882 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1883 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1884 FLAG(sec_stat, PCI_STATUS_SIG_TARGET_ABORT),
1885 FLAG(sec_stat, PCI_STATUS_REC_TARGET_ABORT),
1886 FLAG(sec_stat, PCI_STATUS_REC_MASTER_ABORT),
1887 FLAG(sec_stat, PCI_STATUS_SIG_SYSTEM_ERROR),
1888 FLAG(sec_stat, PCI_STATUS_DETECTED_PARITY));
1890 show_rom(d, PCI_ROM_ADDRESS1);
1894 printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
1895 FLAG(brc, PCI_BRIDGE_CTL_PARITY),
1896 FLAG(brc, PCI_BRIDGE_CTL_SERR),
1897 FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
1898 FLAG(brc, PCI_BRIDGE_CTL_VGA),
1899 FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
1900 FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
1901 FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
1902 printf("\t\tPriDiscTmr%c SecDiscTmr%c DiscTmrStat%c DiscTmrSERREn%c\n",
1903 FLAG(brc, PCI_BRIDGE_CTL_PRI_DISCARD_TIMER),
1904 FLAG(brc, PCI_BRIDGE_CTL_SEC_DISCARD_TIMER),
1905 FLAG(brc, PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS),
1906 FLAG(brc, PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN));
1913 show_htype2(struct device *d)
1916 word cmd = get_conf_word(d, PCI_COMMAND);
1917 word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
1919 int verb = verbose > 2;
1922 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1923 get_conf_byte(d, PCI_CB_PRIMARY_BUS),
1924 get_conf_byte(d, PCI_CB_CARD_BUS),
1925 get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
1926 get_conf_byte(d, PCI_CB_LATENCY_TIMER));
1930 u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
1931 u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
1932 if (limit > base || verb)
1933 printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
1934 (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
1935 (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
1940 u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
1941 u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
1942 if (!(base & PCI_IO_RANGE_TYPE_32))
1947 base &= PCI_CB_IO_RANGE_MASK;
1948 limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
1949 if (base <= limit || verb)
1950 printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
1951 (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
1954 if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
1955 printf("\tSecondary status: SERR\n");
1957 printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
1958 FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
1959 FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
1960 FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
1961 FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
1962 FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
1963 FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
1964 FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
1965 FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
1967 if (d->config_cached < 128)
1969 printf("\t<access denied to the rest>\n");
1973 exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
1975 printf("\t16-bit legacy interface ports at %04x\n", exca);
1979 show_verbose(struct device *d)
1981 struct pci_dev *p = d->dev;
1982 word status = get_conf_word(d, PCI_STATUS);
1983 word cmd = get_conf_word(d, PCI_COMMAND);
1984 word class = p->device_class;
1985 byte bist = get_conf_byte(d, PCI_BIST);
1986 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1987 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
1988 byte cache_line = get_conf_byte(d, PCI_CACHE_LINE_SIZE);
1989 byte max_lat, min_gnt;
1990 byte int_pin = get_conf_byte(d, PCI_INTERRUPT_PIN);
1991 unsigned int irq = p->irq;
1992 word subsys_v, subsys_d;
1993 char ssnamebuf[256];
1999 case PCI_HEADER_TYPE_NORMAL:
2000 if (class == PCI_CLASS_BRIDGE_PCI)
2001 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
2002 max_lat = get_conf_byte(d, PCI_MAX_LAT);
2003 min_gnt = get_conf_byte(d, PCI_MIN_GNT);
2005 case PCI_HEADER_TYPE_BRIDGE:
2006 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
2007 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
2008 irq = int_pin = min_gnt = max_lat = 0;
2010 case PCI_HEADER_TYPE_CARDBUS:
2011 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
2012 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
2013 min_gnt = max_lat = 0;
2016 printf("\t!!! Unknown header type %02x\n", htype);
2020 get_subid(d, &subsys_v, &subsys_d);
2021 if (subsys_v && subsys_v != 0xffff)
2022 printf("\tSubsystem: %s\n",
2023 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
2024 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
2025 p->vendor_id, p->device_id, subsys_v, subsys_d));
2029 printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c DisINTx%c\n",
2030 FLAG(cmd, PCI_COMMAND_IO),
2031 FLAG(cmd, PCI_COMMAND_MEMORY),
2032 FLAG(cmd, PCI_COMMAND_MASTER),
2033 FLAG(cmd, PCI_COMMAND_SPECIAL),
2034 FLAG(cmd, PCI_COMMAND_INVALIDATE),
2035 FLAG(cmd, PCI_COMMAND_VGA_PALETTE),
2036 FLAG(cmd, PCI_COMMAND_PARITY),
2037 FLAG(cmd, PCI_COMMAND_WAIT),
2038 FLAG(cmd, PCI_COMMAND_SERR),
2039 FLAG(cmd, PCI_COMMAND_FAST_BACK),
2040 FLAG(cmd, PCI_COMMAND_DISABLE_INTx));
2041 printf("\tStatus: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c INTx%c\n",
2042 FLAG(status, PCI_STATUS_CAP_LIST),
2043 FLAG(status, PCI_STATUS_66MHZ),
2044 FLAG(status, PCI_STATUS_UDF),
2045 FLAG(status, PCI_STATUS_FAST_BACK),
2046 FLAG(status, PCI_STATUS_PARITY),
2047 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
2048 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
2049 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
2050 FLAG(status, PCI_STATUS_SIG_TARGET_ABORT),
2051 FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
2052 FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
2053 FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
2054 FLAG(status, PCI_STATUS_DETECTED_PARITY),
2055 FLAG(status, PCI_STATUS_INTx));
2056 if (cmd & PCI_COMMAND_MASTER)
2058 printf("\tLatency: %d", latency);
2059 if (min_gnt || max_lat)
2063 printf("%dns min", min_gnt*250);
2064 if (min_gnt && max_lat)
2067 printf("%dns max", max_lat*250);
2071 printf(", Cache Line Size: %d bytes", cache_line * 4);
2075 printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n",
2076 (int_pin ? 'A' + int_pin - 1 : '?'), irq);
2080 printf("\tFlags: ");
2081 if (cmd & PCI_COMMAND_MASTER)
2082 printf("bus master, ");
2083 if (cmd & PCI_COMMAND_VGA_PALETTE)
2084 printf("VGA palette snoop, ");
2085 if (cmd & PCI_COMMAND_WAIT)
2086 printf("stepping, ");
2087 if (cmd & PCI_COMMAND_FAST_BACK)
2088 printf("fast Back2Back, ");
2089 if (status & PCI_STATUS_66MHZ)
2091 if (status & PCI_STATUS_UDF)
2092 printf("user-definable features, ");
2094 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
2095 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
2096 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??");
2097 if (cmd & PCI_COMMAND_MASTER)
2098 printf(", latency %d", latency);
2100 printf(", IRQ " PCIIRQ_FMT, irq);
2104 if (bist & PCI_BIST_CAPABLE)
2106 if (bist & PCI_BIST_START)
2107 printf("\tBIST is running\n");
2109 printf("\tBIST result: %02x\n", bist & PCI_BIST_CODE_MASK);
2114 case PCI_HEADER_TYPE_NORMAL:
2117 case PCI_HEADER_TYPE_BRIDGE:
2120 case PCI_HEADER_TYPE_CARDBUS:
2126 /*** Machine-readable dumps ***/
2129 show_hex_dump(struct device *d)
2131 unsigned int i, cnt;
2133 cnt = d->config_cached;
2134 if (opt_hex >= 3 && config_fetch(d, cnt, 256-cnt))
2137 if (opt_hex >= 4 && config_fetch(d, 256, 4096-256))
2141 for(i=0; i<cnt; i++)
2145 printf(" %02x", get_conf_byte(d, i));
2152 print_shell_escaped(char *c)
2157 if (*c == '"' || *c == '\\')
2165 show_machine(struct device *d)
2167 struct pci_dev *p = d->dev;
2170 char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
2172 get_subid(d, &sv_id, &sd_id);
2176 printf((opt_machine >= 2) ? "Slot:\t" : "Device:\t");
2179 printf("Class:\t%s\n",
2180 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
2181 printf("Vendor:\t%s\n",
2182 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
2183 printf("Device:\t%s\n",
2184 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
2185 if (sv_id && sv_id != 0xffff)
2187 printf("SVendor:\t%s\n",
2188 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
2189 printf("SDevice:\t%s\n",
2190 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
2192 if (c = get_conf_byte(d, PCI_REVISION_ID))
2193 printf("Rev:\t%02x\n", c);
2194 if (c = get_conf_byte(d, PCI_CLASS_PROG))
2195 printf("ProgIf:\t%02x\n", c);
2197 show_kernel_machine(d);
2202 print_shell_escaped(pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
2203 print_shell_escaped(pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
2204 print_shell_escaped(pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
2205 if (c = get_conf_byte(d, PCI_REVISION_ID))
2206 printf(" -r%02x", c);
2207 if (c = get_conf_byte(d, PCI_CLASS_PROG))
2208 printf(" -p%02x", c);
2209 if (sv_id && sv_id != 0xffff)
2211 print_shell_escaped(pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
2212 print_shell_escaped(pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
2215 printf(" \"\" \"\"");
2220 /*** Main show function ***/
2223 show_device(struct device *d)
2233 if (opt_kernel || verbose)
2238 if (verbose || opt_hex)
2247 for(d=first_dev; d; d=d->next)
2251 /*** Tree output ***/
2254 struct bridge *chain; /* Single-linked list of bridges */
2255 struct bridge *next, *child; /* Tree of bridges */
2256 struct bus *first_bus; /* List of buses connected to this bridge */
2257 unsigned int domain;
2258 unsigned int primary, secondary, subordinate; /* Bus numbers */
2259 struct device *br_dev;
2263 unsigned int domain;
2264 unsigned int number;
2265 struct bus *sibling;
2266 struct device *first_dev, **last_dev;
2269 static struct bridge host_bridge = { NULL, NULL, NULL, NULL, 0, ~0, 0, ~0, NULL };
2272 find_bus(struct bridge *b, unsigned int domain, unsigned int n)
2276 for(bus=b->first_bus; bus; bus=bus->sibling)
2277 if (bus->domain == domain && bus->number == n)
2283 new_bus(struct bridge *b, unsigned int domain, unsigned int n)
2285 struct bus *bus = xmalloc(sizeof(struct bus));
2286 bus->domain = domain;
2288 bus->sibling = b->first_bus;
2289 bus->first_dev = NULL;
2290 bus->last_dev = &bus->first_dev;
2296 insert_dev(struct device *d, struct bridge *b)
2298 struct pci_dev *p = d->dev;
2301 if (! (bus = find_bus(b, p->domain, p->bus)))
2304 for(c=b->child; c; c=c->next)
2305 if (c->domain == p->domain && c->secondary <= p->bus && p->bus <= c->subordinate)
2310 bus = new_bus(b, p->domain, p->bus);
2312 /* Simple insertion at the end _does_ guarantee the correct order as the
2313 * original device list was sorted by (domain, bus, devfn) lexicographically
2314 * and all devices on the new list have the same bus number.
2317 bus->last_dev = &d->next;
2324 struct device *d, *d2;
2325 struct bridge **last_br, *b;
2327 /* Build list of bridges */
2329 last_br = &host_bridge.chain;
2330 for(d=first_dev; d; d=d->next)
2332 word class = d->dev->device_class;
2333 byte ht = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
2334 if (class == PCI_CLASS_BRIDGE_PCI &&
2335 (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS))
2337 b = xmalloc(sizeof(struct bridge));
2338 b->domain = d->dev->domain;
2339 if (ht == PCI_HEADER_TYPE_BRIDGE)
2341 b->primary = get_conf_byte(d, PCI_PRIMARY_BUS);
2342 b->secondary = get_conf_byte(d, PCI_SECONDARY_BUS);
2343 b->subordinate = get_conf_byte(d, PCI_SUBORDINATE_BUS);
2347 b->primary = get_conf_byte(d, PCI_CB_PRIMARY_BUS);
2348 b->secondary = get_conf_byte(d, PCI_CB_CARD_BUS);
2349 b->subordinate = get_conf_byte(d, PCI_CB_SUBORDINATE_BUS);
2352 last_br = &b->chain;
2353 b->next = b->child = NULL;
2354 b->first_bus = NULL;
2360 /* Create a bridge tree */
2362 for(b=&host_bridge; b; b=b->chain)
2364 struct bridge *c, *best;
2366 for(c=&host_bridge; c; c=c->chain)
2367 if (c != b && (c == &host_bridge || b->domain == c->domain) &&
2368 b->primary >= c->secondary && b->primary <= c->subordinate &&
2369 (!best || best->subordinate - best->primary > c->subordinate - c->primary))
2373 b->next = best->child;
2378 /* Insert secondary bus for each bridge */
2380 for(b=&host_bridge; b; b=b->chain)
2381 if (!find_bus(b, b->domain, b->secondary))
2382 new_bus(b, b->domain, b->secondary);
2384 /* Create bus structs and link devices */
2386 for(d=first_dev; d;)
2389 insert_dev(d, &host_bridge);
2395 print_it(char *line, char *p)
2399 fputs(line, stdout);
2400 for(p=line; *p; p++)
2401 if (*p == '+' || *p == '|')
2407 static void show_tree_bridge(struct bridge *, char *, char *);
2410 show_tree_dev(struct device *d, char *line, char *p)
2412 struct pci_dev *q = d->dev;
2416 p += sprintf(p, "%02x.%x", q->dev, q->func);
2417 for(b=&host_bridge; b; b=b->chain)
2420 if (b->secondary == b->subordinate)
2421 p += sprintf(p, "-[%04x:%02x]-", b->domain, b->secondary);
2423 p += sprintf(p, "-[%04x:%02x-%02x]-", b->domain, b->secondary, b->subordinate);
2424 show_tree_bridge(b, line, p);
2428 p += sprintf(p, " %s",
2429 pci_lookup_name(pacc, namebuf, sizeof(namebuf),
2430 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
2431 q->vendor_id, q->device_id));
2436 show_tree_bus(struct bus *b, char *line, char *p)
2440 else if (!b->first_dev->next)
2444 show_tree_dev(b->first_dev, line, p);
2448 struct device *d = b->first_dev;
2453 show_tree_dev(d, line, p+2);
2458 show_tree_dev(d, line, p+2);
2463 show_tree_bridge(struct bridge *b, char *line, char *p)
2466 if (!b->first_bus->sibling)
2468 if (b == &host_bridge)
2469 p += sprintf(p, "[%04x:%02x]-", b->domain, b->first_bus->number);
2470 show_tree_bus(b->first_bus, line, p);
2474 struct bus *u = b->first_bus;
2479 k = p + sprintf(p, "+-[%04x:%02x]-", u->domain, u->number);
2480 show_tree_bus(u, line, k);
2483 k = p + sprintf(p, "\\-[%04x:%02x]-", u->domain, u->number);
2484 show_tree_bus(u, line, k);
2494 show_tree_bridge(&host_bridge, line, line);
2497 /*** Bus mapping mode ***/
2500 struct bus_bridge *next;
2501 byte this, dev, func, first, last, bug;
2507 struct bus_bridge *bridges, *via;
2510 static struct bus_info *bus_info;
2513 map_bridge(struct bus_info *bi, struct device *d, int np, int ns, int nl)
2515 struct bus_bridge *b = xmalloc(sizeof(struct bus_bridge));
2516 struct pci_dev *p = d->dev;
2518 b->next = bi->bridges;
2520 b->this = get_conf_byte(d, np);
2523 b->first = get_conf_byte(d, ns);
2524 b->last = get_conf_byte(d, nl);
2525 printf("## %02x.%02x:%d is a bridge from %02x to %02x-%02x\n",
2526 p->bus, p->dev, p->func, b->this, b->first, b->last);
2527 if (b->this != p->bus)
2528 printf("!!! Bridge points to invalid primary bus.\n");
2529 if (b->first > b->last)
2531 printf("!!! Bridge points to invalid bus range.\n");
2540 int verbose = pacc->debugging;
2541 struct bus_info *bi = bus_info + bus;
2545 printf("Mapping bus %02x\n", bus);
2546 for(dev = 0; dev < 32; dev++)
2547 if (filter.slot < 0 || filter.slot == dev)
2550 for(func = 0; func < func_limit; func++)
2551 if (filter.func < 0 || filter.func == func)
2553 /* XXX: Bus mapping supports only domain 0 */
2554 struct pci_dev *p = pci_get_dev(pacc, 0, bus, dev, func);
2555 u16 vendor = pci_read_word(p, PCI_VENDOR_ID);
2556 if (vendor && vendor != 0xffff)
2558 if (!func && (pci_read_byte(p, PCI_HEADER_TYPE) & 0x80))
2561 printf("Discovered device %02x:%02x.%d\n", bus, dev, func);
2563 if (d = scan_device(p))
2566 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
2568 case PCI_HEADER_TYPE_BRIDGE:
2569 map_bridge(bi, d, PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS);
2571 case PCI_HEADER_TYPE_CARDBUS:
2572 map_bridge(bi, d, PCI_CB_PRIMARY_BUS, PCI_CB_CARD_BUS, PCI_CB_SUBORDINATE_BUS);
2578 printf("But it was filtered out.\n");
2586 do_map_bridges(int bus, int min, int max)
2588 struct bus_info *bi = bus_info + bus;
2589 struct bus_bridge *b;
2592 for(b=bi->bridges; b; b=b->next)
2594 if (bus_info[b->first].guestbook)
2596 else if (b->first < min || b->last > max)
2600 bus_info[b->first].via = b;
2601 do_map_bridges(b->first, b->first, b->last);
2611 printf("\nSummary of buses:\n\n");
2612 for(i=0; i<256; i++)
2613 if (bus_info[i].exists && !bus_info[i].guestbook)
2614 do_map_bridges(i, 0, 255);
2615 for(i=0; i<256; i++)
2617 struct bus_info *bi = bus_info + i;
2618 struct bus_bridge *b = bi->via;
2622 printf("%02x: ", i);
2624 printf("Entered via %02x:%02x.%d\n", b->this, b->dev, b->func);
2626 printf("Primary host bus\n");
2628 printf("Secondary host bus (?)\n");
2630 for(b=bi->bridges; b; b=b->next)
2632 printf("\t%02x.%d Bridge to %02x-%02x", b->dev, b->func, b->first, b->last);
2636 printf(" <overlap bug>");
2639 printf(" <crossing bug>");
2650 if (pacc->method == PCI_ACCESS_PROC_BUS_PCI ||
2651 pacc->method == PCI_ACCESS_DUMP)
2652 printf("WARNING: Bus mapping can be reliable only with direct hardware access enabled.\n\n");
2653 bus_info = xmalloc(sizeof(struct bus_info) * 256);
2654 memset(bus_info, 0, sizeof(struct bus_info) * 256);
2655 if (filter.bus >= 0)
2656 do_map_bus(filter.bus);
2660 for(bus=0; bus<256; bus++)
2669 main(int argc, char **argv)
2674 if (argc == 2 && !strcmp(argv[1], "--version"))
2676 puts("lspci version " PCIUTILS_VERSION);
2682 pci_filter_init(pacc, &filter);
2684 while ((i = getopt(argc, argv, options)) != -1)
2688 pacc->numeric_ids++;
2694 pacc->buscentric = 1;
2698 if (msg = pci_filter_parse_slot(&filter, optarg))
2702 if (msg = pci_filter_parse_id(&filter, optarg))
2712 pci_set_name_list_path(pacc, optarg, 0);
2718 opt_pcimap = optarg;
2730 if (parse_generic_option(i, pacc, optarg))
2733 fprintf(stderr, help_msg, pacc->id_file_name);
2753 return (seen_errors ? 2 : 0);