2 * The PCI Utilities -- List All PCI Devices
4 * Copyright (c) 1997--2005 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
19 static int verbose; /* Show detailed information */
20 static int buscentric_view; /* Show bus addresses/IRQ's instead of CPU-visible ones */
21 static int show_hex; /* Show contents of config space as hexadecimal numbers */
22 static struct pci_filter filter; /* Device filter */
23 static int show_tree; /* Show bus tree */
24 static int machine_readable; /* Generate machine-readable output */
25 static int map_mode; /* Bus mapping mode enabled */
27 static char options[] = "nvbxs:d:ti:mgM" GENERIC_OPTIONS ;
29 static char help_msg[] = "\
30 Usage: lspci [<switches>]\n\
33 -n\t\tShow numeric ID's\n\
34 -b\t\tBus-centric view (PCI addresses and IRQ's instead of those seen by the CPU)\n\
35 -x\t\tShow hex-dump of the standard portion of config space\n\
36 -xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n\
37 -xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n\
38 -s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n\
39 -d [<vendor>]:[<device>]\tShow only selected devices\n\
40 -t\t\tShow bus tree\n\
41 -m\t\tProduce machine-readable output\n\
42 -i <file>\tUse specified ID database instead of %s\n\
43 -M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
47 /* Communication with libpci */
49 static struct pci_access *pacc;
52 * If we aren't being compiled by GCC, use xmalloc() instead of alloca().
53 * This increases our memory footprint, but only slightly since we don't
59 #define alloca xmalloc
62 /* Our view of the PCI bus */
67 unsigned int config_cnt, config_bufsize;
71 static struct device *first_dev;
74 config_fetch(struct device *d, unsigned int pos, unsigned int len)
76 unsigned int end = pos+len;
78 if (end <= d->config_cnt)
80 if (end > d->config_bufsize)
82 while (end > d->config_bufsize)
83 d->config_bufsize *= 2;
84 d->config = xrealloc(d->config, d->config_bufsize);
86 result = pci_read_block(d->dev, pos, d->config + pos, len);
87 if (result && pos == d->config_cnt)
92 static struct device *
93 scan_device(struct pci_dev *p)
97 if (!pci_filter_match(&filter, p))
99 d = xmalloc(sizeof(struct device));
100 bzero(d, sizeof(*d));
102 d->config_cnt = d->config_bufsize = 64;
103 d->config = xmalloc(64);
104 if (!pci_read_block(p, 0, d->config, 64))
105 die("Unable to read the configuration space header.");
106 if ((d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
108 /* For cardbus bridges, we need to fetch 64 bytes more to get the
109 * full standard header... */
110 if (!config_fetch(d, 64, 64))
111 die("Unable to read cardbus bridge extension data.");
113 pci_setup_cache(p, d->config, d->config_cnt);
114 pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
125 for(p=pacc->devices; p; p=p->next)
126 if (d = scan_device(p))
133 /* Config space accesses */
136 get_conf_byte(struct device *d, unsigned int pos)
138 return d->config[pos];
142 get_conf_word(struct device *d, unsigned int pos)
144 return d->config[pos] | (d->config[pos+1] << 8);
148 get_conf_long(struct device *d, unsigned int pos)
150 return d->config[pos] |
151 (d->config[pos+1] << 8) |
152 (d->config[pos+2] << 16) |
153 (d->config[pos+3] << 24);
159 compare_them(const void *A, const void *B)
161 const struct pci_dev *a = (*(const struct device **)A)->dev;
162 const struct pci_dev *b = (*(const struct device **)B)->dev;
164 if (a->domain < b->domain)
166 if (a->domain > b->domain)
176 if (a->func < b->func)
178 if (a->func > b->func)
186 struct device **index, **h, **last_dev;
191 for(d=first_dev; d; d=d->next)
193 h = index = alloca(sizeof(struct device *) * cnt);
194 for(d=first_dev; d; d=d->next)
196 qsort(index, cnt, sizeof(struct device *), compare_them);
197 last_dev = &first_dev;
202 last_dev = &(*h)->next;
210 #define FLAG(x,y) ((x & y) ? '+' : '-')
213 show_slot_name(struct device *d)
215 struct pci_dev *p = d->dev;
218 printf("%04x:", p->domain);
219 printf("%02x:%02x.%d", p->bus, p->dev, p->func);
223 show_terse(struct device *d)
226 struct pci_dev *p = d->dev;
227 byte classbuf[128], devbuf[128];
231 pci_lookup_name(pacc, classbuf, sizeof(classbuf),
233 get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0),
234 pci_lookup_name(pacc, devbuf, sizeof(devbuf),
235 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
236 p->vendor_id, p->device_id, 0, 0));
237 if (c = get_conf_byte(d, PCI_REVISION_ID))
238 printf(" (rev %02x)", c);
242 c = get_conf_byte(d, PCI_CLASS_PROG);
243 x = pci_lookup_name(pacc, devbuf, sizeof(devbuf),
245 get_conf_word(d, PCI_CLASS_DEVICE), c, 0, 0);
248 printf(" (prog-if %02x", c);
258 show_size(pciaddr_t x)
264 printf("%d", (int) x);
265 else if (x < 1048576)
266 printf("%dK", (int)(x / 1024));
267 else if (x < 0x80000000)
268 printf("%dM", (int)(x / 1048576));
270 printf(PCIADDR_T_FMT, x);
275 show_bases(struct device *d, int cnt)
277 struct pci_dev *p = d->dev;
278 word cmd = get_conf_word(d, PCI_COMMAND);
283 pciaddr_t pos = p->base_addr[i];
284 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
285 u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
286 if (flg == 0xffffffff)
288 if (!pos && !flg && !len)
291 printf("\tRegion %d: ", i);
294 if (pos && !flg) /* Reported by the OS, but not by the device */
296 printf("[virtual] ");
299 if (flg & PCI_BASE_ADDRESS_SPACE_IO)
301 pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
302 printf("I/O ports at ");
304 printf(PCIADDR_PORT_FMT, a);
305 else if (flg & PCI_BASE_ADDRESS_IO_MASK)
308 printf("<unassigned>");
309 if (!(cmd & PCI_COMMAND_IO))
310 printf(" [disabled]");
314 int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
315 pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
319 printf("Memory at ");
320 if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
324 printf("<invalid-64bit-slot>");
330 z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
334 printf("%08x" PCIADDR_T_FMT, z, a);
336 printf("<unassigned>");
344 printf(PCIADDR_T_FMT, a);
346 printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
348 printf(" (%s, %sprefetchable)",
349 (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
350 (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
351 (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
352 (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
353 if (!(cmd & PCI_COMMAND_MEMORY))
354 printf(" [disabled]");
362 show_pm(struct device *d, int where, int cap)
365 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
367 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
370 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
371 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
372 FLAG(cap, PCI_PM_CAP_DSI),
373 FLAG(cap, PCI_PM_CAP_D1),
374 FLAG(cap, PCI_PM_CAP_D2),
375 pm_aux_current[(cap >> 6) & 7],
376 FLAG(cap, PCI_PM_CAP_PME_D0),
377 FLAG(cap, PCI_PM_CAP_PME_D1),
378 FLAG(cap, PCI_PM_CAP_PME_D2),
379 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
380 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
381 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
383 t = get_conf_word(d, where + PCI_PM_CTRL);
384 printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
385 t & PCI_PM_CTRL_STATE_MASK,
386 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
387 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
388 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
389 FLAG(t, PCI_PM_CTRL_PME_STATUS));
390 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
392 printf("\t\tBridge: PM%c B3%c\n",
393 FLAG(t, PCI_PM_BPCC_ENABLE),
394 FLAG(~t, PCI_PM_PPB_B2_B3));
398 format_agp_rate(int rate, char *buf, int agp3)
408 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
413 strcpy(buf, "<none>");
417 show_agp(struct device *d, int where, int cap)
424 ver = (cap >> 4) & 0x0f;
426 printf("AGP version %x.%x\n", ver, rev);
429 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
431 t = get_conf_long(d, where + PCI_AGP_STATUS);
432 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
434 format_agp_rate(t & 7, rate, agp3);
435 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
436 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
437 FLAG(t, PCI_AGP_STATUS_ISOCH),
438 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
439 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
440 FLAG(t, PCI_AGP_STATUS_SBA),
441 FLAG(t, PCI_AGP_STATUS_ITA_COH),
442 FLAG(t, PCI_AGP_STATUS_GART64),
443 FLAG(t, PCI_AGP_STATUS_HTRANS),
444 FLAG(t, PCI_AGP_STATUS_64BIT),
445 FLAG(t, PCI_AGP_STATUS_FW),
446 FLAG(t, PCI_AGP_STATUS_AGP3),
448 t = get_conf_long(d, where + PCI_AGP_COMMAND);
449 format_agp_rate(t & 7, rate, agp3);
450 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
451 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
452 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
453 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
454 FLAG(t, PCI_AGP_COMMAND_SBA),
455 FLAG(t, PCI_AGP_COMMAND_AGP),
456 FLAG(t, PCI_AGP_COMMAND_GART64),
457 FLAG(t, PCI_AGP_COMMAND_64BIT),
458 FLAG(t, PCI_AGP_COMMAND_FW),
463 show_pcix_nobridge(struct device *d, int where)
468 printf("PCI-X non-bridge device.\n");
473 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
476 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
477 status = get_conf_long(d, where + PCI_PCIX_STATUS);
478 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
479 FLAG(command, PCI_PCIX_COMMAND_DPERE),
480 FLAG(command, PCI_PCIX_COMMAND_ERO),
481 ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U),
482 ((command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U));
483 printf("\t\tStatus: Bus=%u Dev=%u Func=%u 64bit%c 133MHz%c SCD%c USC%c, DC=%s, DMMRBC=%u, DMOST=%u, DMCRS=%u, RSCEM%c\n",
484 ((status >> 8) & 0xffU), // bus
485 ((status >> 3) & 0x1fU), // dev
486 (status & PCI_PCIX_STATUS_FUNCTION), // function
487 FLAG(status, PCI_PCIX_STATUS_64BIT),
488 FLAG(status, PCI_PCIX_STATUS_133MHZ),
489 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
490 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
491 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
492 ((status >> 21) & 3U),
493 ((status >> 23) & 7U),
494 ((status >> 26) & 7U),
495 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS));
499 show_pcix_bridge(struct device *d, int where)
503 u32 status, upstcr, downstcr;
505 printf("PCI-X bridge device.\n");
510 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
513 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
514 printf("\t\tSecondary Status: 64bit%c, 133MHz%c, SCD%c, USC%c, SCO%c, SRD%c Freq=%d\n",
515 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
516 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
517 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
518 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
519 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
520 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
521 ((secstatus >> 6) & 7));
522 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
523 printf("\t\tStatus: Bus=%u Dev=%u Func=%u 64bit%c 133MHz%c SCD%c USC%c, SCO%c, SRD%c\n",
524 ((status >> 8) & 0xff), // bus
525 ((status >> 3) & 0x1f), // dev
526 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION), // function
527 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
528 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
529 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
530 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
531 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
532 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
533 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
534 printf("\t\t: Upstream: Capacity=%u, Commitment Limit=%u\n",
535 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
536 (upstcr >> 16) & 0xffff);
537 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
538 printf("\t\t: Downstream: Capacity=%u, Commitment Limit=%u\n",
539 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
540 (downstcr >> 16) & 0xffff);
544 show_pcix(struct device *d, int where)
546 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
548 case PCI_HEADER_TYPE_NORMAL:
549 show_pcix_nobridge(d, where);
551 case PCI_HEADER_TYPE_BRIDGE:
552 show_pcix_bridge(d, where);
558 ht_link_width(unsigned width)
560 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
561 return widths[width];
565 ht_link_freq(unsigned freq)
567 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
568 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
573 show_ht_pri(struct device *d, int where, int cmd)
575 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
576 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
579 printf("HyperTransport: Slave or Primary Interface\n");
583 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
585 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
586 if (rid < 0x23 && rid > 0x11)
587 printf("\t!!! Possibly incomplete decoding\n");
590 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
592 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
594 (cmd & PCI_HT_PRI_CMD_BUID),
595 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
596 FLAG(cmd, PCI_HT_PRI_CMD_MH),
597 FLAG(cmd, PCI_HT_PRI_CMD_DD),
598 FLAG(cmd, PCI_HT_PRI_CMD_DUL));
599 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
601 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
603 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
605 FLAG(lctr0, PCI_HT_LCTR_CFLE),
606 FLAG(lctr0, PCI_HT_LCTR_CST),
607 FLAG(lctr0, PCI_HT_LCTR_CFE),
608 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
609 FLAG(lctr0, PCI_HT_LCTR_INIT),
610 FLAG(lctr0, PCI_HT_LCTR_EOC),
611 FLAG(lctr0, PCI_HT_LCTR_TXO),
612 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
613 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
614 FLAG(lctr0, PCI_HT_LCTR_LSEN),
615 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
616 FLAG(lctr0, PCI_HT_LCTR_64B));
617 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
619 fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
621 fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
623 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
624 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
625 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
626 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
627 FLAG(lcnf0, PCI_HT_LCNF_DFI),
628 FLAG(lcnf0, PCI_HT_LCNF_DFO),
629 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
630 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
631 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
633 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
635 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
637 FLAG(lctr1, PCI_HT_LCTR_CFLE),
638 FLAG(lctr1, PCI_HT_LCTR_CST),
639 FLAG(lctr1, PCI_HT_LCTR_CFE),
640 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
641 FLAG(lctr1, PCI_HT_LCTR_INIT),
642 FLAG(lctr1, PCI_HT_LCTR_EOC),
643 FLAG(lctr1, PCI_HT_LCTR_TXO),
644 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
645 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
646 FLAG(lctr1, PCI_HT_LCTR_LSEN),
647 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
648 FLAG(lctr1, PCI_HT_LCTR_64B));
649 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
651 fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
653 fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
655 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
656 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
657 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
658 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
659 FLAG(lcnf1, PCI_HT_LCNF_DFI),
660 FLAG(lcnf1, PCI_HT_LCNF_DFO),
661 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
662 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
663 printf("\t\tRevision ID: %u.%02u\n",
664 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
667 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
668 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
669 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
670 FLAG(lfrer0, PCI_HT_LFRER_PROT),
671 FLAG(lfrer0, PCI_HT_LFRER_OV),
672 FLAG(lfrer0, PCI_HT_LFRER_EOC),
673 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
674 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
675 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
676 FLAG(lfcap0, PCI_HT_LFCAP_200),
677 FLAG(lfcap0, PCI_HT_LFCAP_300),
678 FLAG(lfcap0, PCI_HT_LFCAP_400),
679 FLAG(lfcap0, PCI_HT_LFCAP_500),
680 FLAG(lfcap0, PCI_HT_LFCAP_600),
681 FLAG(lfcap0, PCI_HT_LFCAP_800),
682 FLAG(lfcap0, PCI_HT_LFCAP_1000),
683 FLAG(lfcap0, PCI_HT_LFCAP_1200),
684 FLAG(lfcap0, PCI_HT_LFCAP_1400),
685 FLAG(lfcap0, PCI_HT_LFCAP_1600),
686 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
687 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
688 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
689 FLAG(ftr, PCI_HT_FTR_ISOCFC),
690 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
691 FLAG(ftr, PCI_HT_FTR_CRCTM),
692 FLAG(ftr, PCI_HT_FTR_ECTLT),
693 FLAG(ftr, PCI_HT_FTR_64BA),
694 FLAG(ftr, PCI_HT_FTR_UIDRD));
695 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
696 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
697 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
698 FLAG(lfrer1, PCI_HT_LFRER_PROT),
699 FLAG(lfrer1, PCI_HT_LFRER_OV),
700 FLAG(lfrer1, PCI_HT_LFRER_EOC),
701 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
702 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
703 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
704 FLAG(lfcap1, PCI_HT_LFCAP_200),
705 FLAG(lfcap1, PCI_HT_LFCAP_300),
706 FLAG(lfcap1, PCI_HT_LFCAP_400),
707 FLAG(lfcap1, PCI_HT_LFCAP_500),
708 FLAG(lfcap1, PCI_HT_LFCAP_600),
709 FLAG(lfcap1, PCI_HT_LFCAP_800),
710 FLAG(lfcap1, PCI_HT_LFCAP_1000),
711 FLAG(lfcap1, PCI_HT_LFCAP_1200),
712 FLAG(lfcap1, PCI_HT_LFCAP_1400),
713 FLAG(lfcap1, PCI_HT_LFCAP_1600),
714 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
715 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
716 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
717 FLAG(eh, PCI_HT_EH_PFLE),
718 FLAG(eh, PCI_HT_EH_OFLE),
719 FLAG(eh, PCI_HT_EH_PFE),
720 FLAG(eh, PCI_HT_EH_OFE),
721 FLAG(eh, PCI_HT_EH_EOCFE),
722 FLAG(eh, PCI_HT_EH_RFE),
723 FLAG(eh, PCI_HT_EH_CRCFE),
724 FLAG(eh, PCI_HT_EH_SERRFE),
725 FLAG(eh, PCI_HT_EH_CF),
726 FLAG(eh, PCI_HT_EH_RE),
727 FLAG(eh, PCI_HT_EH_PNFE),
728 FLAG(eh, PCI_HT_EH_ONFE),
729 FLAG(eh, PCI_HT_EH_EOCNFE),
730 FLAG(eh, PCI_HT_EH_RNFE),
731 FLAG(eh, PCI_HT_EH_CRCNFE),
732 FLAG(eh, PCI_HT_EH_SERRNFE));
733 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
734 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
735 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
736 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
737 printf("\t\tBus Number: %02x\n", bn);
741 show_ht_sec(struct device *d, int where, int cmd)
743 u16 lctr, lcnf, ftr, eh;
744 u8 rid, lfrer, lfcap, mbu, mlu;
747 printf("HyperTransport: Host or Secondary Interface\n");
751 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
753 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
754 if (rid < 0x23 && rid > 0x11)
755 printf("\t!!! Possibly incomplete decoding\n");
758 fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
760 fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
762 FLAG(cmd, PCI_HT_SEC_CMD_WR),
763 FLAG(cmd, PCI_HT_SEC_CMD_DE),
764 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
765 FLAG(cmd, PCI_HT_SEC_CMD_CS),
766 FLAG(cmd, PCI_HT_SEC_CMD_HH),
767 FLAG(cmd, PCI_HT_SEC_CMD_AS),
768 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
769 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
770 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
772 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
774 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
776 FLAG(lctr, PCI_HT_LCTR_CFLE),
777 FLAG(lctr, PCI_HT_LCTR_CST),
778 FLAG(lctr, PCI_HT_LCTR_CFE),
779 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
780 FLAG(lctr, PCI_HT_LCTR_INIT),
781 FLAG(lctr, PCI_HT_LCTR_EOC),
782 FLAG(lctr, PCI_HT_LCTR_TXO),
783 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
784 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
785 FLAG(lctr, PCI_HT_LCTR_LSEN),
786 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
787 FLAG(lctr, PCI_HT_LCTR_64B));
788 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
790 fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
792 fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
794 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
795 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
796 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
797 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
798 FLAG(lcnf, PCI_HT_LCNF_DFI),
799 FLAG(lcnf, PCI_HT_LCNF_DFO),
800 FLAG(lcnf, PCI_HT_LCNF_DFIE),
801 FLAG(lcnf, PCI_HT_LCNF_DFOE));
802 printf("\t\tRevision ID: %u.%02u\n",
803 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
806 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
807 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
808 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
809 FLAG(lfrer, PCI_HT_LFRER_PROT),
810 FLAG(lfrer, PCI_HT_LFRER_OV),
811 FLAG(lfrer, PCI_HT_LFRER_EOC),
812 FLAG(lfrer, PCI_HT_LFRER_CTLT));
813 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
814 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
815 FLAG(lfcap, PCI_HT_LFCAP_200),
816 FLAG(lfcap, PCI_HT_LFCAP_300),
817 FLAG(lfcap, PCI_HT_LFCAP_400),
818 FLAG(lfcap, PCI_HT_LFCAP_500),
819 FLAG(lfcap, PCI_HT_LFCAP_600),
820 FLAG(lfcap, PCI_HT_LFCAP_800),
821 FLAG(lfcap, PCI_HT_LFCAP_1000),
822 FLAG(lfcap, PCI_HT_LFCAP_1200),
823 FLAG(lfcap, PCI_HT_LFCAP_1400),
824 FLAG(lfcap, PCI_HT_LFCAP_1600),
825 FLAG(lfcap, PCI_HT_LFCAP_VEND));
826 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
827 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
828 FLAG(ftr, PCI_HT_FTR_ISOCFC),
829 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
830 FLAG(ftr, PCI_HT_FTR_CRCTM),
831 FLAG(ftr, PCI_HT_FTR_ECTLT),
832 FLAG(ftr, PCI_HT_FTR_64BA),
833 FLAG(ftr, PCI_HT_FTR_UIDRD),
834 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
835 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
836 if (ftr & PCI_HT_SEC_FTR_EXTRS)
838 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
839 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
840 FLAG(eh, PCI_HT_EH_PFLE),
841 FLAG(eh, PCI_HT_EH_OFLE),
842 FLAG(eh, PCI_HT_EH_PFE),
843 FLAG(eh, PCI_HT_EH_OFE),
844 FLAG(eh, PCI_HT_EH_EOCFE),
845 FLAG(eh, PCI_HT_EH_RFE),
846 FLAG(eh, PCI_HT_EH_CRCFE),
847 FLAG(eh, PCI_HT_EH_SERRFE),
848 FLAG(eh, PCI_HT_EH_CF),
849 FLAG(eh, PCI_HT_EH_RE),
850 FLAG(eh, PCI_HT_EH_PNFE),
851 FLAG(eh, PCI_HT_EH_ONFE),
852 FLAG(eh, PCI_HT_EH_EOCNFE),
853 FLAG(eh, PCI_HT_EH_RNFE),
854 FLAG(eh, PCI_HT_EH_CRCNFE),
855 FLAG(eh, PCI_HT_EH_SERRNFE));
856 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
857 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
858 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
863 show_ht(struct device *d, int where, int cmd)
867 switch (cmd & PCI_HT_CMD_TYP_HI)
869 case PCI_HT_CMD_TYP_HI_PRI:
870 show_ht_pri(d, where, cmd);
872 case PCI_HT_CMD_TYP_HI_SEC:
873 show_ht_sec(d, where, cmd);
877 type = cmd & PCI_HT_CMD_TYP;
880 case PCI_HT_CMD_TYP_SW:
881 printf("HyperTransport: Switch\n");
883 case PCI_HT_CMD_TYP_IDC:
884 printf("HyperTransport: Interrupt Discovery and Configuration\n");
886 case PCI_HT_CMD_TYP_RID:
887 printf("HyperTransport: Revision ID: %u.%02u\n",
888 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
890 case PCI_HT_CMD_TYP_UIDC:
891 printf("HyperTransport: UnitID Clumping\n");
893 case PCI_HT_CMD_TYP_ECSA:
894 printf("HyperTransport: Extended Configuration Space Access\n");
896 case PCI_HT_CMD_TYP_AM:
897 printf("HyperTransport: Address Mapping\n");
899 case PCI_HT_CMD_TYP_MSIM:
900 printf("HyperTransport: MSI Mapping\n");
902 case PCI_HT_CMD_TYP_DR:
903 printf("HyperTransport: DirectRoute\n");
905 case PCI_HT_CMD_TYP_VCS:
906 printf("HyperTransport: VCSet\n");
908 case PCI_HT_CMD_TYP_RM:
909 printf("HyperTransport: Retry Mode\n");
911 case PCI_HT_CMD_TYP_X86:
912 printf("HyperTransport: X86 (reserved)\n");
915 printf("HyperTransport: #%02x\n", type >> 11);
920 show_rom(struct device *d, int reg)
922 struct pci_dev *p = d->dev;
923 pciaddr_t rom = p->rom_base_addr;
924 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
925 u32 flg = get_conf_long(d, reg);
926 word cmd = get_conf_word(d, PCI_COMMAND);
928 if (!rom && !flg && !len)
931 if ((rom & PCI_ROM_ADDRESS_MASK) && !(flg & PCI_ROM_ADDRESS_MASK))
933 printf("[virtual] ");
936 printf("Expansion ROM at ");
937 if (rom & PCI_ROM_ADDRESS_MASK)
938 printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
939 else if (flg & PCI_ROM_ADDRESS_MASK)
942 printf("<unassigned>");
943 if (!(flg & PCI_ROM_ADDRESS_ENABLE))
944 printf(" [disabled]");
945 else if (!(cmd & PCI_COMMAND_MEMORY))
946 printf(" [disabled by cmd]");
952 show_msi(struct device *d, int where, int cap)
958 printf("Message Signalled Interrupts: 64bit%c Queue=%d/%d Enable%c\n",
959 FLAG(cap, PCI_MSI_FLAGS_64BIT),
960 (cap & PCI_MSI_FLAGS_QSIZE) >> 4,
961 (cap & PCI_MSI_FLAGS_QMASK) >> 1,
962 FLAG(cap, PCI_MSI_FLAGS_ENABLE));
965 is64 = cap & PCI_MSI_FLAGS_64BIT;
966 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
968 printf("\t\tAddress: ");
971 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
972 w = get_conf_word(d, where + PCI_MSI_DATA_64);
976 w = get_conf_word(d, where + PCI_MSI_DATA_32);
977 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
978 printf("%08x Data: %04x\n", t, w);
981 static void show_vendor(void)
983 printf("Vendor Specific Information\n");
986 static void show_debug(void)
988 printf("Debug port\n");
991 static float power_limit(int value, int scale)
993 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
994 return value * scales[scale];
997 static const char *latency_l0s(int value)
999 static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
1000 return latencies[value];
1003 static const char *latency_l1(int value)
1005 static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
1006 return latencies[value];
1009 static void show_express_dev(struct device *d, int where, int type)
1014 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
1015 printf("\t\tDevice: Supported: MaxPayload %d bytes, PhantFunc %d, ExtTag%c\n",
1016 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
1017 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
1018 FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
1019 printf("\t\tDevice: Latency L0s %s, L1 %s\n",
1020 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
1021 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
1022 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
1023 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
1024 printf("\t\tDevice: AtnBtn%c AtnInd%c PwrInd%c\n",
1025 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
1026 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
1027 if (type == PCI_EXP_TYPE_UPSTREAM)
1028 printf("\t\tDevice: SlotPowerLimit %f\n",
1029 power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
1030 (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
1032 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
1033 printf("\t\tDevice: Errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
1034 FLAG(w, PCI_EXP_DEVCTL_CERE),
1035 FLAG(w, PCI_EXP_DEVCTL_NFERE),
1036 FLAG(w, PCI_EXP_DEVCTL_FERE),
1037 FLAG(w, PCI_EXP_DEVCTL_URRE));
1038 printf("\t\tDevice: RlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c\n",
1039 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
1040 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
1041 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
1042 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
1043 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
1044 printf("\t\tDevice: MaxPayload %d bytes, MaxReadReq %d bytes\n",
1045 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
1046 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
1049 static char *link_speed(int speed)
1060 static char *aspm_support(int code)
1073 static const char *aspm_enabled(int code)
1075 static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
1079 static void show_express_link(struct device *d, int where, int type)
1084 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
1085 printf("\t\tLink: Supported Speed %s, Width x%d, ASPM %s, Port %d\n",
1086 link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
1087 aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
1089 printf("\t\tLink: Latency L0s %s, L1 %s\n",
1090 latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
1091 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
1092 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
1093 printf("\t\tLink: ASPM %s", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
1094 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
1095 (type == PCI_EXP_TYPE_LEG_END))
1096 printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
1097 if (w & PCI_EXP_LNKCTL_DISABLE)
1098 printf(" Disabled");
1099 printf(" CommClk%c ExtSynch%c\n", FLAG(w, PCI_EXP_LNKCTL_CLOCK),
1100 FLAG(w, PCI_EXP_LNKCTL_XSYNCH));
1101 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
1102 printf("\t\tLink: Speed %s, Width x%d\n",
1103 link_speed(t & PCI_EXP_LNKSTA_SPEED), (t & PCI_EXP_LNKSTA_WIDTH) >> 4);
1106 static const char *indicator(int code)
1108 static const char *names[] = { "Unknown", "On", "Blink", "Off" };
1112 static void show_express_slot(struct device *d, int where)
1117 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
1118 printf("\t\tSlot: AtnBtn%c PwrCtrl%c MRL%c AtnInd%c PwrInd%c HotPlug%c Surpise%c\n",
1119 FLAG(t, PCI_EXP_SLTCAP_ATNB),
1120 FLAG(t, PCI_EXP_SLTCAP_PWRC),
1121 FLAG(t, PCI_EXP_SLTCAP_MRL),
1122 FLAG(t, PCI_EXP_SLTCAP_ATNI),
1123 FLAG(t, PCI_EXP_SLTCAP_PWRI),
1124 FLAG(t, PCI_EXP_SLTCAP_HPC),
1125 FLAG(t, PCI_EXP_SLTCAP_HPS));
1126 printf("\t\tSlot: Number %d, PowerLimit %f\n", t >> 19,
1127 power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7,
1128 (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15));
1129 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
1130 printf("\t\tSlot: Enabled AtnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c\n",
1131 FLAG(w, PCI_EXP_SLTCTL_ATNB),
1132 FLAG(w, PCI_EXP_SLTCTL_PWRF),
1133 FLAG(w, PCI_EXP_SLTCTL_MRLS),
1134 FLAG(w, PCI_EXP_SLTCTL_PRSD),
1135 FLAG(w, PCI_EXP_SLTCTL_CMDC),
1136 FLAG(w, PCI_EXP_SLTCTL_HPIE));
1137 printf("\t\tSlot: AttnInd %s, PwrInd %s, Power%c\n",
1138 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
1139 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
1140 FLAG(w, w & PCI_EXP_SLTCTL_PWRC));
1143 static void show_express_root(struct device *d, int where)
1145 u16 w = get_conf_word(d, where + PCI_EXP_RTCTL);
1146 printf("\t\tRoot: Correctable%c Non-Fatal%c Fatal%c PME%c\n",
1147 FLAG(w, PCI_EXP_RTCTL_SECEE),
1148 FLAG(w, PCI_EXP_RTCTL_SENFEE),
1149 FLAG(w, PCI_EXP_RTCTL_SEFEE),
1150 FLAG(w, PCI_EXP_RTCTL_PMEIE));
1154 show_express(struct device *d, int where, int cap)
1156 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1163 case PCI_EXP_TYPE_ENDPOINT:
1166 case PCI_EXP_TYPE_LEG_END:
1167 printf("Legacy Endpoint");
1169 case PCI_EXP_TYPE_ROOT_PORT:
1170 slot = cap & PCI_EXP_FLAGS_SLOT;
1171 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1173 case PCI_EXP_TYPE_UPSTREAM:
1174 printf("Upstream Port");
1176 case PCI_EXP_TYPE_DOWNSTREAM:
1177 slot = cap & PCI_EXP_FLAGS_SLOT;
1178 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1180 case PCI_EXP_TYPE_PCI_BRIDGE:
1181 printf("PCI/PCI-X Bridge");
1184 printf("Unknown type");
1186 printf(" IRQ %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1193 if (type == PCI_EXP_TYPE_ROOT_PORT)
1195 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1198 show_express_dev(d, where, type);
1199 show_express_link(d, where, type);
1201 show_express_slot(d, where);
1202 if (type == PCI_EXP_TYPE_ROOT_PORT)
1203 show_express_root(d, where);
1207 show_msix(struct device *d, int where, int cap)
1211 printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
1212 FLAG(cap, PCI_MSIX_ENABLE),
1213 FLAG(cap, PCI_MSIX_MASK),
1214 (cap & PCI_MSIX_TABSIZE) + 1);
1215 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1218 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1219 printf("\t\tVector table: BAR=%d offset=%08x\n",
1220 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1221 off = get_conf_long(d, where + PCI_MSIX_PBA);
1222 printf("\t\tPBA: BAR=%d offset=%08x\n",
1223 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1227 show_slotid(int cap)
1229 int esr = cap & 0xff;
1232 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1233 esr & PCI_SID_ESR_NSLOTS,
1234 FLAG(esr, PCI_SID_ESR_FIC),
1239 show_aer(struct device *d, int where)
1241 printf("Advanced Error Reporting\n");
1245 show_vc(struct device *d, int where)
1247 printf("Virtual Channel\n");
1251 show_dsn(struct device *d, int where)
1254 if (!config_fetch(d, where + 4, 8))
1256 t1 = get_conf_long(d, where + 4);
1257 t2 = get_conf_long(d, where + 8);
1258 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
1259 t1 & 0xff, (t1 >> 8) & 0xff, (t1 >> 16) & 0xff, t1 >> 24,
1260 t2 & 0xff, (t2 >> 8) & 0xff, (t2 >> 16) & 0xff, t2 >> 24);
1264 show_pb(struct device *d, int where)
1266 printf("Power Budgeting\n");
1270 show_ext_caps(struct device *d)
1278 if (!config_fetch(d, where, 4))
1280 header = get_conf_long(d, where);
1283 id = header & 0xffff;
1284 printf("\tCapabilities: [%03x] ", where);
1287 case PCI_EXT_CAP_ID_AER:
1290 case PCI_EXT_CAP_ID_VC:
1293 case PCI_EXT_CAP_ID_DSN:
1296 case PCI_EXT_CAP_ID_PB:
1300 printf("Unknown (%d)\n", id);
1303 where = header >> 20;
1308 show_caps(struct device *d)
1310 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1312 int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
1316 printf("\tCapabilities: ");
1317 if (!config_fetch(d, where, 4))
1319 puts("<available only to root>");
1322 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1323 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1324 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1325 printf("[%02x] ", where);
1328 printf("<chain broken>\n");
1334 show_pm(d, where, cap);
1336 case PCI_CAP_ID_AGP:
1337 show_agp(d, where, cap);
1339 case PCI_CAP_ID_VPD:
1340 printf("Vital Product Data\n");
1342 case PCI_CAP_ID_SLOTID:
1345 case PCI_CAP_ID_MSI:
1346 show_msi(d, where, cap);
1348 case PCI_CAP_ID_PCIX:
1349 show_pcix(d, where);
1352 show_ht(d, where, cap);
1354 case PCI_CAP_ID_VNDR:
1357 case PCI_CAP_ID_DBG:
1360 case PCI_CAP_ID_EXP:
1361 show_express(d, where, cap);
1363 case PCI_CAP_ID_MSIX:
1364 show_msix(d, where, cap);
1367 printf("#%02x [%04x]\n", id, cap);
1376 show_htype0(struct device *d)
1379 show_rom(d, PCI_ROM_ADDRESS);
1384 show_htype1(struct device *d)
1386 u32 io_base = get_conf_byte(d, PCI_IO_BASE);
1387 u32 io_limit = get_conf_byte(d, PCI_IO_LIMIT);
1388 u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
1389 u32 mem_base = get_conf_word(d, PCI_MEMORY_BASE);
1390 u32 mem_limit = get_conf_word(d, PCI_MEMORY_LIMIT);
1391 u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
1392 u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE);
1393 u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT);
1394 u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
1395 word sec_stat = get_conf_word(d, PCI_SEC_STATUS);
1396 word brc = get_conf_word(d, PCI_BRIDGE_CONTROL);
1397 int verb = verbose > 2;
1400 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1401 get_conf_byte(d, PCI_PRIMARY_BUS),
1402 get_conf_byte(d, PCI_SECONDARY_BUS),
1403 get_conf_byte(d, PCI_SUBORDINATE_BUS),
1404 get_conf_byte(d, PCI_SEC_LATENCY_TIMER));
1406 if (io_type != (io_limit & PCI_IO_RANGE_TYPE_MASK) ||
1407 (io_type != PCI_IO_RANGE_TYPE_16 && io_type != PCI_IO_RANGE_TYPE_32))
1408 printf("\t!!! Unknown I/O range types %x/%x\n", io_base, io_limit);
1411 io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
1412 io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
1413 if (io_type == PCI_IO_RANGE_TYPE_32)
1415 io_base |= (get_conf_word(d, PCI_IO_BASE_UPPER16) << 16);
1416 io_limit |= (get_conf_word(d, PCI_IO_LIMIT_UPPER16) << 16);
1418 if (io_base <= io_limit || verb)
1419 printf("\tI/O behind bridge: %08x-%08x\n", io_base, io_limit+0xfff);
1422 if (mem_type != (mem_limit & PCI_MEMORY_RANGE_TYPE_MASK) ||
1424 printf("\t!!! Unknown memory range types %x/%x\n", mem_base, mem_limit);
1427 mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
1428 mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
1429 if (mem_base <= mem_limit || verb)
1430 printf("\tMemory behind bridge: %08x-%08x\n", mem_base, mem_limit + 0xfffff);
1433 if (pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
1434 (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64))
1435 printf("\t!!! Unknown prefetchable memory range types %x/%x\n", pref_base, pref_limit);
1438 pref_base = (pref_base & PCI_PREF_RANGE_MASK) << 16;
1439 pref_limit = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
1440 if (pref_base <= pref_limit || verb)
1442 if (pref_type == PCI_PREF_RANGE_TYPE_32)
1443 printf("\tPrefetchable memory behind bridge: %08x-%08x\n", pref_base, pref_limit + 0xfffff);
1445 printf("\tPrefetchable memory behind bridge: %08x%08x-%08x%08x\n",
1446 get_conf_long(d, PCI_PREF_BASE_UPPER32),
1448 get_conf_long(d, PCI_PREF_LIMIT_UPPER32),
1454 printf("\tSecondary status: 66MHz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c\n",
1455 FLAG(sec_stat, PCI_STATUS_66MHZ),
1456 FLAG(sec_stat, PCI_STATUS_FAST_BACK),
1457 FLAG(sec_stat, PCI_STATUS_PARITY),
1458 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1459 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1460 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1461 FLAG(sec_stat, PCI_STATUS_SIG_TARGET_ABORT),
1462 FLAG(sec_stat, PCI_STATUS_REC_TARGET_ABORT),
1463 FLAG(sec_stat, PCI_STATUS_REC_MASTER_ABORT),
1464 FLAG(sec_stat, PCI_STATUS_SIG_SYSTEM_ERROR),
1465 FLAG(sec_stat, PCI_STATUS_DETECTED_PARITY));
1467 show_rom(d, PCI_ROM_ADDRESS1);
1470 printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
1471 FLAG(brc, PCI_BRIDGE_CTL_PARITY),
1472 FLAG(brc, PCI_BRIDGE_CTL_SERR),
1473 FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
1474 FLAG(brc, PCI_BRIDGE_CTL_VGA),
1475 FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
1476 FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
1477 FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
1483 show_htype2(struct device *d)
1486 word cmd = get_conf_word(d, PCI_COMMAND);
1487 word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
1488 word exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
1489 int verb = verbose > 2;
1492 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1493 get_conf_byte(d, PCI_CB_PRIMARY_BUS),
1494 get_conf_byte(d, PCI_CB_CARD_BUS),
1495 get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
1496 get_conf_byte(d, PCI_CB_LATENCY_TIMER));
1500 u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
1501 u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
1502 if (limit > base || verb)
1503 printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
1504 (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
1505 (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
1510 u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
1511 u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
1512 if (!(base & PCI_IO_RANGE_TYPE_32))
1517 base &= PCI_CB_IO_RANGE_MASK;
1518 limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
1519 if (base <= limit || verb)
1520 printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
1521 (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
1524 if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
1525 printf("\tSecondary status: SERR\n");
1527 printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
1528 FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
1529 FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
1530 FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
1531 FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
1532 FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
1533 FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
1534 FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
1535 FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
1537 printf("\t16-bit legacy interface ports at %04x\n", exca);
1541 show_verbose(struct device *d)
1543 struct pci_dev *p = d->dev;
1544 word status = get_conf_word(d, PCI_STATUS);
1545 word cmd = get_conf_word(d, PCI_COMMAND);
1546 word class = get_conf_word(d, PCI_CLASS_DEVICE);
1547 byte bist = get_conf_byte(d, PCI_BIST);
1548 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1549 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
1550 byte cache_line = get_conf_byte(d, PCI_CACHE_LINE_SIZE);
1551 byte max_lat, min_gnt;
1552 byte int_pin = get_conf_byte(d, PCI_INTERRUPT_PIN);
1553 unsigned int irq = p->irq;
1554 word subsys_v, subsys_d;
1555 char ssnamebuf[256];
1561 case PCI_HEADER_TYPE_NORMAL:
1562 if (class == PCI_CLASS_BRIDGE_PCI)
1563 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1564 max_lat = get_conf_byte(d, PCI_MAX_LAT);
1565 min_gnt = get_conf_byte(d, PCI_MIN_GNT);
1566 subsys_v = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1567 subsys_d = get_conf_word(d, PCI_SUBSYSTEM_ID);
1569 case PCI_HEADER_TYPE_BRIDGE:
1570 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1571 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1572 irq = int_pin = min_gnt = max_lat = 0;
1573 subsys_v = subsys_d = 0;
1575 case PCI_HEADER_TYPE_CARDBUS:
1576 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1577 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1578 min_gnt = max_lat = 0;
1579 subsys_v = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1580 subsys_d = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1583 printf("\t!!! Unknown header type %02x\n", htype);
1587 if (subsys_v && subsys_v != 0xffff)
1588 printf("\tSubsystem: %s\n",
1589 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1590 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1591 p->vendor_id, p->device_id, subsys_v, subsys_d));
1595 printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c\n",
1596 FLAG(cmd, PCI_COMMAND_IO),
1597 FLAG(cmd, PCI_COMMAND_MEMORY),
1598 FLAG(cmd, PCI_COMMAND_MASTER),
1599 FLAG(cmd, PCI_COMMAND_SPECIAL),
1600 FLAG(cmd, PCI_COMMAND_INVALIDATE),
1601 FLAG(cmd, PCI_COMMAND_VGA_PALETTE),
1602 FLAG(cmd, PCI_COMMAND_PARITY),
1603 FLAG(cmd, PCI_COMMAND_WAIT),
1604 FLAG(cmd, PCI_COMMAND_SERR),
1605 FLAG(cmd, PCI_COMMAND_FAST_BACK));
1606 printf("\tStatus: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c\n",
1607 FLAG(status, PCI_STATUS_CAP_LIST),
1608 FLAG(status, PCI_STATUS_66MHZ),
1609 FLAG(status, PCI_STATUS_UDF),
1610 FLAG(status, PCI_STATUS_FAST_BACK),
1611 FLAG(status, PCI_STATUS_PARITY),
1612 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1613 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1614 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1615 FLAG(status, PCI_STATUS_SIG_TARGET_ABORT),
1616 FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
1617 FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
1618 FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
1619 FLAG(status, PCI_STATUS_DETECTED_PARITY));
1620 if (cmd & PCI_COMMAND_MASTER)
1622 printf("\tLatency: %d", latency);
1623 if (min_gnt || max_lat)
1627 printf("%dns min", min_gnt*250);
1628 if (min_gnt && max_lat)
1631 printf("%dns max", max_lat*250);
1635 printf(", Cache Line Size %02x", cache_line);
1639 printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n",
1640 (int_pin ? 'A' + int_pin - 1 : '?'), irq);
1644 printf("\tFlags: ");
1645 if (cmd & PCI_COMMAND_MASTER)
1646 printf("bus master, ");
1647 if (cmd & PCI_COMMAND_VGA_PALETTE)
1648 printf("VGA palette snoop, ");
1649 if (cmd & PCI_COMMAND_WAIT)
1650 printf("stepping, ");
1651 if (cmd & PCI_COMMAND_FAST_BACK)
1652 printf("fast Back2Back, ");
1653 if (status & PCI_STATUS_66MHZ)
1655 if (status & PCI_STATUS_UDF)
1656 printf("user-definable features, ");
1658 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1659 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1660 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??");
1661 if (cmd & PCI_COMMAND_MASTER)
1662 printf(", latency %d", latency);
1664 printf(", IRQ " PCIIRQ_FMT, irq);
1668 if (bist & PCI_BIST_CAPABLE)
1670 if (bist & PCI_BIST_START)
1671 printf("\tBIST is running\n");
1673 printf("\tBIST result: %02x\n", bist & PCI_BIST_CODE_MASK);
1678 case PCI_HEADER_TYPE_NORMAL:
1681 case PCI_HEADER_TYPE_BRIDGE:
1684 case PCI_HEADER_TYPE_CARDBUS:
1691 show_hex_dump(struct device *d)
1693 unsigned int i, cnt;
1695 cnt = d->config_cnt;
1696 if (show_hex >= 3 && config_fetch(d, cnt, 256-cnt))
1699 if (show_hex >= 4 && config_fetch(d, 256, 4096-256))
1703 for(i=0; i<cnt; i++)
1707 printf(" %02x", get_conf_byte(d, i));
1714 show_machine(struct device *d)
1716 struct pci_dev *p = d->dev;
1718 word sv_id=0, sd_id=0;
1719 char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
1721 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
1723 case PCI_HEADER_TYPE_NORMAL:
1724 sv_id = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1725 sd_id = get_conf_word(d, PCI_SUBSYSTEM_ID);
1727 case PCI_HEADER_TYPE_CARDBUS:
1728 sv_id = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1729 sd_id = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1735 printf("Device:\t");
1738 printf("Class:\t%s\n",
1739 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0));
1740 printf("Vendor:\t%s\n",
1741 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, 0, 0));
1742 printf("Device:\t%s\n",
1743 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, 0, 0));
1744 if (sv_id && sv_id != 0xffff)
1746 printf("SVendor:\t%s\n",
1747 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, sv_id, sd_id));
1748 printf("SDevice:\t%s\n",
1749 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1751 if (c = get_conf_byte(d, PCI_REVISION_ID))
1752 printf("Rev:\t%02x\n", c);
1753 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1754 printf("ProgIf:\t%02x\n", c);
1759 printf(" \"%s\" \"%s\" \"%s\"",
1760 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS,
1761 get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0),
1762 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR,
1763 p->vendor_id, p->device_id, 0, 0),
1764 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE,
1765 p->vendor_id, p->device_id, 0, 0));
1766 if (c = get_conf_byte(d, PCI_REVISION_ID))
1767 printf(" -r%02x", c);
1768 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1769 printf(" -p%02x", c);
1770 if (sv_id && sv_id != 0xffff)
1771 printf(" \"%s\" \"%s\"",
1772 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, sv_id, sd_id),
1773 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1775 printf(" \"\" \"\"");
1781 show_device(struct device *d)
1783 if (machine_readable)
1791 if (verbose || show_hex)
1800 for(d=first_dev; d; d=d->next)
1807 struct bridge *chain; /* Single-linked list of bridges */
1808 struct bridge *next, *child; /* Tree of bridges */
1809 struct bus *first_bus; /* List of buses connected to this bridge */
1810 unsigned int domain;
1811 unsigned int primary, secondary, subordinate; /* Bus numbers */
1812 struct device *br_dev;
1816 unsigned int domain;
1817 unsigned int number;
1818 struct bus *sibling;
1819 struct device *first_dev, **last_dev;
1822 static struct bridge host_bridge = { NULL, NULL, NULL, NULL, 0, ~0, 0, ~0, NULL };
1825 find_bus(struct bridge *b, unsigned int domain, unsigned int n)
1829 for(bus=b->first_bus; bus; bus=bus->sibling)
1830 if (bus->domain == domain && bus->number == n)
1836 new_bus(struct bridge *b, unsigned int domain, unsigned int n)
1838 struct bus *bus = xmalloc(sizeof(struct bus));
1840 bus = xmalloc(sizeof(struct bus));
1841 bus->domain = domain;
1843 bus->sibling = b->first_bus;
1844 bus->first_dev = NULL;
1845 bus->last_dev = &bus->first_dev;
1851 insert_dev(struct device *d, struct bridge *b)
1853 struct pci_dev *p = d->dev;
1856 if (! (bus = find_bus(b, p->domain, p->bus)))
1859 for(c=b->child; c; c=c->next)
1860 if (c->domain == p->domain && c->secondary <= p->bus && p->bus <= c->subordinate)
1865 bus = new_bus(b, p->domain, p->bus);
1867 /* Simple insertion at the end _does_ guarantee the correct order as the
1868 * original device list was sorted by (domain, bus, devfn) lexicographically
1869 * and all devices on the new list have the same bus number.
1872 bus->last_dev = &d->next;
1879 struct device *d, *d2;
1880 struct bridge **last_br, *b;
1882 /* Build list of bridges */
1884 last_br = &host_bridge.chain;
1885 for(d=first_dev; d; d=d->next)
1887 word class = get_conf_word(d, PCI_CLASS_DEVICE);
1888 byte ht = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1889 if (class == PCI_CLASS_BRIDGE_PCI &&
1890 (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS))
1892 b = xmalloc(sizeof(struct bridge));
1893 b->domain = d->dev->domain;
1894 if (ht == PCI_HEADER_TYPE_BRIDGE)
1896 b->primary = get_conf_byte(d, PCI_CB_PRIMARY_BUS);
1897 b->secondary = get_conf_byte(d, PCI_CB_CARD_BUS);
1898 b->subordinate = get_conf_byte(d, PCI_CB_SUBORDINATE_BUS);
1902 b->primary = get_conf_byte(d, PCI_PRIMARY_BUS);
1903 b->secondary = get_conf_byte(d, PCI_SECONDARY_BUS);
1904 b->subordinate = get_conf_byte(d, PCI_SUBORDINATE_BUS);
1907 last_br = &b->chain;
1908 b->next = b->child = NULL;
1909 b->first_bus = NULL;
1915 /* Create a bridge tree */
1917 for(b=&host_bridge; b; b=b->chain)
1919 struct bridge *c, *best;
1921 for(c=&host_bridge; c; c=c->chain)
1922 if (c != b && (c == &host_bridge || b->domain == c->domain) &&
1923 b->primary >= c->secondary && b->primary <= c->subordinate &&
1924 (!best || best->subordinate - best->primary > c->subordinate - c->primary))
1928 b->next = best->child;
1933 /* Insert secondary bus for each bridge */
1935 for(b=&host_bridge; b; b=b->chain)
1936 if (!find_bus(b, b->domain, b->secondary))
1937 new_bus(b, b->domain, b->secondary);
1939 /* Create bus structs and link devices */
1941 for(d=first_dev; d;)
1944 insert_dev(d, &host_bridge);
1950 print_it(byte *line, byte *p)
1954 fputs(line, stdout);
1955 for(p=line; *p; p++)
1956 if (*p == '+' || *p == '|')
1962 static void show_tree_bridge(struct bridge *, byte *, byte *);
1965 show_tree_dev(struct device *d, byte *line, byte *p)
1967 struct pci_dev *q = d->dev;
1971 p += sprintf(p, "%02x.%x", q->dev, q->func);
1972 for(b=&host_bridge; b; b=b->chain)
1975 if (b->secondary == b->subordinate)
1976 p += sprintf(p, "-[%04x:%02x]-", b->domain, b->secondary);
1978 p += sprintf(p, "-[%04x:%02x-%02x]-", b->domain, b->secondary, b->subordinate);
1979 show_tree_bridge(b, line, p);
1983 p += sprintf(p, " %s",
1984 pci_lookup_name(pacc, namebuf, sizeof(namebuf),
1985 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1986 q->vendor_id, q->device_id, 0, 0));
1991 show_tree_bus(struct bus *b, byte *line, byte *p)
1995 else if (!b->first_dev->next)
1999 show_tree_dev(b->first_dev, line, p);
2003 struct device *d = b->first_dev;
2008 show_tree_dev(d, line, p+2);
2013 show_tree_dev(d, line, p+2);
2018 show_tree_bridge(struct bridge *b, byte *line, byte *p)
2021 if (!b->first_bus->sibling)
2023 if (b == &host_bridge)
2024 p += sprintf(p, "[%04x:%02x]-", b->domain, b->first_bus->number);
2025 show_tree_bus(b->first_bus, line, p);
2029 struct bus *u = b->first_bus;
2034 k = p + sprintf(p, "+-[%04x:%02x]-", u->domain, u->number);
2035 show_tree_bus(u, line, k);
2038 k = p + sprintf(p, "\\-[%04x:%02x]-", u->domain, u->number);
2039 show_tree_bus(u, line, k);
2049 show_tree_bridge(&host_bridge, line, line);
2052 /* Bus mapping mode */
2055 struct bus_bridge *next;
2056 byte this, dev, func, first, last, bug;
2062 struct bus_bridge *bridges, *via;
2065 static struct bus_info *bus_info;
2068 map_bridge(struct bus_info *bi, struct device *d, int np, int ns, int nl)
2070 struct bus_bridge *b = xmalloc(sizeof(struct bus_bridge));
2071 struct pci_dev *p = d->dev;
2073 b->next = bi->bridges;
2075 b->this = get_conf_byte(d, np);
2078 b->first = get_conf_byte(d, ns);
2079 b->last = get_conf_byte(d, nl);
2080 printf("## %02x.%02x:%d is a bridge from %02x to %02x-%02x\n",
2081 p->bus, p->dev, p->func, b->this, b->first, b->last);
2082 if (b->this != p->bus)
2083 printf("!!! Bridge points to invalid primary bus.\n");
2084 if (b->first > b->last)
2086 printf("!!! Bridge points to invalid bus range.\n");
2095 int verbose = pacc->debugging;
2096 struct bus_info *bi = bus_info + bus;
2100 printf("Mapping bus %02x\n", bus);
2101 for(dev = 0; dev < 32; dev++)
2102 if (filter.slot < 0 || filter.slot == dev)
2105 for(func = 0; func < func_limit; func++)
2106 if (filter.func < 0 || filter.func == func)
2108 /* XXX: Bus mapping supports only domain 0 */
2109 struct pci_dev *p = pci_get_dev(pacc, 0, bus, dev, func);
2110 u16 vendor = pci_read_word(p, PCI_VENDOR_ID);
2111 if (vendor && vendor != 0xffff)
2113 if (!func && (pci_read_byte(p, PCI_HEADER_TYPE) & 0x80))
2116 printf("Discovered device %02x:%02x.%d\n", bus, dev, func);
2118 if (d = scan_device(p))
2121 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
2123 case PCI_HEADER_TYPE_BRIDGE:
2124 map_bridge(bi, d, PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS);
2126 case PCI_HEADER_TYPE_CARDBUS:
2127 map_bridge(bi, d, PCI_CB_PRIMARY_BUS, PCI_CB_CARD_BUS, PCI_CB_SUBORDINATE_BUS);
2133 printf("But it was filtered out.\n");
2141 do_map_bridges(int bus, int min, int max)
2143 struct bus_info *bi = bus_info + bus;
2144 struct bus_bridge *b;
2147 for(b=bi->bridges; b; b=b->next)
2149 if (bus_info[b->first].guestbook)
2151 else if (b->first < min || b->last > max)
2155 bus_info[b->first].via = b;
2156 do_map_bridges(b->first, b->first, b->last);
2166 printf("\nSummary of buses:\n\n");
2167 for(i=0; i<256; i++)
2168 if (bus_info[i].exists && !bus_info[i].guestbook)
2169 do_map_bridges(i, 0, 255);
2170 for(i=0; i<256; i++)
2172 struct bus_info *bi = bus_info + i;
2173 struct bus_bridge *b = bi->via;
2177 printf("%02x: ", i);
2179 printf("Entered via %02x:%02x.%d\n", b->this, b->dev, b->func);
2181 printf("Primary host bus\n");
2183 printf("Secondary host bus (?)\n");
2185 for(b=bi->bridges; b; b=b->next)
2187 printf("\t%02x.%d Bridge to %02x-%02x", b->dev, b->func, b->first, b->last);
2191 printf(" <overlap bug>");
2194 printf(" <crossing bug>");
2205 if (pacc->method == PCI_ACCESS_PROC_BUS_PCI ||
2206 pacc->method == PCI_ACCESS_DUMP)
2207 printf("WARNING: Bus mapping can be reliable only with direct hardware access enabled.\n\n");
2208 bus_info = xmalloc(sizeof(struct bus_info) * 256);
2209 bzero(bus_info, sizeof(struct bus_info) * 256);
2210 if (filter.bus >= 0)
2211 do_map_bus(filter.bus);
2215 for(bus=0; bus<256; bus++)
2224 main(int argc, char **argv)
2229 if (argc == 2 && !strcmp(argv[1], "--version"))
2231 puts("lspci version " PCIUTILS_VERSION);
2237 pci_filter_init(pacc, &filter);
2239 while ((i = getopt(argc, argv, options)) != -1)
2243 pacc->numeric_ids = 1;
2249 pacc->buscentric = 1;
2250 buscentric_view = 1;
2253 if (msg = pci_filter_parse_slot(&filter, optarg))
2257 if (msg = pci_filter_parse_id(&filter, optarg))
2267 pacc->id_file_name = optarg;
2276 if (parse_generic_option(i, pacc, optarg))
2279 fprintf(stderr, help_msg, pacc->id_file_name);