2 * The PCI Utilities -- List All PCI Devices
4 * Copyright (c) 1997--2006 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
19 static int verbose; /* Show detailed information */
20 static int buscentric_view; /* Show bus addresses/IRQ's instead of CPU-visible ones */
21 static int show_hex; /* Show contents of config space as hexadecimal numbers */
22 static struct pci_filter filter; /* Device filter */
23 static int show_tree; /* Show bus tree */
24 static int machine_readable; /* Generate machine-readable output */
25 static int map_mode; /* Bus mapping mode enabled */
26 static int show_domains; /* Show domain numbers (0=disabled, 1=auto-detected, 2=requested) */
28 static char options[] = "nvbxs:d:ti:mgMD" GENERIC_OPTIONS ;
30 static char help_msg[] = "\
31 Usage: lspci [<switches>]\n\
34 -n\t\tShow numeric ID's\n\
35 -b\t\tBus-centric view (PCI addresses and IRQ's instead of those seen by the CPU)\n\
36 -x\t\tShow hex-dump of the standard portion of config space\n\
37 -xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n\
38 -xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n\
39 -s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n\
40 -d [<vendor>]:[<device>]\tShow only selected devices\n\
41 -t\t\tShow bus tree\n\
42 -m\t\tProduce machine-readable output\n\
43 -i <file>\tUse specified ID database instead of %s\n\
44 -D\t\tAlways show domain numbers\n\
45 -M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
49 /* Communication with libpci */
51 static struct pci_access *pacc;
54 * If we aren't being compiled by GCC, use xmalloc() instead of alloca().
55 * This increases our memory footprint, but only slightly since we don't
61 #define alloca xmalloc
64 /* Our view of the PCI bus */
69 unsigned int config_cached, config_bufsize;
70 byte *config; /* Cached configuration space data */
71 byte *present; /* Maps which configuration bytes are present */
74 static struct device *first_dev;
77 config_fetch(struct device *d, unsigned int pos, unsigned int len)
79 unsigned int end = pos+len;
82 while (pos < d->config_bufsize && len && d->present[pos])
84 while (pos+len <= d->config_bufsize && len && d->present[pos+len-1])
89 if (end > d->config_bufsize)
91 int orig_size = d->config_bufsize;
92 while (end > d->config_bufsize)
93 d->config_bufsize *= 2;
94 d->config = xrealloc(d->config, d->config_bufsize);
95 d->present = xrealloc(d->present, d->config_bufsize);
96 bzero(d->present + orig_size, d->config_bufsize - orig_size);
98 result = pci_read_block(d->dev, pos, d->config + pos, len);
100 memset(d->present + pos, 1, len);
104 static struct device *
105 scan_device(struct pci_dev *p)
109 if (p->domain && !show_domains)
111 if (!pci_filter_match(&filter, p))
113 d = xmalloc(sizeof(struct device));
114 bzero(d, sizeof(*d));
116 d->config_cached = d->config_bufsize = 64;
117 d->config = xmalloc(64);
118 d->present = xmalloc(64);
119 memset(d->present, 1, 64);
120 if (!pci_read_block(p, 0, d->config, 64))
121 die("Unable to read the standard configuration space header");
122 if ((d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
124 /* For cardbus bridges, we need to fetch 64 bytes more to get the
125 * full standard header... */
126 if (config_fetch(d, 64, 64))
127 d->config_cached += 64;
129 pci_setup_cache(p, d->config, d->config_cached);
130 pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
141 for(p=pacc->devices; p; p=p->next)
142 if (d = scan_device(p))
149 /* Config space accesses */
152 check_conf_range(struct device *d, unsigned int pos, unsigned int len)
155 if (!d->present[pos])
156 die("Internal bug: Accessing non-read configuration byte at position %x", pos);
162 get_conf_byte(struct device *d, unsigned int pos)
164 check_conf_range(d, pos, 1);
165 return d->config[pos];
169 get_conf_word(struct device *d, unsigned int pos)
171 check_conf_range(d, pos, 2);
172 return d->config[pos] | (d->config[pos+1] << 8);
176 get_conf_long(struct device *d, unsigned int pos)
178 check_conf_range(d, pos, 4);
179 return d->config[pos] |
180 (d->config[pos+1] << 8) |
181 (d->config[pos+2] << 16) |
182 (d->config[pos+3] << 24);
188 compare_them(const void *A, const void *B)
190 const struct pci_dev *a = (*(const struct device **)A)->dev;
191 const struct pci_dev *b = (*(const struct device **)B)->dev;
193 if (a->domain < b->domain)
195 if (a->domain > b->domain)
205 if (a->func < b->func)
207 if (a->func > b->func)
215 struct device **index, **h, **last_dev;
220 for(d=first_dev; d; d=d->next)
222 h = index = alloca(sizeof(struct device *) * cnt);
223 for(d=first_dev; d; d=d->next)
225 qsort(index, cnt, sizeof(struct device *), compare_them);
226 last_dev = &first_dev;
231 last_dev = &(*h)->next;
239 #define FLAG(x,y) ((x & y) ? '+' : '-')
242 show_slot_name(struct device *d)
244 struct pci_dev *p = d->dev;
246 if (!machine_readable ? show_domains : (p->domain || show_domains >= 2))
247 printf("%04x:", p->domain);
248 printf("%02x:%02x.%d", p->bus, p->dev, p->func);
252 show_terse(struct device *d)
255 struct pci_dev *p = d->dev;
256 byte classbuf[128], devbuf[128];
260 pci_lookup_name(pacc, classbuf, sizeof(classbuf),
262 get_conf_word(d, PCI_CLASS_DEVICE)),
263 pci_lookup_name(pacc, devbuf, sizeof(devbuf),
264 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
265 p->vendor_id, p->device_id));
266 if (c = get_conf_byte(d, PCI_REVISION_ID))
267 printf(" (rev %02x)", c);
271 c = get_conf_byte(d, PCI_CLASS_PROG);
272 x = pci_lookup_name(pacc, devbuf, sizeof(devbuf),
273 PCI_LOOKUP_PROGIF | PCI_LOOKUP_NO_NUMBERS,
274 get_conf_word(d, PCI_CLASS_DEVICE), c);
277 printf(" (prog-if %02x", c);
287 show_size(pciaddr_t x)
293 printf("%d", (int) x);
294 else if (x < 1048576)
295 printf("%dK", (int)(x / 1024));
296 else if (x < 0x80000000)
297 printf("%dM", (int)(x / 1048576));
299 printf(PCIADDR_T_FMT, x);
304 show_bases(struct device *d, int cnt)
306 struct pci_dev *p = d->dev;
307 word cmd = get_conf_word(d, PCI_COMMAND);
312 pciaddr_t pos = p->base_addr[i];
313 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
314 u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
315 if (flg == 0xffffffff)
317 if (!pos && !flg && !len)
320 printf("\tRegion %d: ", i);
323 if (pos && !flg) /* Reported by the OS, but not by the device */
325 printf("[virtual] ");
328 if (flg & PCI_BASE_ADDRESS_SPACE_IO)
330 pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
331 printf("I/O ports at ");
333 printf(PCIADDR_PORT_FMT, a);
334 else if (flg & PCI_BASE_ADDRESS_IO_MASK)
337 printf("<unassigned>");
338 if (!(cmd & PCI_COMMAND_IO))
339 printf(" [disabled]");
343 int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
344 pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
348 printf("Memory at ");
349 if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
353 printf("<invalid-64bit-slot>");
359 z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
362 u32 y = a & 0xffffffff;
364 printf("%08x%08x", z, y);
366 printf("<unassigned>");
374 printf(PCIADDR_T_FMT, a);
376 printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
378 printf(" (%s, %sprefetchable)",
379 (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
380 (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
381 (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
382 (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
383 if (!(cmd & PCI_COMMAND_MEMORY))
384 printf(" [disabled]");
392 show_pm(struct device *d, int where, int cap)
395 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
397 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
400 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
401 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
402 FLAG(cap, PCI_PM_CAP_DSI),
403 FLAG(cap, PCI_PM_CAP_D1),
404 FLAG(cap, PCI_PM_CAP_D2),
405 pm_aux_current[(cap >> 6) & 7],
406 FLAG(cap, PCI_PM_CAP_PME_D0),
407 FLAG(cap, PCI_PM_CAP_PME_D1),
408 FLAG(cap, PCI_PM_CAP_PME_D2),
409 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
410 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
411 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
413 t = get_conf_word(d, where + PCI_PM_CTRL);
414 printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
415 t & PCI_PM_CTRL_STATE_MASK,
416 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
417 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
418 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
419 FLAG(t, PCI_PM_CTRL_PME_STATUS));
420 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
422 printf("\t\tBridge: PM%c B3%c\n",
423 FLAG(t, PCI_PM_BPCC_ENABLE),
424 FLAG(~t, PCI_PM_PPB_B2_B3));
428 format_agp_rate(int rate, char *buf, int agp3)
438 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
443 strcpy(buf, "<none>");
447 show_agp(struct device *d, int where, int cap)
454 ver = (cap >> 4) & 0x0f;
456 printf("AGP version %x.%x\n", ver, rev);
459 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
461 t = get_conf_long(d, where + PCI_AGP_STATUS);
462 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
464 format_agp_rate(t & 7, rate, agp3);
465 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
466 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
467 FLAG(t, PCI_AGP_STATUS_ISOCH),
468 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
469 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
470 FLAG(t, PCI_AGP_STATUS_SBA),
471 FLAG(t, PCI_AGP_STATUS_ITA_COH),
472 FLAG(t, PCI_AGP_STATUS_GART64),
473 FLAG(t, PCI_AGP_STATUS_HTRANS),
474 FLAG(t, PCI_AGP_STATUS_64BIT),
475 FLAG(t, PCI_AGP_STATUS_FW),
476 FLAG(t, PCI_AGP_STATUS_AGP3),
478 t = get_conf_long(d, where + PCI_AGP_COMMAND);
479 format_agp_rate(t & 7, rate, agp3);
480 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
481 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
482 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
483 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
484 FLAG(t, PCI_AGP_COMMAND_SBA),
485 FLAG(t, PCI_AGP_COMMAND_AGP),
486 FLAG(t, PCI_AGP_COMMAND_GART64),
487 FLAG(t, PCI_AGP_COMMAND_64BIT),
488 FLAG(t, PCI_AGP_COMMAND_FW),
493 show_pcix_nobridge(struct device *d, int where)
497 static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
499 printf("PCI-X non-bridge device\n");
504 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
507 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
508 status = get_conf_long(d, where + PCI_PCIX_STATUS);
509 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
510 FLAG(command, PCI_PCIX_COMMAND_DPERE),
511 FLAG(command, PCI_PCIX_COMMAND_ERO),
512 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
513 max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
514 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
515 ((status >> 8) & 0xff),
516 ((status >> 3) & 0x1f),
517 (status & PCI_PCIX_STATUS_FUNCTION),
518 FLAG(status, PCI_PCIX_STATUS_64BIT),
519 FLAG(status, PCI_PCIX_STATUS_133MHZ),
520 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
521 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
522 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
523 1 << (9 + ((status >> 21) & 3U)),
524 max_outstanding[(status >> 23) & 7U],
525 1 << (3 + ((status >> 26) & 7U)),
526 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
527 FLAG(status, PCI_PCIX_STATUS_266MHZ),
528 FLAG(status, PCI_PCIX_STATUS_533MHZ));
532 show_pcix_bridge(struct device *d, int where)
534 static const byte * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
536 u32 status, upstcr, downstcr;
538 printf("PCI-X bridge device\n");
543 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
546 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
547 printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
548 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
549 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
550 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
551 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
552 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
553 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
554 sec_clock_freq[(secstatus >> 6) & 7]);
555 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
556 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
557 ((status >> 8) & 0xff),
558 ((status >> 3) & 0x1f),
559 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
560 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
561 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
562 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
563 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
564 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
565 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
566 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
567 printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
568 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
569 (upstcr >> 16) & 0xffff);
570 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
571 printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
572 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
573 (downstcr >> 16) & 0xffff);
577 show_pcix(struct device *d, int where)
579 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
581 case PCI_HEADER_TYPE_NORMAL:
582 show_pcix_nobridge(d, where);
584 case PCI_HEADER_TYPE_BRIDGE:
585 show_pcix_bridge(d, where);
591 ht_link_width(unsigned width)
593 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
594 return widths[width];
598 ht_link_freq(unsigned freq)
600 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
601 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
606 show_ht_pri(struct device *d, int where, int cmd)
608 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
609 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
612 printf("HyperTransport: Slave or Primary Interface\n");
616 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
618 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
619 if (rid < 0x23 && rid > 0x11)
620 printf("\t\t!!! Possibly incomplete decoding\n");
623 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
625 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
627 (cmd & PCI_HT_PRI_CMD_BUID),
628 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
629 FLAG(cmd, PCI_HT_PRI_CMD_MH),
630 FLAG(cmd, PCI_HT_PRI_CMD_DD),
631 FLAG(cmd, PCI_HT_PRI_CMD_DUL));
632 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
634 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
636 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
638 FLAG(lctr0, PCI_HT_LCTR_CFLE),
639 FLAG(lctr0, PCI_HT_LCTR_CST),
640 FLAG(lctr0, PCI_HT_LCTR_CFE),
641 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
642 FLAG(lctr0, PCI_HT_LCTR_INIT),
643 FLAG(lctr0, PCI_HT_LCTR_EOC),
644 FLAG(lctr0, PCI_HT_LCTR_TXO),
645 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
646 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
647 FLAG(lctr0, PCI_HT_LCTR_LSEN),
648 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
649 FLAG(lctr0, PCI_HT_LCTR_64B));
650 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
652 fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
654 fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
656 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
657 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
658 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
659 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
660 FLAG(lcnf0, PCI_HT_LCNF_DFI),
661 FLAG(lcnf0, PCI_HT_LCNF_DFO),
662 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
663 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
664 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
666 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
668 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
670 FLAG(lctr1, PCI_HT_LCTR_CFLE),
671 FLAG(lctr1, PCI_HT_LCTR_CST),
672 FLAG(lctr1, PCI_HT_LCTR_CFE),
673 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
674 FLAG(lctr1, PCI_HT_LCTR_INIT),
675 FLAG(lctr1, PCI_HT_LCTR_EOC),
676 FLAG(lctr1, PCI_HT_LCTR_TXO),
677 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
678 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
679 FLAG(lctr1, PCI_HT_LCTR_LSEN),
680 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
681 FLAG(lctr1, PCI_HT_LCTR_64B));
682 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
684 fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
686 fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
688 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
689 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
690 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
691 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
692 FLAG(lcnf1, PCI_HT_LCNF_DFI),
693 FLAG(lcnf1, PCI_HT_LCNF_DFO),
694 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
695 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
696 printf("\t\tRevision ID: %u.%02u\n",
697 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
700 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
701 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
702 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
703 FLAG(lfrer0, PCI_HT_LFRER_PROT),
704 FLAG(lfrer0, PCI_HT_LFRER_OV),
705 FLAG(lfrer0, PCI_HT_LFRER_EOC),
706 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
707 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
708 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
709 FLAG(lfcap0, PCI_HT_LFCAP_200),
710 FLAG(lfcap0, PCI_HT_LFCAP_300),
711 FLAG(lfcap0, PCI_HT_LFCAP_400),
712 FLAG(lfcap0, PCI_HT_LFCAP_500),
713 FLAG(lfcap0, PCI_HT_LFCAP_600),
714 FLAG(lfcap0, PCI_HT_LFCAP_800),
715 FLAG(lfcap0, PCI_HT_LFCAP_1000),
716 FLAG(lfcap0, PCI_HT_LFCAP_1200),
717 FLAG(lfcap0, PCI_HT_LFCAP_1400),
718 FLAG(lfcap0, PCI_HT_LFCAP_1600),
719 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
720 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
721 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
722 FLAG(ftr, PCI_HT_FTR_ISOCFC),
723 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
724 FLAG(ftr, PCI_HT_FTR_CRCTM),
725 FLAG(ftr, PCI_HT_FTR_ECTLT),
726 FLAG(ftr, PCI_HT_FTR_64BA),
727 FLAG(ftr, PCI_HT_FTR_UIDRD));
728 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
729 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
730 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
731 FLAG(lfrer1, PCI_HT_LFRER_PROT),
732 FLAG(lfrer1, PCI_HT_LFRER_OV),
733 FLAG(lfrer1, PCI_HT_LFRER_EOC),
734 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
735 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
736 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
737 FLAG(lfcap1, PCI_HT_LFCAP_200),
738 FLAG(lfcap1, PCI_HT_LFCAP_300),
739 FLAG(lfcap1, PCI_HT_LFCAP_400),
740 FLAG(lfcap1, PCI_HT_LFCAP_500),
741 FLAG(lfcap1, PCI_HT_LFCAP_600),
742 FLAG(lfcap1, PCI_HT_LFCAP_800),
743 FLAG(lfcap1, PCI_HT_LFCAP_1000),
744 FLAG(lfcap1, PCI_HT_LFCAP_1200),
745 FLAG(lfcap1, PCI_HT_LFCAP_1400),
746 FLAG(lfcap1, PCI_HT_LFCAP_1600),
747 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
748 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
749 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
750 FLAG(eh, PCI_HT_EH_PFLE),
751 FLAG(eh, PCI_HT_EH_OFLE),
752 FLAG(eh, PCI_HT_EH_PFE),
753 FLAG(eh, PCI_HT_EH_OFE),
754 FLAG(eh, PCI_HT_EH_EOCFE),
755 FLAG(eh, PCI_HT_EH_RFE),
756 FLAG(eh, PCI_HT_EH_CRCFE),
757 FLAG(eh, PCI_HT_EH_SERRFE),
758 FLAG(eh, PCI_HT_EH_CF),
759 FLAG(eh, PCI_HT_EH_RE),
760 FLAG(eh, PCI_HT_EH_PNFE),
761 FLAG(eh, PCI_HT_EH_ONFE),
762 FLAG(eh, PCI_HT_EH_EOCNFE),
763 FLAG(eh, PCI_HT_EH_RNFE),
764 FLAG(eh, PCI_HT_EH_CRCNFE),
765 FLAG(eh, PCI_HT_EH_SERRNFE));
766 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
767 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
768 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
769 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
770 printf("\t\tBus Number: %02x\n", bn);
774 show_ht_sec(struct device *d, int where, int cmd)
776 u16 lctr, lcnf, ftr, eh;
777 u8 rid, lfrer, lfcap, mbu, mlu;
780 printf("HyperTransport: Host or Secondary Interface\n");
784 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
786 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
787 if (rid < 0x23 && rid > 0x11)
788 printf("\t\t!!! Possibly incomplete decoding\n");
791 fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
793 fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
795 FLAG(cmd, PCI_HT_SEC_CMD_WR),
796 FLAG(cmd, PCI_HT_SEC_CMD_DE),
797 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
798 FLAG(cmd, PCI_HT_SEC_CMD_CS),
799 FLAG(cmd, PCI_HT_SEC_CMD_HH),
800 FLAG(cmd, PCI_HT_SEC_CMD_AS),
801 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
802 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
803 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
805 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
807 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
809 FLAG(lctr, PCI_HT_LCTR_CFLE),
810 FLAG(lctr, PCI_HT_LCTR_CST),
811 FLAG(lctr, PCI_HT_LCTR_CFE),
812 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
813 FLAG(lctr, PCI_HT_LCTR_INIT),
814 FLAG(lctr, PCI_HT_LCTR_EOC),
815 FLAG(lctr, PCI_HT_LCTR_TXO),
816 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
817 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
818 FLAG(lctr, PCI_HT_LCTR_LSEN),
819 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
820 FLAG(lctr, PCI_HT_LCTR_64B));
821 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
823 fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
825 fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
827 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
828 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
829 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
830 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
831 FLAG(lcnf, PCI_HT_LCNF_DFI),
832 FLAG(lcnf, PCI_HT_LCNF_DFO),
833 FLAG(lcnf, PCI_HT_LCNF_DFIE),
834 FLAG(lcnf, PCI_HT_LCNF_DFOE));
835 printf("\t\tRevision ID: %u.%02u\n",
836 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
839 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
840 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
841 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
842 FLAG(lfrer, PCI_HT_LFRER_PROT),
843 FLAG(lfrer, PCI_HT_LFRER_OV),
844 FLAG(lfrer, PCI_HT_LFRER_EOC),
845 FLAG(lfrer, PCI_HT_LFRER_CTLT));
846 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
847 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
848 FLAG(lfcap, PCI_HT_LFCAP_200),
849 FLAG(lfcap, PCI_HT_LFCAP_300),
850 FLAG(lfcap, PCI_HT_LFCAP_400),
851 FLAG(lfcap, PCI_HT_LFCAP_500),
852 FLAG(lfcap, PCI_HT_LFCAP_600),
853 FLAG(lfcap, PCI_HT_LFCAP_800),
854 FLAG(lfcap, PCI_HT_LFCAP_1000),
855 FLAG(lfcap, PCI_HT_LFCAP_1200),
856 FLAG(lfcap, PCI_HT_LFCAP_1400),
857 FLAG(lfcap, PCI_HT_LFCAP_1600),
858 FLAG(lfcap, PCI_HT_LFCAP_VEND));
859 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
860 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
861 FLAG(ftr, PCI_HT_FTR_ISOCFC),
862 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
863 FLAG(ftr, PCI_HT_FTR_CRCTM),
864 FLAG(ftr, PCI_HT_FTR_ECTLT),
865 FLAG(ftr, PCI_HT_FTR_64BA),
866 FLAG(ftr, PCI_HT_FTR_UIDRD),
867 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
868 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
869 if (ftr & PCI_HT_SEC_FTR_EXTRS)
871 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
872 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
873 FLAG(eh, PCI_HT_EH_PFLE),
874 FLAG(eh, PCI_HT_EH_OFLE),
875 FLAG(eh, PCI_HT_EH_PFE),
876 FLAG(eh, PCI_HT_EH_OFE),
877 FLAG(eh, PCI_HT_EH_EOCFE),
878 FLAG(eh, PCI_HT_EH_RFE),
879 FLAG(eh, PCI_HT_EH_CRCFE),
880 FLAG(eh, PCI_HT_EH_SERRFE),
881 FLAG(eh, PCI_HT_EH_CF),
882 FLAG(eh, PCI_HT_EH_RE),
883 FLAG(eh, PCI_HT_EH_PNFE),
884 FLAG(eh, PCI_HT_EH_ONFE),
885 FLAG(eh, PCI_HT_EH_EOCNFE),
886 FLAG(eh, PCI_HT_EH_RNFE),
887 FLAG(eh, PCI_HT_EH_CRCNFE),
888 FLAG(eh, PCI_HT_EH_SERRNFE));
889 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
890 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
891 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
896 show_ht(struct device *d, int where, int cmd)
900 switch (cmd & PCI_HT_CMD_TYP_HI)
902 case PCI_HT_CMD_TYP_HI_PRI:
903 show_ht_pri(d, where, cmd);
905 case PCI_HT_CMD_TYP_HI_SEC:
906 show_ht_sec(d, where, cmd);
910 type = cmd & PCI_HT_CMD_TYP;
913 case PCI_HT_CMD_TYP_SW:
914 printf("HyperTransport: Switch\n");
916 case PCI_HT_CMD_TYP_IDC:
917 printf("HyperTransport: Interrupt Discovery and Configuration\n");
919 case PCI_HT_CMD_TYP_RID:
920 printf("HyperTransport: Revision ID: %u.%02u\n",
921 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
923 case PCI_HT_CMD_TYP_UIDC:
924 printf("HyperTransport: UnitID Clumping\n");
926 case PCI_HT_CMD_TYP_ECSA:
927 printf("HyperTransport: Extended Configuration Space Access\n");
929 case PCI_HT_CMD_TYP_AM:
930 printf("HyperTransport: Address Mapping\n");
932 case PCI_HT_CMD_TYP_MSIM:
933 printf("HyperTransport: MSI Mapping\n");
935 case PCI_HT_CMD_TYP_DR:
936 printf("HyperTransport: DirectRoute\n");
938 case PCI_HT_CMD_TYP_VCS:
939 printf("HyperTransport: VCSet\n");
941 case PCI_HT_CMD_TYP_RM:
942 printf("HyperTransport: Retry Mode\n");
944 case PCI_HT_CMD_TYP_X86:
945 printf("HyperTransport: X86 (reserved)\n");
948 printf("HyperTransport: #%02x\n", type >> 11);
953 show_rom(struct device *d, int reg)
955 struct pci_dev *p = d->dev;
956 pciaddr_t rom = p->rom_base_addr;
957 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
958 u32 flg = get_conf_long(d, reg);
959 word cmd = get_conf_word(d, PCI_COMMAND);
961 if (!rom && !flg && !len)
964 if ((rom & PCI_ROM_ADDRESS_MASK) && !(flg & PCI_ROM_ADDRESS_MASK))
966 printf("[virtual] ");
969 printf("Expansion ROM at ");
970 if (rom & PCI_ROM_ADDRESS_MASK)
971 printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
972 else if (flg & PCI_ROM_ADDRESS_MASK)
975 printf("<unassigned>");
976 if (!(flg & PCI_ROM_ADDRESS_ENABLE))
977 printf(" [disabled]");
978 else if (!(cmd & PCI_COMMAND_MEMORY))
979 printf(" [disabled by cmd]");
985 show_msi(struct device *d, int where, int cap)
991 printf("Message Signalled Interrupts: 64bit%c Queue=%d/%d Enable%c\n",
992 FLAG(cap, PCI_MSI_FLAGS_64BIT),
993 (cap & PCI_MSI_FLAGS_QSIZE) >> 4,
994 (cap & PCI_MSI_FLAGS_QMASK) >> 1,
995 FLAG(cap, PCI_MSI_FLAGS_ENABLE));
998 is64 = cap & PCI_MSI_FLAGS_64BIT;
999 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
1001 printf("\t\tAddress: ");
1004 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
1005 w = get_conf_word(d, where + PCI_MSI_DATA_64);
1009 w = get_conf_word(d, where + PCI_MSI_DATA_32);
1010 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
1011 printf("%08x Data: %04x\n", t, w);
1014 static void show_vendor(void)
1016 printf("Vendor Specific Information\n");
1019 static void show_debug(void)
1021 printf("Debug port\n");
1024 static float power_limit(int value, int scale)
1026 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
1027 return value * scales[scale];
1030 static const char *latency_l0s(int value)
1032 static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
1033 return latencies[value];
1036 static const char *latency_l1(int value)
1038 static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
1039 return latencies[value];
1042 static void show_express_dev(struct device *d, int where, int type)
1047 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
1048 printf("\t\tDevice: Supported: MaxPayload %d bytes, PhantFunc %d, ExtTag%c\n",
1049 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
1050 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
1051 FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
1052 printf("\t\tDevice: Latency L0s %s, L1 %s\n",
1053 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
1054 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
1055 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
1056 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
1057 printf("\t\tDevice: AtnBtn%c AtnInd%c PwrInd%c\n",
1058 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
1059 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
1060 if (type == PCI_EXP_TYPE_UPSTREAM)
1061 printf("\t\tDevice: SlotPowerLimit %f\n",
1062 power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
1063 (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
1065 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
1066 printf("\t\tDevice: Errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
1067 FLAG(w, PCI_EXP_DEVCTL_CERE),
1068 FLAG(w, PCI_EXP_DEVCTL_NFERE),
1069 FLAG(w, PCI_EXP_DEVCTL_FERE),
1070 FLAG(w, PCI_EXP_DEVCTL_URRE));
1071 printf("\t\tDevice: RlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c\n",
1072 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
1073 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
1074 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
1075 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
1076 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
1077 printf("\t\tDevice: MaxPayload %d bytes, MaxReadReq %d bytes\n",
1078 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
1079 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
1082 static char *link_speed(int speed)
1093 static char *aspm_support(int code)
1106 static const char *aspm_enabled(int code)
1108 static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
1112 static void show_express_link(struct device *d, int where, int type)
1117 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
1118 printf("\t\tLink: Supported Speed %s, Width x%d, ASPM %s, Port %d\n",
1119 link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
1120 aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
1122 printf("\t\tLink: Latency L0s %s, L1 %s\n",
1123 latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
1124 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
1125 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
1126 printf("\t\tLink: ASPM %s", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
1127 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
1128 (type == PCI_EXP_TYPE_LEG_END))
1129 printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
1130 if (w & PCI_EXP_LNKCTL_DISABLE)
1131 printf(" Disabled");
1132 printf(" CommClk%c ExtSynch%c\n", FLAG(w, PCI_EXP_LNKCTL_CLOCK),
1133 FLAG(w, PCI_EXP_LNKCTL_XSYNCH));
1134 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
1135 printf("\t\tLink: Speed %s, Width x%d\n",
1136 link_speed(w & PCI_EXP_LNKSTA_SPEED), (w & PCI_EXP_LNKSTA_WIDTH) >> 4);
1139 static const char *indicator(int code)
1141 static const char *names[] = { "Unknown", "On", "Blink", "Off" };
1145 static void show_express_slot(struct device *d, int where)
1150 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
1151 printf("\t\tSlot: AtnBtn%c PwrCtrl%c MRL%c AtnInd%c PwrInd%c HotPlug%c Surpise%c\n",
1152 FLAG(t, PCI_EXP_SLTCAP_ATNB),
1153 FLAG(t, PCI_EXP_SLTCAP_PWRC),
1154 FLAG(t, PCI_EXP_SLTCAP_MRL),
1155 FLAG(t, PCI_EXP_SLTCAP_ATNI),
1156 FLAG(t, PCI_EXP_SLTCAP_PWRI),
1157 FLAG(t, PCI_EXP_SLTCAP_HPC),
1158 FLAG(t, PCI_EXP_SLTCAP_HPS));
1159 printf("\t\tSlot: Number %d, PowerLimit %f\n", t >> 19,
1160 power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7,
1161 (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15));
1162 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
1163 printf("\t\tSlot: Enabled AtnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c\n",
1164 FLAG(w, PCI_EXP_SLTCTL_ATNB),
1165 FLAG(w, PCI_EXP_SLTCTL_PWRF),
1166 FLAG(w, PCI_EXP_SLTCTL_MRLS),
1167 FLAG(w, PCI_EXP_SLTCTL_PRSD),
1168 FLAG(w, PCI_EXP_SLTCTL_CMDC),
1169 FLAG(w, PCI_EXP_SLTCTL_HPIE));
1170 printf("\t\tSlot: AttnInd %s, PwrInd %s, Power%c\n",
1171 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
1172 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
1173 FLAG(w, w & PCI_EXP_SLTCTL_PWRC));
1176 static void show_express_root(struct device *d, int where)
1178 u16 w = get_conf_word(d, where + PCI_EXP_RTCTL);
1179 printf("\t\tRoot: Correctable%c Non-Fatal%c Fatal%c PME%c\n",
1180 FLAG(w, PCI_EXP_RTCTL_SECEE),
1181 FLAG(w, PCI_EXP_RTCTL_SENFEE),
1182 FLAG(w, PCI_EXP_RTCTL_SEFEE),
1183 FLAG(w, PCI_EXP_RTCTL_PMEIE));
1187 show_express(struct device *d, int where, int cap)
1189 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1196 case PCI_EXP_TYPE_ENDPOINT:
1199 case PCI_EXP_TYPE_LEG_END:
1200 printf("Legacy Endpoint");
1202 case PCI_EXP_TYPE_ROOT_PORT:
1203 slot = cap & PCI_EXP_FLAGS_SLOT;
1204 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1206 case PCI_EXP_TYPE_UPSTREAM:
1207 printf("Upstream Port");
1209 case PCI_EXP_TYPE_DOWNSTREAM:
1210 slot = cap & PCI_EXP_FLAGS_SLOT;
1211 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1213 case PCI_EXP_TYPE_PCI_BRIDGE:
1214 printf("PCI/PCI-X Bridge");
1217 printf("Unknown type");
1219 printf(" IRQ %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1226 if (type == PCI_EXP_TYPE_ROOT_PORT)
1228 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1231 show_express_dev(d, where, type);
1232 show_express_link(d, where, type);
1234 show_express_slot(d, where);
1235 if (type == PCI_EXP_TYPE_ROOT_PORT)
1236 show_express_root(d, where);
1240 show_msix(struct device *d, int where, int cap)
1244 printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
1245 FLAG(cap, PCI_MSIX_ENABLE),
1246 FLAG(cap, PCI_MSIX_MASK),
1247 (cap & PCI_MSIX_TABSIZE) + 1);
1248 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1251 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1252 printf("\t\tVector table: BAR=%d offset=%08x\n",
1253 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1254 off = get_conf_long(d, where + PCI_MSIX_PBA);
1255 printf("\t\tPBA: BAR=%d offset=%08x\n",
1256 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1260 show_slotid(int cap)
1262 int esr = cap & 0xff;
1265 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1266 esr & PCI_SID_ESR_NSLOTS,
1267 FLAG(esr, PCI_SID_ESR_FIC),
1272 show_aer(struct device *d UNUSED, int where UNUSED)
1274 printf("Advanced Error Reporting\n");
1278 show_vc(struct device *d UNUSED, int where UNUSED)
1280 printf("Virtual Channel\n");
1284 show_dsn(struct device *d, int where)
1287 if (!config_fetch(d, where + 4, 8))
1289 t1 = get_conf_long(d, where + 4);
1290 t2 = get_conf_long(d, where + 8);
1291 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
1292 t1 & 0xff, (t1 >> 8) & 0xff, (t1 >> 16) & 0xff, t1 >> 24,
1293 t2 & 0xff, (t2 >> 8) & 0xff, (t2 >> 16) & 0xff, t2 >> 24);
1297 show_pb(struct device *d UNUSED, int where UNUSED)
1299 printf("Power Budgeting\n");
1303 show_ext_caps(struct device *d)
1311 if (!config_fetch(d, where, 4))
1313 header = get_conf_long(d, where);
1316 id = header & 0xffff;
1317 printf("\tCapabilities: [%03x] ", where);
1320 case PCI_EXT_CAP_ID_AER:
1323 case PCI_EXT_CAP_ID_VC:
1326 case PCI_EXT_CAP_ID_DSN:
1329 case PCI_EXT_CAP_ID_PB:
1333 printf("Unknown (%d)\n", id);
1336 where = header >> 20;
1341 show_caps(struct device *d)
1343 int can_have_ext_caps = 0;
1345 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1347 int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
1351 printf("\tCapabilities: ");
1352 if (!config_fetch(d, where, 4))
1354 puts("<access denied>");
1357 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1358 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1359 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1360 printf("[%02x] ", where);
1363 printf("<chain broken>\n");
1369 show_pm(d, where, cap);
1371 case PCI_CAP_ID_AGP:
1372 show_agp(d, where, cap);
1374 case PCI_CAP_ID_VPD:
1375 printf("Vital Product Data\n");
1377 case PCI_CAP_ID_SLOTID:
1380 case PCI_CAP_ID_MSI:
1381 show_msi(d, where, cap);
1383 case PCI_CAP_ID_PCIX:
1384 show_pcix(d, where);
1385 can_have_ext_caps = 1;
1388 show_ht(d, where, cap);
1390 case PCI_CAP_ID_VNDR:
1393 case PCI_CAP_ID_DBG:
1396 case PCI_CAP_ID_EXP:
1397 show_express(d, where, cap);
1398 can_have_ext_caps = 1;
1400 case PCI_CAP_ID_MSIX:
1401 show_msix(d, where, cap);
1404 printf("#%02x [%04x]\n", id, cap);
1409 if (can_have_ext_caps)
1414 show_htype0(struct device *d)
1417 show_rom(d, PCI_ROM_ADDRESS);
1422 show_htype1(struct device *d)
1424 u32 io_base = get_conf_byte(d, PCI_IO_BASE);
1425 u32 io_limit = get_conf_byte(d, PCI_IO_LIMIT);
1426 u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
1427 u32 mem_base = get_conf_word(d, PCI_MEMORY_BASE);
1428 u32 mem_limit = get_conf_word(d, PCI_MEMORY_LIMIT);
1429 u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
1430 u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE);
1431 u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT);
1432 u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
1433 word sec_stat = get_conf_word(d, PCI_SEC_STATUS);
1434 word brc = get_conf_word(d, PCI_BRIDGE_CONTROL);
1435 int verb = verbose > 2;
1438 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1439 get_conf_byte(d, PCI_PRIMARY_BUS),
1440 get_conf_byte(d, PCI_SECONDARY_BUS),
1441 get_conf_byte(d, PCI_SUBORDINATE_BUS),
1442 get_conf_byte(d, PCI_SEC_LATENCY_TIMER));
1444 if (io_type != (io_limit & PCI_IO_RANGE_TYPE_MASK) ||
1445 (io_type != PCI_IO_RANGE_TYPE_16 && io_type != PCI_IO_RANGE_TYPE_32))
1446 printf("\t!!! Unknown I/O range types %x/%x\n", io_base, io_limit);
1449 io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
1450 io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
1451 if (io_type == PCI_IO_RANGE_TYPE_32)
1453 io_base |= (get_conf_word(d, PCI_IO_BASE_UPPER16) << 16);
1454 io_limit |= (get_conf_word(d, PCI_IO_LIMIT_UPPER16) << 16);
1456 if (io_base <= io_limit || verb)
1457 printf("\tI/O behind bridge: %08x-%08x\n", io_base, io_limit+0xfff);
1460 if (mem_type != (mem_limit & PCI_MEMORY_RANGE_TYPE_MASK) ||
1462 printf("\t!!! Unknown memory range types %x/%x\n", mem_base, mem_limit);
1465 mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
1466 mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
1467 if (mem_base <= mem_limit || verb)
1468 printf("\tMemory behind bridge: %08x-%08x\n", mem_base, mem_limit + 0xfffff);
1471 if (pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
1472 (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64))
1473 printf("\t!!! Unknown prefetchable memory range types %x/%x\n", pref_base, pref_limit);
1476 pref_base = (pref_base & PCI_PREF_RANGE_MASK) << 16;
1477 pref_limit = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
1478 if (pref_base <= pref_limit || verb)
1480 if (pref_type == PCI_PREF_RANGE_TYPE_32)
1481 printf("\tPrefetchable memory behind bridge: %08x-%08x\n", pref_base, pref_limit + 0xfffff);
1483 printf("\tPrefetchable memory behind bridge: %08x%08x-%08x%08x\n",
1484 get_conf_long(d, PCI_PREF_BASE_UPPER32),
1486 get_conf_long(d, PCI_PREF_LIMIT_UPPER32),
1492 printf("\tSecondary status: 66MHz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c\n",
1493 FLAG(sec_stat, PCI_STATUS_66MHZ),
1494 FLAG(sec_stat, PCI_STATUS_FAST_BACK),
1495 FLAG(sec_stat, PCI_STATUS_PARITY),
1496 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1497 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1498 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1499 FLAG(sec_stat, PCI_STATUS_SIG_TARGET_ABORT),
1500 FLAG(sec_stat, PCI_STATUS_REC_TARGET_ABORT),
1501 FLAG(sec_stat, PCI_STATUS_REC_MASTER_ABORT),
1502 FLAG(sec_stat, PCI_STATUS_SIG_SYSTEM_ERROR),
1503 FLAG(sec_stat, PCI_STATUS_DETECTED_PARITY));
1505 show_rom(d, PCI_ROM_ADDRESS1);
1508 printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
1509 FLAG(brc, PCI_BRIDGE_CTL_PARITY),
1510 FLAG(brc, PCI_BRIDGE_CTL_SERR),
1511 FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
1512 FLAG(brc, PCI_BRIDGE_CTL_VGA),
1513 FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
1514 FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
1515 FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
1521 show_htype2(struct device *d)
1524 word cmd = get_conf_word(d, PCI_COMMAND);
1525 word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
1527 int verb = verbose > 2;
1530 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1531 get_conf_byte(d, PCI_CB_PRIMARY_BUS),
1532 get_conf_byte(d, PCI_CB_CARD_BUS),
1533 get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
1534 get_conf_byte(d, PCI_CB_LATENCY_TIMER));
1538 u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
1539 u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
1540 if (limit > base || verb)
1541 printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
1542 (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
1543 (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
1548 u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
1549 u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
1550 if (!(base & PCI_IO_RANGE_TYPE_32))
1555 base &= PCI_CB_IO_RANGE_MASK;
1556 limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
1557 if (base <= limit || verb)
1558 printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
1559 (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
1562 if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
1563 printf("\tSecondary status: SERR\n");
1565 printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
1566 FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
1567 FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
1568 FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
1569 FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
1570 FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
1571 FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
1572 FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
1573 FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
1575 if (d->config_cached < 128)
1577 printf("\t<access denied to the rest>\n");
1581 exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
1583 printf("\t16-bit legacy interface ports at %04x\n", exca);
1587 show_verbose(struct device *d)
1589 struct pci_dev *p = d->dev;
1590 word status = get_conf_word(d, PCI_STATUS);
1591 word cmd = get_conf_word(d, PCI_COMMAND);
1592 word class = get_conf_word(d, PCI_CLASS_DEVICE);
1593 byte bist = get_conf_byte(d, PCI_BIST);
1594 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1595 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
1596 byte cache_line = get_conf_byte(d, PCI_CACHE_LINE_SIZE);
1597 byte max_lat, min_gnt;
1598 byte int_pin = get_conf_byte(d, PCI_INTERRUPT_PIN);
1599 unsigned int irq = p->irq;
1600 word subsys_v = 0, subsys_d = 0;
1601 char ssnamebuf[256];
1607 case PCI_HEADER_TYPE_NORMAL:
1608 if (class == PCI_CLASS_BRIDGE_PCI)
1609 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1610 max_lat = get_conf_byte(d, PCI_MAX_LAT);
1611 min_gnt = get_conf_byte(d, PCI_MIN_GNT);
1612 subsys_v = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1613 subsys_d = get_conf_word(d, PCI_SUBSYSTEM_ID);
1615 case PCI_HEADER_TYPE_BRIDGE:
1616 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1617 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1618 irq = int_pin = min_gnt = max_lat = 0;
1620 case PCI_HEADER_TYPE_CARDBUS:
1621 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1622 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1623 min_gnt = max_lat = 0;
1624 if (d->config_cached >= 128)
1626 subsys_v = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1627 subsys_d = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1631 printf("\t!!! Unknown header type %02x\n", htype);
1635 if (subsys_v && subsys_v != 0xffff)
1636 printf("\tSubsystem: %s\n",
1637 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1638 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1639 p->vendor_id, p->device_id, subsys_v, subsys_d));
1643 printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c\n",
1644 FLAG(cmd, PCI_COMMAND_IO),
1645 FLAG(cmd, PCI_COMMAND_MEMORY),
1646 FLAG(cmd, PCI_COMMAND_MASTER),
1647 FLAG(cmd, PCI_COMMAND_SPECIAL),
1648 FLAG(cmd, PCI_COMMAND_INVALIDATE),
1649 FLAG(cmd, PCI_COMMAND_VGA_PALETTE),
1650 FLAG(cmd, PCI_COMMAND_PARITY),
1651 FLAG(cmd, PCI_COMMAND_WAIT),
1652 FLAG(cmd, PCI_COMMAND_SERR),
1653 FLAG(cmd, PCI_COMMAND_FAST_BACK));
1654 printf("\tStatus: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c\n",
1655 FLAG(status, PCI_STATUS_CAP_LIST),
1656 FLAG(status, PCI_STATUS_66MHZ),
1657 FLAG(status, PCI_STATUS_UDF),
1658 FLAG(status, PCI_STATUS_FAST_BACK),
1659 FLAG(status, PCI_STATUS_PARITY),
1660 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1661 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1662 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1663 FLAG(status, PCI_STATUS_SIG_TARGET_ABORT),
1664 FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
1665 FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
1666 FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
1667 FLAG(status, PCI_STATUS_DETECTED_PARITY));
1668 if (cmd & PCI_COMMAND_MASTER)
1670 printf("\tLatency: %d", latency);
1671 if (min_gnt || max_lat)
1675 printf("%dns min", min_gnt*250);
1676 if (min_gnt && max_lat)
1679 printf("%dns max", max_lat*250);
1683 printf(", Cache Line Size: %d bytes", cache_line * 4);
1687 printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n",
1688 (int_pin ? 'A' + int_pin - 1 : '?'), irq);
1692 printf("\tFlags: ");
1693 if (cmd & PCI_COMMAND_MASTER)
1694 printf("bus master, ");
1695 if (cmd & PCI_COMMAND_VGA_PALETTE)
1696 printf("VGA palette snoop, ");
1697 if (cmd & PCI_COMMAND_WAIT)
1698 printf("stepping, ");
1699 if (cmd & PCI_COMMAND_FAST_BACK)
1700 printf("fast Back2Back, ");
1701 if (status & PCI_STATUS_66MHZ)
1703 if (status & PCI_STATUS_UDF)
1704 printf("user-definable features, ");
1706 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1707 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1708 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??");
1709 if (cmd & PCI_COMMAND_MASTER)
1710 printf(", latency %d", latency);
1712 printf(", IRQ " PCIIRQ_FMT, irq);
1716 if (bist & PCI_BIST_CAPABLE)
1718 if (bist & PCI_BIST_START)
1719 printf("\tBIST is running\n");
1721 printf("\tBIST result: %02x\n", bist & PCI_BIST_CODE_MASK);
1726 case PCI_HEADER_TYPE_NORMAL:
1729 case PCI_HEADER_TYPE_BRIDGE:
1732 case PCI_HEADER_TYPE_CARDBUS:
1739 show_hex_dump(struct device *d)
1741 unsigned int i, cnt;
1743 cnt = d->config_cached;
1744 if (show_hex >= 3 && config_fetch(d, cnt, 256-cnt))
1747 if (show_hex >= 4 && config_fetch(d, 256, 4096-256))
1751 for(i=0; i<cnt; i++)
1755 printf(" %02x", get_conf_byte(d, i));
1762 show_machine(struct device *d)
1764 struct pci_dev *p = d->dev;
1766 word sv_id=0, sd_id=0;
1767 char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
1769 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
1771 case PCI_HEADER_TYPE_NORMAL:
1772 sv_id = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1773 sd_id = get_conf_word(d, PCI_SUBSYSTEM_ID);
1775 case PCI_HEADER_TYPE_CARDBUS:
1776 if (d->config_cached >= 128)
1778 sv_id = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1779 sd_id = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1786 printf("Device:\t");
1789 printf("Class:\t%s\n",
1790 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, get_conf_word(d, PCI_CLASS_DEVICE)));
1791 printf("Vendor:\t%s\n",
1792 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
1793 printf("Device:\t%s\n",
1794 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
1795 if (sv_id && sv_id != 0xffff)
1797 printf("SVendor:\t%s\n",
1798 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
1799 printf("SDevice:\t%s\n",
1800 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1802 if (c = get_conf_byte(d, PCI_REVISION_ID))
1803 printf("Rev:\t%02x\n", c);
1804 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1805 printf("ProgIf:\t%02x\n", c);
1810 printf(" \"%s\" \"%s\" \"%s\"",
1811 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS,
1812 get_conf_word(d, PCI_CLASS_DEVICE)),
1813 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR,
1814 p->vendor_id, p->device_id),
1815 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE,
1816 p->vendor_id, p->device_id));
1817 if (c = get_conf_byte(d, PCI_REVISION_ID))
1818 printf(" -r%02x", c);
1819 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1820 printf(" -p%02x", c);
1821 if (sv_id && sv_id != 0xffff)
1822 printf(" \"%s\" \"%s\"",
1823 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id),
1824 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1826 printf(" \"\" \"\"");
1832 show_device(struct device *d)
1834 if (machine_readable)
1842 if (verbose || show_hex)
1851 for(d=first_dev; d; d=d->next)
1858 struct bridge *chain; /* Single-linked list of bridges */
1859 struct bridge *next, *child; /* Tree of bridges */
1860 struct bus *first_bus; /* List of buses connected to this bridge */
1861 unsigned int domain;
1862 unsigned int primary, secondary, subordinate; /* Bus numbers */
1863 struct device *br_dev;
1867 unsigned int domain;
1868 unsigned int number;
1869 struct bus *sibling;
1870 struct device *first_dev, **last_dev;
1873 static struct bridge host_bridge = { NULL, NULL, NULL, NULL, 0, ~0, 0, ~0, NULL };
1876 find_bus(struct bridge *b, unsigned int domain, unsigned int n)
1880 for(bus=b->first_bus; bus; bus=bus->sibling)
1881 if (bus->domain == domain && bus->number == n)
1887 new_bus(struct bridge *b, unsigned int domain, unsigned int n)
1889 struct bus *bus = xmalloc(sizeof(struct bus));
1890 bus->domain = domain;
1892 bus->sibling = b->first_bus;
1893 bus->first_dev = NULL;
1894 bus->last_dev = &bus->first_dev;
1900 insert_dev(struct device *d, struct bridge *b)
1902 struct pci_dev *p = d->dev;
1905 if (! (bus = find_bus(b, p->domain, p->bus)))
1908 for(c=b->child; c; c=c->next)
1909 if (c->domain == p->domain && c->secondary <= p->bus && p->bus <= c->subordinate)
1914 bus = new_bus(b, p->domain, p->bus);
1916 /* Simple insertion at the end _does_ guarantee the correct order as the
1917 * original device list was sorted by (domain, bus, devfn) lexicographically
1918 * and all devices on the new list have the same bus number.
1921 bus->last_dev = &d->next;
1928 struct device *d, *d2;
1929 struct bridge **last_br, *b;
1931 /* Build list of bridges */
1933 last_br = &host_bridge.chain;
1934 for(d=first_dev; d; d=d->next)
1936 word class = get_conf_word(d, PCI_CLASS_DEVICE);
1937 byte ht = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1938 if (class == PCI_CLASS_BRIDGE_PCI &&
1939 (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS))
1941 b = xmalloc(sizeof(struct bridge));
1942 b->domain = d->dev->domain;
1943 if (ht == PCI_HEADER_TYPE_BRIDGE)
1945 b->primary = get_conf_byte(d, PCI_CB_PRIMARY_BUS);
1946 b->secondary = get_conf_byte(d, PCI_CB_CARD_BUS);
1947 b->subordinate = get_conf_byte(d, PCI_CB_SUBORDINATE_BUS);
1951 b->primary = get_conf_byte(d, PCI_PRIMARY_BUS);
1952 b->secondary = get_conf_byte(d, PCI_SECONDARY_BUS);
1953 b->subordinate = get_conf_byte(d, PCI_SUBORDINATE_BUS);
1956 last_br = &b->chain;
1957 b->next = b->child = NULL;
1958 b->first_bus = NULL;
1964 /* Create a bridge tree */
1966 for(b=&host_bridge; b; b=b->chain)
1968 struct bridge *c, *best;
1970 for(c=&host_bridge; c; c=c->chain)
1971 if (c != b && (c == &host_bridge || b->domain == c->domain) &&
1972 b->primary >= c->secondary && b->primary <= c->subordinate &&
1973 (!best || best->subordinate - best->primary > c->subordinate - c->primary))
1977 b->next = best->child;
1982 /* Insert secondary bus for each bridge */
1984 for(b=&host_bridge; b; b=b->chain)
1985 if (!find_bus(b, b->domain, b->secondary))
1986 new_bus(b, b->domain, b->secondary);
1988 /* Create bus structs and link devices */
1990 for(d=first_dev; d;)
1993 insert_dev(d, &host_bridge);
1999 print_it(byte *line, byte *p)
2003 fputs(line, stdout);
2004 for(p=line; *p; p++)
2005 if (*p == '+' || *p == '|')
2011 static void show_tree_bridge(struct bridge *, byte *, byte *);
2014 show_tree_dev(struct device *d, byte *line, byte *p)
2016 struct pci_dev *q = d->dev;
2020 p += sprintf(p, "%02x.%x", q->dev, q->func);
2021 for(b=&host_bridge; b; b=b->chain)
2024 if (b->secondary == b->subordinate)
2025 p += sprintf(p, "-[%04x:%02x]-", b->domain, b->secondary);
2027 p += sprintf(p, "-[%04x:%02x-%02x]-", b->domain, b->secondary, b->subordinate);
2028 show_tree_bridge(b, line, p);
2032 p += sprintf(p, " %s",
2033 pci_lookup_name(pacc, namebuf, sizeof(namebuf),
2034 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
2035 q->vendor_id, q->device_id));
2040 show_tree_bus(struct bus *b, byte *line, byte *p)
2044 else if (!b->first_dev->next)
2048 show_tree_dev(b->first_dev, line, p);
2052 struct device *d = b->first_dev;
2057 show_tree_dev(d, line, p+2);
2062 show_tree_dev(d, line, p+2);
2067 show_tree_bridge(struct bridge *b, byte *line, byte *p)
2070 if (!b->first_bus->sibling)
2072 if (b == &host_bridge)
2073 p += sprintf(p, "[%04x:%02x]-", b->domain, b->first_bus->number);
2074 show_tree_bus(b->first_bus, line, p);
2078 struct bus *u = b->first_bus;
2083 k = p + sprintf(p, "+-[%04x:%02x]-", u->domain, u->number);
2084 show_tree_bus(u, line, k);
2087 k = p + sprintf(p, "\\-[%04x:%02x]-", u->domain, u->number);
2088 show_tree_bus(u, line, k);
2098 show_tree_bridge(&host_bridge, line, line);
2101 /* Bus mapping mode */
2104 struct bus_bridge *next;
2105 byte this, dev, func, first, last, bug;
2111 struct bus_bridge *bridges, *via;
2114 static struct bus_info *bus_info;
2117 map_bridge(struct bus_info *bi, struct device *d, int np, int ns, int nl)
2119 struct bus_bridge *b = xmalloc(sizeof(struct bus_bridge));
2120 struct pci_dev *p = d->dev;
2122 b->next = bi->bridges;
2124 b->this = get_conf_byte(d, np);
2127 b->first = get_conf_byte(d, ns);
2128 b->last = get_conf_byte(d, nl);
2129 printf("## %02x.%02x:%d is a bridge from %02x to %02x-%02x\n",
2130 p->bus, p->dev, p->func, b->this, b->first, b->last);
2131 if (b->this != p->bus)
2132 printf("!!! Bridge points to invalid primary bus.\n");
2133 if (b->first > b->last)
2135 printf("!!! Bridge points to invalid bus range.\n");
2144 int verbose = pacc->debugging;
2145 struct bus_info *bi = bus_info + bus;
2149 printf("Mapping bus %02x\n", bus);
2150 for(dev = 0; dev < 32; dev++)
2151 if (filter.slot < 0 || filter.slot == dev)
2154 for(func = 0; func < func_limit; func++)
2155 if (filter.func < 0 || filter.func == func)
2157 /* XXX: Bus mapping supports only domain 0 */
2158 struct pci_dev *p = pci_get_dev(pacc, 0, bus, dev, func);
2159 u16 vendor = pci_read_word(p, PCI_VENDOR_ID);
2160 if (vendor && vendor != 0xffff)
2162 if (!func && (pci_read_byte(p, PCI_HEADER_TYPE) & 0x80))
2165 printf("Discovered device %02x:%02x.%d\n", bus, dev, func);
2167 if (d = scan_device(p))
2170 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
2172 case PCI_HEADER_TYPE_BRIDGE:
2173 map_bridge(bi, d, PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS);
2175 case PCI_HEADER_TYPE_CARDBUS:
2176 map_bridge(bi, d, PCI_CB_PRIMARY_BUS, PCI_CB_CARD_BUS, PCI_CB_SUBORDINATE_BUS);
2182 printf("But it was filtered out.\n");
2190 do_map_bridges(int bus, int min, int max)
2192 struct bus_info *bi = bus_info + bus;
2193 struct bus_bridge *b;
2196 for(b=bi->bridges; b; b=b->next)
2198 if (bus_info[b->first].guestbook)
2200 else if (b->first < min || b->last > max)
2204 bus_info[b->first].via = b;
2205 do_map_bridges(b->first, b->first, b->last);
2215 printf("\nSummary of buses:\n\n");
2216 for(i=0; i<256; i++)
2217 if (bus_info[i].exists && !bus_info[i].guestbook)
2218 do_map_bridges(i, 0, 255);
2219 for(i=0; i<256; i++)
2221 struct bus_info *bi = bus_info + i;
2222 struct bus_bridge *b = bi->via;
2226 printf("%02x: ", i);
2228 printf("Entered via %02x:%02x.%d\n", b->this, b->dev, b->func);
2230 printf("Primary host bus\n");
2232 printf("Secondary host bus (?)\n");
2234 for(b=bi->bridges; b; b=b->next)
2236 printf("\t%02x.%d Bridge to %02x-%02x", b->dev, b->func, b->first, b->last);
2240 printf(" <overlap bug>");
2243 printf(" <crossing bug>");
2254 if (pacc->method == PCI_ACCESS_PROC_BUS_PCI ||
2255 pacc->method == PCI_ACCESS_DUMP)
2256 printf("WARNING: Bus mapping can be reliable only with direct hardware access enabled.\n\n");
2257 bus_info = xmalloc(sizeof(struct bus_info) * 256);
2258 bzero(bus_info, sizeof(struct bus_info) * 256);
2259 if (filter.bus >= 0)
2260 do_map_bus(filter.bus);
2264 for(bus=0; bus<256; bus++)
2273 main(int argc, char **argv)
2278 if (argc == 2 && !strcmp(argv[1], "--version"))
2280 puts("lspci version " PCIUTILS_VERSION);
2286 pci_filter_init(pacc, &filter);
2288 while ((i = getopt(argc, argv, options)) != -1)
2292 pacc->numeric_ids = 1;
2298 pacc->buscentric = 1;
2299 buscentric_view = 1;
2302 if (msg = pci_filter_parse_slot(&filter, optarg))
2306 if (msg = pci_filter_parse_id(&filter, optarg))
2316 pacc->id_file_name = optarg;
2328 if (parse_generic_option(i, pacc, optarg))
2331 fprintf(stderr, help_msg, pacc->id_file_name);