2 * The PCI Utilities -- List All PCI Devices
4 * Copyright (c) 1997--2005 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
19 static int verbose; /* Show detailed information */
20 static int buscentric_view; /* Show bus addresses/IRQ's instead of CPU-visible ones */
21 static int show_hex; /* Show contents of config space as hexadecimal numbers */
22 static struct pci_filter filter; /* Device filter */
23 static int show_tree; /* Show bus tree */
24 static int machine_readable; /* Generate machine-readable output */
25 static int map_mode; /* Bus mapping mode enabled */
27 static char options[] = "nvbxs:d:ti:mgM" GENERIC_OPTIONS ;
29 static char help_msg[] = "\
30 Usage: lspci [<switches>]\n\
33 -n\t\tShow numeric ID's\n\
34 -b\t\tBus-centric view (PCI addresses and IRQ's instead of those seen by the CPU)\n\
35 -x\t\tShow hex-dump of the standard portion of config space\n\
36 -xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n\
37 -xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n\
38 -s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n\
39 -d [<vendor>]:[<device>]\tShow only selected devices\n\
40 -t\t\tShow bus tree\n\
41 -m\t\tProduce machine-readable output\n\
42 -i <file>\tUse specified ID database instead of %s\n\
43 -M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
47 /* Communication with libpci */
49 static struct pci_access *pacc;
52 * If we aren't being compiled by GCC, use xmalloc() instead of alloca().
53 * This increases our memory footprint, but only slightly since we don't
59 #define alloca xmalloc
62 /* Our view of the PCI bus */
67 unsigned int config_cnt, config_bufsize;
71 static struct device *first_dev;
74 config_fetch(struct device *d, unsigned int pos, unsigned int len)
76 unsigned int end = pos+len;
78 if (end <= d->config_cnt)
80 if (end > d->config_bufsize)
82 while (end > d->config_bufsize)
83 d->config_bufsize *= 2;
84 d->config = xrealloc(d->config, d->config_bufsize);
86 result = pci_read_block(d->dev, pos, d->config + pos, len);
87 if (result && pos == d->config_cnt)
92 static struct device *
93 scan_device(struct pci_dev *p)
97 if (!pci_filter_match(&filter, p))
99 d = xmalloc(sizeof(struct device));
100 bzero(d, sizeof(*d));
102 d->config_cnt = d->config_bufsize = 64;
103 d->config = xmalloc(64);
104 if (!pci_read_block(p, 0, d->config, 64))
105 die("Unable to read the configuration space header.");
106 if ((d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
108 /* For cardbus bridges, we need to fetch 64 bytes more to get the
109 * full standard header... */
110 if (!config_fetch(d, 64, 64))
111 die("Unable to read cardbus bridge extension data.");
113 pci_setup_cache(p, d->config, d->config_cnt);
114 pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
125 for(p=pacc->devices; p; p=p->next)
126 if (d = scan_device(p))
133 /* Config space accesses */
136 get_conf_byte(struct device *d, unsigned int pos)
138 return d->config[pos];
142 get_conf_word(struct device *d, unsigned int pos)
144 return d->config[pos] | (d->config[pos+1] << 8);
148 get_conf_long(struct device *d, unsigned int pos)
150 return d->config[pos] |
151 (d->config[pos+1] << 8) |
152 (d->config[pos+2] << 16) |
153 (d->config[pos+3] << 24);
159 compare_them(const void *A, const void *B)
161 const struct pci_dev *a = (*(const struct device **)A)->dev;
162 const struct pci_dev *b = (*(const struct device **)B)->dev;
164 if (a->domain < b->domain)
166 if (a->domain > b->domain)
176 if (a->func < b->func)
178 if (a->func > b->func)
186 struct device **index, **h, **last_dev;
191 for(d=first_dev; d; d=d->next)
193 h = index = alloca(sizeof(struct device *) * cnt);
194 for(d=first_dev; d; d=d->next)
196 qsort(index, cnt, sizeof(struct device *), compare_them);
197 last_dev = &first_dev;
202 last_dev = &(*h)->next;
210 #define FLAG(x,y) ((x & y) ? '+' : '-')
213 show_slot_name(struct device *d)
215 struct pci_dev *p = d->dev;
218 printf("%04x:", p->domain);
219 printf("%02x:%02x.%d", p->bus, p->dev, p->func);
223 show_terse(struct device *d)
226 struct pci_dev *p = d->dev;
227 byte classbuf[128], devbuf[128];
231 pci_lookup_name(pacc, classbuf, sizeof(classbuf),
233 get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0),
234 pci_lookup_name(pacc, devbuf, sizeof(devbuf),
235 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
236 p->vendor_id, p->device_id, 0, 0));
237 if (c = get_conf_byte(d, PCI_REVISION_ID))
238 printf(" (rev %02x)", c);
242 c = get_conf_byte(d, PCI_CLASS_PROG);
243 x = pci_lookup_name(pacc, devbuf, sizeof(devbuf),
245 get_conf_word(d, PCI_CLASS_DEVICE), c, 0, 0);
248 printf(" (prog-if %02x", c);
258 show_size(pciaddr_t x)
264 printf("%d", (int) x);
265 else if (x < 1048576)
266 printf("%dK", (int)(x / 1024));
267 else if (x < 0x80000000)
268 printf("%dM", (int)(x / 1048576));
270 printf(PCIADDR_T_FMT, x);
275 show_bases(struct device *d, int cnt)
277 struct pci_dev *p = d->dev;
278 word cmd = get_conf_word(d, PCI_COMMAND);
283 pciaddr_t pos = p->base_addr[i];
284 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
285 u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
286 if (flg == 0xffffffff)
288 if (!pos && !flg && !len)
291 printf("\tRegion %d: ", i);
294 if (pos && !flg) /* Reported by the OS, but not by the device */
296 printf("[virtual] ");
299 if (flg & PCI_BASE_ADDRESS_SPACE_IO)
301 pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
302 printf("I/O ports at ");
304 printf(PCIADDR_PORT_FMT, a);
305 else if (flg & PCI_BASE_ADDRESS_IO_MASK)
308 printf("<unassigned>");
309 if (!(cmd & PCI_COMMAND_IO))
310 printf(" [disabled]");
314 int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
315 pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
319 printf("Memory at ");
320 if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
324 printf("<invalid-64bit-slot>");
330 z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
334 printf("%08x" PCIADDR_T_FMT, z, a);
336 printf("<unassigned>");
344 printf(PCIADDR_T_FMT, a);
346 printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
348 printf(" (%s, %sprefetchable)",
349 (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
350 (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
351 (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
352 (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
353 if (!(cmd & PCI_COMMAND_MEMORY))
354 printf(" [disabled]");
362 show_pm(struct device *d, int where, int cap)
365 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
367 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
370 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
371 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
372 FLAG(cap, PCI_PM_CAP_DSI),
373 FLAG(cap, PCI_PM_CAP_D1),
374 FLAG(cap, PCI_PM_CAP_D2),
375 pm_aux_current[(cap >> 6) & 7],
376 FLAG(cap, PCI_PM_CAP_PME_D0),
377 FLAG(cap, PCI_PM_CAP_PME_D1),
378 FLAG(cap, PCI_PM_CAP_PME_D2),
379 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
380 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
381 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
383 t = get_conf_word(d, where + PCI_PM_CTRL);
384 printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
385 t & PCI_PM_CTRL_STATE_MASK,
386 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
387 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
388 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
389 FLAG(t, PCI_PM_CTRL_PME_STATUS));
390 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
392 printf("\t\tBridge: PM%c B3%c\n",
393 FLAG(t, PCI_PM_BPCC_ENABLE),
394 FLAG(~t, PCI_PM_PPB_B2_B3));
398 format_agp_rate(int rate, char *buf, int agp3)
408 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
413 strcpy(buf, "<none>");
417 show_agp(struct device *d, int where, int cap)
424 ver = (cap >> 4) & 0x0f;
426 printf("AGP version %x.%x\n", ver, rev);
429 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
431 t = get_conf_long(d, where + PCI_AGP_STATUS);
432 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
434 format_agp_rate(t & 7, rate, agp3);
435 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
436 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
437 FLAG(t, PCI_AGP_STATUS_ISOCH),
438 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
439 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
440 FLAG(t, PCI_AGP_STATUS_SBA),
441 FLAG(t, PCI_AGP_STATUS_ITA_COH),
442 FLAG(t, PCI_AGP_STATUS_GART64),
443 FLAG(t, PCI_AGP_STATUS_HTRANS),
444 FLAG(t, PCI_AGP_STATUS_64BIT),
445 FLAG(t, PCI_AGP_STATUS_FW),
446 FLAG(t, PCI_AGP_STATUS_AGP3),
448 t = get_conf_long(d, where + PCI_AGP_COMMAND);
449 format_agp_rate(t & 7, rate, agp3);
450 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
451 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
452 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
453 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
454 FLAG(t, PCI_AGP_COMMAND_SBA),
455 FLAG(t, PCI_AGP_COMMAND_AGP),
456 FLAG(t, PCI_AGP_COMMAND_GART64),
457 FLAG(t, PCI_AGP_COMMAND_64BIT),
458 FLAG(t, PCI_AGP_COMMAND_FW),
463 show_pcix_nobridge(struct device *d, int where)
467 static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
469 printf("PCI-X non-bridge device\n");
474 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
477 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
478 status = get_conf_long(d, where + PCI_PCIX_STATUS);
479 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
480 FLAG(command, PCI_PCIX_COMMAND_DPERE),
481 FLAG(command, PCI_PCIX_COMMAND_ERO),
482 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
483 max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
484 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
485 ((status >> 8) & 0xff), // bus
486 ((status >> 3) & 0x1f), // device
487 (status & PCI_PCIX_STATUS_FUNCTION), // function
488 FLAG(status, PCI_PCIX_STATUS_64BIT),
489 FLAG(status, PCI_PCIX_STATUS_133MHZ),
490 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
491 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
492 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
493 1 << (9 + ((status >> 21) & 3U)),
494 max_outstanding[(status >> 23) & 7U],
495 1 << (3 + ((status >> 26) & 7U)),
496 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
497 FLAG(status, PCI_PCIX_STATUS_266MHZ),
498 FLAG(status, PCI_PCIX_STATUS_533MHZ));
502 show_pcix_bridge(struct device *d, int where)
504 static const byte * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
506 u32 status, upstcr, downstcr;
508 printf("PCI-X bridge device\n");
513 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
516 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
517 printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
518 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
519 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
520 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
521 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
522 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
523 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
524 sec_clock_freq[(secstatus >> 6) & 7]);
525 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
526 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
527 ((status >> 8) & 0xff), // bus
528 ((status >> 3) & 0x1f), // device
529 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION), // function
530 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
531 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
532 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
533 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
534 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
535 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
536 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
537 printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
538 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
539 (upstcr >> 16) & 0xffff);
540 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
541 printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
542 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
543 (downstcr >> 16) & 0xffff);
547 show_pcix(struct device *d, int where)
549 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
551 case PCI_HEADER_TYPE_NORMAL:
552 show_pcix_nobridge(d, where);
554 case PCI_HEADER_TYPE_BRIDGE:
555 show_pcix_bridge(d, where);
561 ht_link_width(unsigned width)
563 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
564 return widths[width];
568 ht_link_freq(unsigned freq)
570 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
571 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
576 show_ht_pri(struct device *d, int where, int cmd)
578 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
579 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
582 printf("HyperTransport: Slave or Primary Interface\n");
586 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
588 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
589 if (rid < 0x23 && rid > 0x11)
590 printf("\t\t!!! Possibly incomplete decoding\n");
593 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
595 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
597 (cmd & PCI_HT_PRI_CMD_BUID),
598 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
599 FLAG(cmd, PCI_HT_PRI_CMD_MH),
600 FLAG(cmd, PCI_HT_PRI_CMD_DD),
601 FLAG(cmd, PCI_HT_PRI_CMD_DUL));
602 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
604 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
606 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
608 FLAG(lctr0, PCI_HT_LCTR_CFLE),
609 FLAG(lctr0, PCI_HT_LCTR_CST),
610 FLAG(lctr0, PCI_HT_LCTR_CFE),
611 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
612 FLAG(lctr0, PCI_HT_LCTR_INIT),
613 FLAG(lctr0, PCI_HT_LCTR_EOC),
614 FLAG(lctr0, PCI_HT_LCTR_TXO),
615 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
616 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
617 FLAG(lctr0, PCI_HT_LCTR_LSEN),
618 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
619 FLAG(lctr0, PCI_HT_LCTR_64B));
620 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
622 fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
624 fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
626 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
627 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
628 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
629 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
630 FLAG(lcnf0, PCI_HT_LCNF_DFI),
631 FLAG(lcnf0, PCI_HT_LCNF_DFO),
632 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
633 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
634 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
636 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
638 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
640 FLAG(lctr1, PCI_HT_LCTR_CFLE),
641 FLAG(lctr1, PCI_HT_LCTR_CST),
642 FLAG(lctr1, PCI_HT_LCTR_CFE),
643 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
644 FLAG(lctr1, PCI_HT_LCTR_INIT),
645 FLAG(lctr1, PCI_HT_LCTR_EOC),
646 FLAG(lctr1, PCI_HT_LCTR_TXO),
647 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
648 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
649 FLAG(lctr1, PCI_HT_LCTR_LSEN),
650 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
651 FLAG(lctr1, PCI_HT_LCTR_64B));
652 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
654 fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
656 fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
658 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
659 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
660 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
661 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
662 FLAG(lcnf1, PCI_HT_LCNF_DFI),
663 FLAG(lcnf1, PCI_HT_LCNF_DFO),
664 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
665 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
666 printf("\t\tRevision ID: %u.%02u\n",
667 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
670 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
671 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
672 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
673 FLAG(lfrer0, PCI_HT_LFRER_PROT),
674 FLAG(lfrer0, PCI_HT_LFRER_OV),
675 FLAG(lfrer0, PCI_HT_LFRER_EOC),
676 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
677 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
678 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
679 FLAG(lfcap0, PCI_HT_LFCAP_200),
680 FLAG(lfcap0, PCI_HT_LFCAP_300),
681 FLAG(lfcap0, PCI_HT_LFCAP_400),
682 FLAG(lfcap0, PCI_HT_LFCAP_500),
683 FLAG(lfcap0, PCI_HT_LFCAP_600),
684 FLAG(lfcap0, PCI_HT_LFCAP_800),
685 FLAG(lfcap0, PCI_HT_LFCAP_1000),
686 FLAG(lfcap0, PCI_HT_LFCAP_1200),
687 FLAG(lfcap0, PCI_HT_LFCAP_1400),
688 FLAG(lfcap0, PCI_HT_LFCAP_1600),
689 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
690 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
691 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
692 FLAG(ftr, PCI_HT_FTR_ISOCFC),
693 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
694 FLAG(ftr, PCI_HT_FTR_CRCTM),
695 FLAG(ftr, PCI_HT_FTR_ECTLT),
696 FLAG(ftr, PCI_HT_FTR_64BA),
697 FLAG(ftr, PCI_HT_FTR_UIDRD));
698 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
699 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
700 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
701 FLAG(lfrer1, PCI_HT_LFRER_PROT),
702 FLAG(lfrer1, PCI_HT_LFRER_OV),
703 FLAG(lfrer1, PCI_HT_LFRER_EOC),
704 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
705 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
706 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
707 FLAG(lfcap1, PCI_HT_LFCAP_200),
708 FLAG(lfcap1, PCI_HT_LFCAP_300),
709 FLAG(lfcap1, PCI_HT_LFCAP_400),
710 FLAG(lfcap1, PCI_HT_LFCAP_500),
711 FLAG(lfcap1, PCI_HT_LFCAP_600),
712 FLAG(lfcap1, PCI_HT_LFCAP_800),
713 FLAG(lfcap1, PCI_HT_LFCAP_1000),
714 FLAG(lfcap1, PCI_HT_LFCAP_1200),
715 FLAG(lfcap1, PCI_HT_LFCAP_1400),
716 FLAG(lfcap1, PCI_HT_LFCAP_1600),
717 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
718 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
719 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
720 FLAG(eh, PCI_HT_EH_PFLE),
721 FLAG(eh, PCI_HT_EH_OFLE),
722 FLAG(eh, PCI_HT_EH_PFE),
723 FLAG(eh, PCI_HT_EH_OFE),
724 FLAG(eh, PCI_HT_EH_EOCFE),
725 FLAG(eh, PCI_HT_EH_RFE),
726 FLAG(eh, PCI_HT_EH_CRCFE),
727 FLAG(eh, PCI_HT_EH_SERRFE),
728 FLAG(eh, PCI_HT_EH_CF),
729 FLAG(eh, PCI_HT_EH_RE),
730 FLAG(eh, PCI_HT_EH_PNFE),
731 FLAG(eh, PCI_HT_EH_ONFE),
732 FLAG(eh, PCI_HT_EH_EOCNFE),
733 FLAG(eh, PCI_HT_EH_RNFE),
734 FLAG(eh, PCI_HT_EH_CRCNFE),
735 FLAG(eh, PCI_HT_EH_SERRNFE));
736 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
737 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
738 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
739 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
740 printf("\t\tBus Number: %02x\n", bn);
744 show_ht_sec(struct device *d, int where, int cmd)
746 u16 lctr, lcnf, ftr, eh;
747 u8 rid, lfrer, lfcap, mbu, mlu;
750 printf("HyperTransport: Host or Secondary Interface\n");
754 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
756 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
757 if (rid < 0x23 && rid > 0x11)
758 printf("\t\t!!! Possibly incomplete decoding\n");
761 fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
763 fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
765 FLAG(cmd, PCI_HT_SEC_CMD_WR),
766 FLAG(cmd, PCI_HT_SEC_CMD_DE),
767 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
768 FLAG(cmd, PCI_HT_SEC_CMD_CS),
769 FLAG(cmd, PCI_HT_SEC_CMD_HH),
770 FLAG(cmd, PCI_HT_SEC_CMD_AS),
771 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
772 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
773 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
775 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
777 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
779 FLAG(lctr, PCI_HT_LCTR_CFLE),
780 FLAG(lctr, PCI_HT_LCTR_CST),
781 FLAG(lctr, PCI_HT_LCTR_CFE),
782 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
783 FLAG(lctr, PCI_HT_LCTR_INIT),
784 FLAG(lctr, PCI_HT_LCTR_EOC),
785 FLAG(lctr, PCI_HT_LCTR_TXO),
786 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
787 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
788 FLAG(lctr, PCI_HT_LCTR_LSEN),
789 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
790 FLAG(lctr, PCI_HT_LCTR_64B));
791 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
793 fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
795 fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
797 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
798 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
799 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
800 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
801 FLAG(lcnf, PCI_HT_LCNF_DFI),
802 FLAG(lcnf, PCI_HT_LCNF_DFO),
803 FLAG(lcnf, PCI_HT_LCNF_DFIE),
804 FLAG(lcnf, PCI_HT_LCNF_DFOE));
805 printf("\t\tRevision ID: %u.%02u\n",
806 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
809 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
810 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
811 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
812 FLAG(lfrer, PCI_HT_LFRER_PROT),
813 FLAG(lfrer, PCI_HT_LFRER_OV),
814 FLAG(lfrer, PCI_HT_LFRER_EOC),
815 FLAG(lfrer, PCI_HT_LFRER_CTLT));
816 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
817 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
818 FLAG(lfcap, PCI_HT_LFCAP_200),
819 FLAG(lfcap, PCI_HT_LFCAP_300),
820 FLAG(lfcap, PCI_HT_LFCAP_400),
821 FLAG(lfcap, PCI_HT_LFCAP_500),
822 FLAG(lfcap, PCI_HT_LFCAP_600),
823 FLAG(lfcap, PCI_HT_LFCAP_800),
824 FLAG(lfcap, PCI_HT_LFCAP_1000),
825 FLAG(lfcap, PCI_HT_LFCAP_1200),
826 FLAG(lfcap, PCI_HT_LFCAP_1400),
827 FLAG(lfcap, PCI_HT_LFCAP_1600),
828 FLAG(lfcap, PCI_HT_LFCAP_VEND));
829 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
830 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
831 FLAG(ftr, PCI_HT_FTR_ISOCFC),
832 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
833 FLAG(ftr, PCI_HT_FTR_CRCTM),
834 FLAG(ftr, PCI_HT_FTR_ECTLT),
835 FLAG(ftr, PCI_HT_FTR_64BA),
836 FLAG(ftr, PCI_HT_FTR_UIDRD),
837 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
838 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
839 if (ftr & PCI_HT_SEC_FTR_EXTRS)
841 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
842 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
843 FLAG(eh, PCI_HT_EH_PFLE),
844 FLAG(eh, PCI_HT_EH_OFLE),
845 FLAG(eh, PCI_HT_EH_PFE),
846 FLAG(eh, PCI_HT_EH_OFE),
847 FLAG(eh, PCI_HT_EH_EOCFE),
848 FLAG(eh, PCI_HT_EH_RFE),
849 FLAG(eh, PCI_HT_EH_CRCFE),
850 FLAG(eh, PCI_HT_EH_SERRFE),
851 FLAG(eh, PCI_HT_EH_CF),
852 FLAG(eh, PCI_HT_EH_RE),
853 FLAG(eh, PCI_HT_EH_PNFE),
854 FLAG(eh, PCI_HT_EH_ONFE),
855 FLAG(eh, PCI_HT_EH_EOCNFE),
856 FLAG(eh, PCI_HT_EH_RNFE),
857 FLAG(eh, PCI_HT_EH_CRCNFE),
858 FLAG(eh, PCI_HT_EH_SERRNFE));
859 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
860 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
861 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
866 show_ht(struct device *d, int where, int cmd)
870 switch (cmd & PCI_HT_CMD_TYP_HI)
872 case PCI_HT_CMD_TYP_HI_PRI:
873 show_ht_pri(d, where, cmd);
875 case PCI_HT_CMD_TYP_HI_SEC:
876 show_ht_sec(d, where, cmd);
880 type = cmd & PCI_HT_CMD_TYP;
883 case PCI_HT_CMD_TYP_SW:
884 printf("HyperTransport: Switch\n");
886 case PCI_HT_CMD_TYP_IDC:
887 printf("HyperTransport: Interrupt Discovery and Configuration\n");
889 case PCI_HT_CMD_TYP_RID:
890 printf("HyperTransport: Revision ID: %u.%02u\n",
891 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
893 case PCI_HT_CMD_TYP_UIDC:
894 printf("HyperTransport: UnitID Clumping\n");
896 case PCI_HT_CMD_TYP_ECSA:
897 printf("HyperTransport: Extended Configuration Space Access\n");
899 case PCI_HT_CMD_TYP_AM:
900 printf("HyperTransport: Address Mapping\n");
902 case PCI_HT_CMD_TYP_MSIM:
903 printf("HyperTransport: MSI Mapping\n");
905 case PCI_HT_CMD_TYP_DR:
906 printf("HyperTransport: DirectRoute\n");
908 case PCI_HT_CMD_TYP_VCS:
909 printf("HyperTransport: VCSet\n");
911 case PCI_HT_CMD_TYP_RM:
912 printf("HyperTransport: Retry Mode\n");
914 case PCI_HT_CMD_TYP_X86:
915 printf("HyperTransport: X86 (reserved)\n");
918 printf("HyperTransport: #%02x\n", type >> 11);
923 show_rom(struct device *d, int reg)
925 struct pci_dev *p = d->dev;
926 pciaddr_t rom = p->rom_base_addr;
927 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
928 u32 flg = get_conf_long(d, reg);
929 word cmd = get_conf_word(d, PCI_COMMAND);
931 if (!rom && !flg && !len)
934 if ((rom & PCI_ROM_ADDRESS_MASK) && !(flg & PCI_ROM_ADDRESS_MASK))
936 printf("[virtual] ");
939 printf("Expansion ROM at ");
940 if (rom & PCI_ROM_ADDRESS_MASK)
941 printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
942 else if (flg & PCI_ROM_ADDRESS_MASK)
945 printf("<unassigned>");
946 if (!(flg & PCI_ROM_ADDRESS_ENABLE))
947 printf(" [disabled]");
948 else if (!(cmd & PCI_COMMAND_MEMORY))
949 printf(" [disabled by cmd]");
955 show_msi(struct device *d, int where, int cap)
961 printf("Message Signalled Interrupts: 64bit%c Queue=%d/%d Enable%c\n",
962 FLAG(cap, PCI_MSI_FLAGS_64BIT),
963 (cap & PCI_MSI_FLAGS_QSIZE) >> 4,
964 (cap & PCI_MSI_FLAGS_QMASK) >> 1,
965 FLAG(cap, PCI_MSI_FLAGS_ENABLE));
968 is64 = cap & PCI_MSI_FLAGS_64BIT;
969 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
971 printf("\t\tAddress: ");
974 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
975 w = get_conf_word(d, where + PCI_MSI_DATA_64);
979 w = get_conf_word(d, where + PCI_MSI_DATA_32);
980 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
981 printf("%08x Data: %04x\n", t, w);
984 static void show_vendor(void)
986 printf("Vendor Specific Information\n");
989 static void show_debug(void)
991 printf("Debug port\n");
994 static float power_limit(int value, int scale)
996 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
997 return value * scales[scale];
1000 static const char *latency_l0s(int value)
1002 static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
1003 return latencies[value];
1006 static const char *latency_l1(int value)
1008 static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
1009 return latencies[value];
1012 static void show_express_dev(struct device *d, int where, int type)
1017 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
1018 printf("\t\tDevice: Supported: MaxPayload %d bytes, PhantFunc %d, ExtTag%c\n",
1019 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
1020 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
1021 FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
1022 printf("\t\tDevice: Latency L0s %s, L1 %s\n",
1023 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
1024 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
1025 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
1026 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
1027 printf("\t\tDevice: AtnBtn%c AtnInd%c PwrInd%c\n",
1028 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
1029 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
1030 if (type == PCI_EXP_TYPE_UPSTREAM)
1031 printf("\t\tDevice: SlotPowerLimit %f\n",
1032 power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
1033 (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
1035 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
1036 printf("\t\tDevice: Errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
1037 FLAG(w, PCI_EXP_DEVCTL_CERE),
1038 FLAG(w, PCI_EXP_DEVCTL_NFERE),
1039 FLAG(w, PCI_EXP_DEVCTL_FERE),
1040 FLAG(w, PCI_EXP_DEVCTL_URRE));
1041 printf("\t\tDevice: RlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c\n",
1042 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
1043 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
1044 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
1045 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
1046 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
1047 printf("\t\tDevice: MaxPayload %d bytes, MaxReadReq %d bytes\n",
1048 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
1049 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
1052 static char *link_speed(int speed)
1063 static char *aspm_support(int code)
1076 static const char *aspm_enabled(int code)
1078 static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
1082 static void show_express_link(struct device *d, int where, int type)
1087 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
1088 printf("\t\tLink: Supported Speed %s, Width x%d, ASPM %s, Port %d\n",
1089 link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
1090 aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
1092 printf("\t\tLink: Latency L0s %s, L1 %s\n",
1093 latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
1094 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
1095 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
1096 printf("\t\tLink: ASPM %s", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
1097 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
1098 (type == PCI_EXP_TYPE_LEG_END))
1099 printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
1100 if (w & PCI_EXP_LNKCTL_DISABLE)
1101 printf(" Disabled");
1102 printf(" CommClk%c ExtSynch%c\n", FLAG(w, PCI_EXP_LNKCTL_CLOCK),
1103 FLAG(w, PCI_EXP_LNKCTL_XSYNCH));
1104 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
1105 printf("\t\tLink: Speed %s, Width x%d\n",
1106 link_speed(t & PCI_EXP_LNKSTA_SPEED), (t & PCI_EXP_LNKSTA_WIDTH) >> 4);
1109 static const char *indicator(int code)
1111 static const char *names[] = { "Unknown", "On", "Blink", "Off" };
1115 static void show_express_slot(struct device *d, int where)
1120 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
1121 printf("\t\tSlot: AtnBtn%c PwrCtrl%c MRL%c AtnInd%c PwrInd%c HotPlug%c Surpise%c\n",
1122 FLAG(t, PCI_EXP_SLTCAP_ATNB),
1123 FLAG(t, PCI_EXP_SLTCAP_PWRC),
1124 FLAG(t, PCI_EXP_SLTCAP_MRL),
1125 FLAG(t, PCI_EXP_SLTCAP_ATNI),
1126 FLAG(t, PCI_EXP_SLTCAP_PWRI),
1127 FLAG(t, PCI_EXP_SLTCAP_HPC),
1128 FLAG(t, PCI_EXP_SLTCAP_HPS));
1129 printf("\t\tSlot: Number %d, PowerLimit %f\n", t >> 19,
1130 power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7,
1131 (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15));
1132 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
1133 printf("\t\tSlot: Enabled AtnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c\n",
1134 FLAG(w, PCI_EXP_SLTCTL_ATNB),
1135 FLAG(w, PCI_EXP_SLTCTL_PWRF),
1136 FLAG(w, PCI_EXP_SLTCTL_MRLS),
1137 FLAG(w, PCI_EXP_SLTCTL_PRSD),
1138 FLAG(w, PCI_EXP_SLTCTL_CMDC),
1139 FLAG(w, PCI_EXP_SLTCTL_HPIE));
1140 printf("\t\tSlot: AttnInd %s, PwrInd %s, Power%c\n",
1141 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
1142 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
1143 FLAG(w, w & PCI_EXP_SLTCTL_PWRC));
1146 static void show_express_root(struct device *d, int where)
1148 u16 w = get_conf_word(d, where + PCI_EXP_RTCTL);
1149 printf("\t\tRoot: Correctable%c Non-Fatal%c Fatal%c PME%c\n",
1150 FLAG(w, PCI_EXP_RTCTL_SECEE),
1151 FLAG(w, PCI_EXP_RTCTL_SENFEE),
1152 FLAG(w, PCI_EXP_RTCTL_SEFEE),
1153 FLAG(w, PCI_EXP_RTCTL_PMEIE));
1157 show_express(struct device *d, int where, int cap)
1159 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1166 case PCI_EXP_TYPE_ENDPOINT:
1169 case PCI_EXP_TYPE_LEG_END:
1170 printf("Legacy Endpoint");
1172 case PCI_EXP_TYPE_ROOT_PORT:
1173 slot = cap & PCI_EXP_FLAGS_SLOT;
1174 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1176 case PCI_EXP_TYPE_UPSTREAM:
1177 printf("Upstream Port");
1179 case PCI_EXP_TYPE_DOWNSTREAM:
1180 slot = cap & PCI_EXP_FLAGS_SLOT;
1181 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1183 case PCI_EXP_TYPE_PCI_BRIDGE:
1184 printf("PCI/PCI-X Bridge");
1187 printf("Unknown type");
1189 printf(" IRQ %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1196 if (type == PCI_EXP_TYPE_ROOT_PORT)
1198 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1201 show_express_dev(d, where, type);
1202 show_express_link(d, where, type);
1204 show_express_slot(d, where);
1205 if (type == PCI_EXP_TYPE_ROOT_PORT)
1206 show_express_root(d, where);
1210 show_msix(struct device *d, int where, int cap)
1214 printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
1215 FLAG(cap, PCI_MSIX_ENABLE),
1216 FLAG(cap, PCI_MSIX_MASK),
1217 (cap & PCI_MSIX_TABSIZE) + 1);
1218 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1221 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1222 printf("\t\tVector table: BAR=%d offset=%08x\n",
1223 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1224 off = get_conf_long(d, where + PCI_MSIX_PBA);
1225 printf("\t\tPBA: BAR=%d offset=%08x\n",
1226 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1230 show_slotid(int cap)
1232 int esr = cap & 0xff;
1235 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1236 esr & PCI_SID_ESR_NSLOTS,
1237 FLAG(esr, PCI_SID_ESR_FIC),
1242 show_aer(struct device *d UNUSED, int where UNUSED)
1244 printf("Advanced Error Reporting\n");
1248 show_vc(struct device *d UNUSED, int where UNUSED)
1250 printf("Virtual Channel\n");
1254 show_dsn(struct device *d, int where)
1257 if (!config_fetch(d, where + 4, 8))
1259 t1 = get_conf_long(d, where + 4);
1260 t2 = get_conf_long(d, where + 8);
1261 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
1262 t1 & 0xff, (t1 >> 8) & 0xff, (t1 >> 16) & 0xff, t1 >> 24,
1263 t2 & 0xff, (t2 >> 8) & 0xff, (t2 >> 16) & 0xff, t2 >> 24);
1267 show_pb(struct device *d UNUSED, int where UNUSED)
1269 printf("Power Budgeting\n");
1273 show_ext_caps(struct device *d)
1281 if (!config_fetch(d, where, 4))
1283 header = get_conf_long(d, where);
1286 id = header & 0xffff;
1287 printf("\tCapabilities: [%03x] ", where);
1290 case PCI_EXT_CAP_ID_AER:
1293 case PCI_EXT_CAP_ID_VC:
1296 case PCI_EXT_CAP_ID_DSN:
1299 case PCI_EXT_CAP_ID_PB:
1303 printf("Unknown (%d)\n", id);
1306 where = header >> 20;
1311 show_caps(struct device *d)
1313 int can_have_ext_caps = 0;
1315 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1317 int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
1321 printf("\tCapabilities: ");
1322 if (!config_fetch(d, where, 4))
1324 puts("<available only to root>");
1327 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1328 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1329 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1330 printf("[%02x] ", where);
1333 printf("<chain broken>\n");
1339 show_pm(d, where, cap);
1341 case PCI_CAP_ID_AGP:
1342 show_agp(d, where, cap);
1344 case PCI_CAP_ID_VPD:
1345 printf("Vital Product Data\n");
1347 case PCI_CAP_ID_SLOTID:
1350 case PCI_CAP_ID_MSI:
1351 show_msi(d, where, cap);
1353 case PCI_CAP_ID_PCIX:
1354 show_pcix(d, where);
1355 can_have_ext_caps = 1;
1358 show_ht(d, where, cap);
1360 case PCI_CAP_ID_VNDR:
1363 case PCI_CAP_ID_DBG:
1366 case PCI_CAP_ID_EXP:
1367 show_express(d, where, cap);
1368 can_have_ext_caps = 1;
1370 case PCI_CAP_ID_MSIX:
1371 show_msix(d, where, cap);
1374 printf("#%02x [%04x]\n", id, cap);
1379 if (can_have_ext_caps)
1384 show_htype0(struct device *d)
1387 show_rom(d, PCI_ROM_ADDRESS);
1392 show_htype1(struct device *d)
1394 u32 io_base = get_conf_byte(d, PCI_IO_BASE);
1395 u32 io_limit = get_conf_byte(d, PCI_IO_LIMIT);
1396 u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
1397 u32 mem_base = get_conf_word(d, PCI_MEMORY_BASE);
1398 u32 mem_limit = get_conf_word(d, PCI_MEMORY_LIMIT);
1399 u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
1400 u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE);
1401 u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT);
1402 u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
1403 word sec_stat = get_conf_word(d, PCI_SEC_STATUS);
1404 word brc = get_conf_word(d, PCI_BRIDGE_CONTROL);
1405 int verb = verbose > 2;
1408 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1409 get_conf_byte(d, PCI_PRIMARY_BUS),
1410 get_conf_byte(d, PCI_SECONDARY_BUS),
1411 get_conf_byte(d, PCI_SUBORDINATE_BUS),
1412 get_conf_byte(d, PCI_SEC_LATENCY_TIMER));
1414 if (io_type != (io_limit & PCI_IO_RANGE_TYPE_MASK) ||
1415 (io_type != PCI_IO_RANGE_TYPE_16 && io_type != PCI_IO_RANGE_TYPE_32))
1416 printf("\t!!! Unknown I/O range types %x/%x\n", io_base, io_limit);
1419 io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
1420 io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
1421 if (io_type == PCI_IO_RANGE_TYPE_32)
1423 io_base |= (get_conf_word(d, PCI_IO_BASE_UPPER16) << 16);
1424 io_limit |= (get_conf_word(d, PCI_IO_LIMIT_UPPER16) << 16);
1426 if (io_base <= io_limit || verb)
1427 printf("\tI/O behind bridge: %08x-%08x\n", io_base, io_limit+0xfff);
1430 if (mem_type != (mem_limit & PCI_MEMORY_RANGE_TYPE_MASK) ||
1432 printf("\t!!! Unknown memory range types %x/%x\n", mem_base, mem_limit);
1435 mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
1436 mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
1437 if (mem_base <= mem_limit || verb)
1438 printf("\tMemory behind bridge: %08x-%08x\n", mem_base, mem_limit + 0xfffff);
1441 if (pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
1442 (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64))
1443 printf("\t!!! Unknown prefetchable memory range types %x/%x\n", pref_base, pref_limit);
1446 pref_base = (pref_base & PCI_PREF_RANGE_MASK) << 16;
1447 pref_limit = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
1448 if (pref_base <= pref_limit || verb)
1450 if (pref_type == PCI_PREF_RANGE_TYPE_32)
1451 printf("\tPrefetchable memory behind bridge: %08x-%08x\n", pref_base, pref_limit + 0xfffff);
1453 printf("\tPrefetchable memory behind bridge: %08x%08x-%08x%08x\n",
1454 get_conf_long(d, PCI_PREF_BASE_UPPER32),
1456 get_conf_long(d, PCI_PREF_LIMIT_UPPER32),
1462 printf("\tSecondary status: 66MHz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c\n",
1463 FLAG(sec_stat, PCI_STATUS_66MHZ),
1464 FLAG(sec_stat, PCI_STATUS_FAST_BACK),
1465 FLAG(sec_stat, PCI_STATUS_PARITY),
1466 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1467 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1468 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1469 FLAG(sec_stat, PCI_STATUS_SIG_TARGET_ABORT),
1470 FLAG(sec_stat, PCI_STATUS_REC_TARGET_ABORT),
1471 FLAG(sec_stat, PCI_STATUS_REC_MASTER_ABORT),
1472 FLAG(sec_stat, PCI_STATUS_SIG_SYSTEM_ERROR),
1473 FLAG(sec_stat, PCI_STATUS_DETECTED_PARITY));
1475 show_rom(d, PCI_ROM_ADDRESS1);
1478 printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
1479 FLAG(brc, PCI_BRIDGE_CTL_PARITY),
1480 FLAG(brc, PCI_BRIDGE_CTL_SERR),
1481 FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
1482 FLAG(brc, PCI_BRIDGE_CTL_VGA),
1483 FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
1484 FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
1485 FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
1491 show_htype2(struct device *d)
1494 word cmd = get_conf_word(d, PCI_COMMAND);
1495 word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
1496 word exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
1497 int verb = verbose > 2;
1500 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1501 get_conf_byte(d, PCI_CB_PRIMARY_BUS),
1502 get_conf_byte(d, PCI_CB_CARD_BUS),
1503 get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
1504 get_conf_byte(d, PCI_CB_LATENCY_TIMER));
1508 u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
1509 u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
1510 if (limit > base || verb)
1511 printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
1512 (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
1513 (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
1518 u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
1519 u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
1520 if (!(base & PCI_IO_RANGE_TYPE_32))
1525 base &= PCI_CB_IO_RANGE_MASK;
1526 limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
1527 if (base <= limit || verb)
1528 printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
1529 (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
1532 if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
1533 printf("\tSecondary status: SERR\n");
1535 printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
1536 FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
1537 FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
1538 FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
1539 FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
1540 FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
1541 FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
1542 FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
1543 FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
1545 printf("\t16-bit legacy interface ports at %04x\n", exca);
1549 show_verbose(struct device *d)
1551 struct pci_dev *p = d->dev;
1552 word status = get_conf_word(d, PCI_STATUS);
1553 word cmd = get_conf_word(d, PCI_COMMAND);
1554 word class = get_conf_word(d, PCI_CLASS_DEVICE);
1555 byte bist = get_conf_byte(d, PCI_BIST);
1556 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1557 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
1558 byte cache_line = get_conf_byte(d, PCI_CACHE_LINE_SIZE);
1559 byte max_lat, min_gnt;
1560 byte int_pin = get_conf_byte(d, PCI_INTERRUPT_PIN);
1561 unsigned int irq = p->irq;
1562 word subsys_v, subsys_d;
1563 char ssnamebuf[256];
1569 case PCI_HEADER_TYPE_NORMAL:
1570 if (class == PCI_CLASS_BRIDGE_PCI)
1571 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1572 max_lat = get_conf_byte(d, PCI_MAX_LAT);
1573 min_gnt = get_conf_byte(d, PCI_MIN_GNT);
1574 subsys_v = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1575 subsys_d = get_conf_word(d, PCI_SUBSYSTEM_ID);
1577 case PCI_HEADER_TYPE_BRIDGE:
1578 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1579 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1580 irq = int_pin = min_gnt = max_lat = 0;
1581 subsys_v = subsys_d = 0;
1583 case PCI_HEADER_TYPE_CARDBUS:
1584 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1585 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1586 min_gnt = max_lat = 0;
1587 subsys_v = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1588 subsys_d = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1591 printf("\t!!! Unknown header type %02x\n", htype);
1595 if (subsys_v && subsys_v != 0xffff)
1596 printf("\tSubsystem: %s\n",
1597 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1598 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1599 p->vendor_id, p->device_id, subsys_v, subsys_d));
1603 printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c\n",
1604 FLAG(cmd, PCI_COMMAND_IO),
1605 FLAG(cmd, PCI_COMMAND_MEMORY),
1606 FLAG(cmd, PCI_COMMAND_MASTER),
1607 FLAG(cmd, PCI_COMMAND_SPECIAL),
1608 FLAG(cmd, PCI_COMMAND_INVALIDATE),
1609 FLAG(cmd, PCI_COMMAND_VGA_PALETTE),
1610 FLAG(cmd, PCI_COMMAND_PARITY),
1611 FLAG(cmd, PCI_COMMAND_WAIT),
1612 FLAG(cmd, PCI_COMMAND_SERR),
1613 FLAG(cmd, PCI_COMMAND_FAST_BACK));
1614 printf("\tStatus: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c\n",
1615 FLAG(status, PCI_STATUS_CAP_LIST),
1616 FLAG(status, PCI_STATUS_66MHZ),
1617 FLAG(status, PCI_STATUS_UDF),
1618 FLAG(status, PCI_STATUS_FAST_BACK),
1619 FLAG(status, PCI_STATUS_PARITY),
1620 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1621 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1622 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1623 FLAG(status, PCI_STATUS_SIG_TARGET_ABORT),
1624 FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
1625 FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
1626 FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
1627 FLAG(status, PCI_STATUS_DETECTED_PARITY));
1628 if (cmd & PCI_COMMAND_MASTER)
1630 printf("\tLatency: %d", latency);
1631 if (min_gnt || max_lat)
1635 printf("%dns min", min_gnt*250);
1636 if (min_gnt && max_lat)
1639 printf("%dns max", max_lat*250);
1643 printf(", Cache Line Size %02x", cache_line);
1647 printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n",
1648 (int_pin ? 'A' + int_pin - 1 : '?'), irq);
1652 printf("\tFlags: ");
1653 if (cmd & PCI_COMMAND_MASTER)
1654 printf("bus master, ");
1655 if (cmd & PCI_COMMAND_VGA_PALETTE)
1656 printf("VGA palette snoop, ");
1657 if (cmd & PCI_COMMAND_WAIT)
1658 printf("stepping, ");
1659 if (cmd & PCI_COMMAND_FAST_BACK)
1660 printf("fast Back2Back, ");
1661 if (status & PCI_STATUS_66MHZ)
1663 if (status & PCI_STATUS_UDF)
1664 printf("user-definable features, ");
1666 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1667 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1668 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??");
1669 if (cmd & PCI_COMMAND_MASTER)
1670 printf(", latency %d", latency);
1672 printf(", IRQ " PCIIRQ_FMT, irq);
1676 if (bist & PCI_BIST_CAPABLE)
1678 if (bist & PCI_BIST_START)
1679 printf("\tBIST is running\n");
1681 printf("\tBIST result: %02x\n", bist & PCI_BIST_CODE_MASK);
1686 case PCI_HEADER_TYPE_NORMAL:
1689 case PCI_HEADER_TYPE_BRIDGE:
1692 case PCI_HEADER_TYPE_CARDBUS:
1699 show_hex_dump(struct device *d)
1701 unsigned int i, cnt;
1703 cnt = d->config_cnt;
1704 if (show_hex >= 3 && config_fetch(d, cnt, 256-cnt))
1707 if (show_hex >= 4 && config_fetch(d, 256, 4096-256))
1711 for(i=0; i<cnt; i++)
1715 printf(" %02x", get_conf_byte(d, i));
1722 show_machine(struct device *d)
1724 struct pci_dev *p = d->dev;
1726 word sv_id=0, sd_id=0;
1727 char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
1729 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
1731 case PCI_HEADER_TYPE_NORMAL:
1732 sv_id = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1733 sd_id = get_conf_word(d, PCI_SUBSYSTEM_ID);
1735 case PCI_HEADER_TYPE_CARDBUS:
1736 sv_id = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1737 sd_id = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1743 printf("Device:\t");
1746 printf("Class:\t%s\n",
1747 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0));
1748 printf("Vendor:\t%s\n",
1749 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, 0, 0));
1750 printf("Device:\t%s\n",
1751 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, 0, 0));
1752 if (sv_id && sv_id != 0xffff)
1754 printf("SVendor:\t%s\n",
1755 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, sv_id, sd_id));
1756 printf("SDevice:\t%s\n",
1757 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1759 if (c = get_conf_byte(d, PCI_REVISION_ID))
1760 printf("Rev:\t%02x\n", c);
1761 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1762 printf("ProgIf:\t%02x\n", c);
1767 printf(" \"%s\" \"%s\" \"%s\"",
1768 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS,
1769 get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0),
1770 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR,
1771 p->vendor_id, p->device_id, 0, 0),
1772 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE,
1773 p->vendor_id, p->device_id, 0, 0));
1774 if (c = get_conf_byte(d, PCI_REVISION_ID))
1775 printf(" -r%02x", c);
1776 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1777 printf(" -p%02x", c);
1778 if (sv_id && sv_id != 0xffff)
1779 printf(" \"%s\" \"%s\"",
1780 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, sv_id, sd_id),
1781 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1783 printf(" \"\" \"\"");
1789 show_device(struct device *d)
1791 if (machine_readable)
1799 if (verbose || show_hex)
1808 for(d=first_dev; d; d=d->next)
1815 struct bridge *chain; /* Single-linked list of bridges */
1816 struct bridge *next, *child; /* Tree of bridges */
1817 struct bus *first_bus; /* List of buses connected to this bridge */
1818 unsigned int domain;
1819 unsigned int primary, secondary, subordinate; /* Bus numbers */
1820 struct device *br_dev;
1824 unsigned int domain;
1825 unsigned int number;
1826 struct bus *sibling;
1827 struct device *first_dev, **last_dev;
1830 static struct bridge host_bridge = { NULL, NULL, NULL, NULL, 0, ~0, 0, ~0, NULL };
1833 find_bus(struct bridge *b, unsigned int domain, unsigned int n)
1837 for(bus=b->first_bus; bus; bus=bus->sibling)
1838 if (bus->domain == domain && bus->number == n)
1844 new_bus(struct bridge *b, unsigned int domain, unsigned int n)
1846 struct bus *bus = xmalloc(sizeof(struct bus));
1848 bus = xmalloc(sizeof(struct bus));
1849 bus->domain = domain;
1851 bus->sibling = b->first_bus;
1852 bus->first_dev = NULL;
1853 bus->last_dev = &bus->first_dev;
1859 insert_dev(struct device *d, struct bridge *b)
1861 struct pci_dev *p = d->dev;
1864 if (! (bus = find_bus(b, p->domain, p->bus)))
1867 for(c=b->child; c; c=c->next)
1868 if (c->domain == p->domain && c->secondary <= p->bus && p->bus <= c->subordinate)
1873 bus = new_bus(b, p->domain, p->bus);
1875 /* Simple insertion at the end _does_ guarantee the correct order as the
1876 * original device list was sorted by (domain, bus, devfn) lexicographically
1877 * and all devices on the new list have the same bus number.
1880 bus->last_dev = &d->next;
1887 struct device *d, *d2;
1888 struct bridge **last_br, *b;
1890 /* Build list of bridges */
1892 last_br = &host_bridge.chain;
1893 for(d=first_dev; d; d=d->next)
1895 word class = get_conf_word(d, PCI_CLASS_DEVICE);
1896 byte ht = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1897 if (class == PCI_CLASS_BRIDGE_PCI &&
1898 (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS))
1900 b = xmalloc(sizeof(struct bridge));
1901 b->domain = d->dev->domain;
1902 if (ht == PCI_HEADER_TYPE_BRIDGE)
1904 b->primary = get_conf_byte(d, PCI_CB_PRIMARY_BUS);
1905 b->secondary = get_conf_byte(d, PCI_CB_CARD_BUS);
1906 b->subordinate = get_conf_byte(d, PCI_CB_SUBORDINATE_BUS);
1910 b->primary = get_conf_byte(d, PCI_PRIMARY_BUS);
1911 b->secondary = get_conf_byte(d, PCI_SECONDARY_BUS);
1912 b->subordinate = get_conf_byte(d, PCI_SUBORDINATE_BUS);
1915 last_br = &b->chain;
1916 b->next = b->child = NULL;
1917 b->first_bus = NULL;
1923 /* Create a bridge tree */
1925 for(b=&host_bridge; b; b=b->chain)
1927 struct bridge *c, *best;
1929 for(c=&host_bridge; c; c=c->chain)
1930 if (c != b && (c == &host_bridge || b->domain == c->domain) &&
1931 b->primary >= c->secondary && b->primary <= c->subordinate &&
1932 (!best || best->subordinate - best->primary > c->subordinate - c->primary))
1936 b->next = best->child;
1941 /* Insert secondary bus for each bridge */
1943 for(b=&host_bridge; b; b=b->chain)
1944 if (!find_bus(b, b->domain, b->secondary))
1945 new_bus(b, b->domain, b->secondary);
1947 /* Create bus structs and link devices */
1949 for(d=first_dev; d;)
1952 insert_dev(d, &host_bridge);
1958 print_it(byte *line, byte *p)
1962 fputs(line, stdout);
1963 for(p=line; *p; p++)
1964 if (*p == '+' || *p == '|')
1970 static void show_tree_bridge(struct bridge *, byte *, byte *);
1973 show_tree_dev(struct device *d, byte *line, byte *p)
1975 struct pci_dev *q = d->dev;
1979 p += sprintf(p, "%02x.%x", q->dev, q->func);
1980 for(b=&host_bridge; b; b=b->chain)
1983 if (b->secondary == b->subordinate)
1984 p += sprintf(p, "-[%04x:%02x]-", b->domain, b->secondary);
1986 p += sprintf(p, "-[%04x:%02x-%02x]-", b->domain, b->secondary, b->subordinate);
1987 show_tree_bridge(b, line, p);
1991 p += sprintf(p, " %s",
1992 pci_lookup_name(pacc, namebuf, sizeof(namebuf),
1993 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1994 q->vendor_id, q->device_id, 0, 0));
1999 show_tree_bus(struct bus *b, byte *line, byte *p)
2003 else if (!b->first_dev->next)
2007 show_tree_dev(b->first_dev, line, p);
2011 struct device *d = b->first_dev;
2016 show_tree_dev(d, line, p+2);
2021 show_tree_dev(d, line, p+2);
2026 show_tree_bridge(struct bridge *b, byte *line, byte *p)
2029 if (!b->first_bus->sibling)
2031 if (b == &host_bridge)
2032 p += sprintf(p, "[%04x:%02x]-", b->domain, b->first_bus->number);
2033 show_tree_bus(b->first_bus, line, p);
2037 struct bus *u = b->first_bus;
2042 k = p + sprintf(p, "+-[%04x:%02x]-", u->domain, u->number);
2043 show_tree_bus(u, line, k);
2046 k = p + sprintf(p, "\\-[%04x:%02x]-", u->domain, u->number);
2047 show_tree_bus(u, line, k);
2057 show_tree_bridge(&host_bridge, line, line);
2060 /* Bus mapping mode */
2063 struct bus_bridge *next;
2064 byte this, dev, func, first, last, bug;
2070 struct bus_bridge *bridges, *via;
2073 static struct bus_info *bus_info;
2076 map_bridge(struct bus_info *bi, struct device *d, int np, int ns, int nl)
2078 struct bus_bridge *b = xmalloc(sizeof(struct bus_bridge));
2079 struct pci_dev *p = d->dev;
2081 b->next = bi->bridges;
2083 b->this = get_conf_byte(d, np);
2086 b->first = get_conf_byte(d, ns);
2087 b->last = get_conf_byte(d, nl);
2088 printf("## %02x.%02x:%d is a bridge from %02x to %02x-%02x\n",
2089 p->bus, p->dev, p->func, b->this, b->first, b->last);
2090 if (b->this != p->bus)
2091 printf("!!! Bridge points to invalid primary bus.\n");
2092 if (b->first > b->last)
2094 printf("!!! Bridge points to invalid bus range.\n");
2103 int verbose = pacc->debugging;
2104 struct bus_info *bi = bus_info + bus;
2108 printf("Mapping bus %02x\n", bus);
2109 for(dev = 0; dev < 32; dev++)
2110 if (filter.slot < 0 || filter.slot == dev)
2113 for(func = 0; func < func_limit; func++)
2114 if (filter.func < 0 || filter.func == func)
2116 /* XXX: Bus mapping supports only domain 0 */
2117 struct pci_dev *p = pci_get_dev(pacc, 0, bus, dev, func);
2118 u16 vendor = pci_read_word(p, PCI_VENDOR_ID);
2119 if (vendor && vendor != 0xffff)
2121 if (!func && (pci_read_byte(p, PCI_HEADER_TYPE) & 0x80))
2124 printf("Discovered device %02x:%02x.%d\n", bus, dev, func);
2126 if (d = scan_device(p))
2129 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
2131 case PCI_HEADER_TYPE_BRIDGE:
2132 map_bridge(bi, d, PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS);
2134 case PCI_HEADER_TYPE_CARDBUS:
2135 map_bridge(bi, d, PCI_CB_PRIMARY_BUS, PCI_CB_CARD_BUS, PCI_CB_SUBORDINATE_BUS);
2141 printf("But it was filtered out.\n");
2149 do_map_bridges(int bus, int min, int max)
2151 struct bus_info *bi = bus_info + bus;
2152 struct bus_bridge *b;
2155 for(b=bi->bridges; b; b=b->next)
2157 if (bus_info[b->first].guestbook)
2159 else if (b->first < min || b->last > max)
2163 bus_info[b->first].via = b;
2164 do_map_bridges(b->first, b->first, b->last);
2174 printf("\nSummary of buses:\n\n");
2175 for(i=0; i<256; i++)
2176 if (bus_info[i].exists && !bus_info[i].guestbook)
2177 do_map_bridges(i, 0, 255);
2178 for(i=0; i<256; i++)
2180 struct bus_info *bi = bus_info + i;
2181 struct bus_bridge *b = bi->via;
2185 printf("%02x: ", i);
2187 printf("Entered via %02x:%02x.%d\n", b->this, b->dev, b->func);
2189 printf("Primary host bus\n");
2191 printf("Secondary host bus (?)\n");
2193 for(b=bi->bridges; b; b=b->next)
2195 printf("\t%02x.%d Bridge to %02x-%02x", b->dev, b->func, b->first, b->last);
2199 printf(" <overlap bug>");
2202 printf(" <crossing bug>");
2213 if (pacc->method == PCI_ACCESS_PROC_BUS_PCI ||
2214 pacc->method == PCI_ACCESS_DUMP)
2215 printf("WARNING: Bus mapping can be reliable only with direct hardware access enabled.\n\n");
2216 bus_info = xmalloc(sizeof(struct bus_info) * 256);
2217 bzero(bus_info, sizeof(struct bus_info) * 256);
2218 if (filter.bus >= 0)
2219 do_map_bus(filter.bus);
2223 for(bus=0; bus<256; bus++)
2232 main(int argc, char **argv)
2237 if (argc == 2 && !strcmp(argv[1], "--version"))
2239 puts("lspci version " PCIUTILS_VERSION);
2245 pci_filter_init(pacc, &filter);
2247 while ((i = getopt(argc, argv, options)) != -1)
2251 pacc->numeric_ids = 1;
2257 pacc->buscentric = 1;
2258 buscentric_view = 1;
2261 if (msg = pci_filter_parse_slot(&filter, optarg))
2265 if (msg = pci_filter_parse_id(&filter, optarg))
2275 pacc->id_file_name = optarg;
2284 if (parse_generic_option(i, pacc, optarg))
2287 fprintf(stderr, help_msg, pacc->id_file_name);