2 * The PCI Utilities -- List All PCI Devices
4 * Copyright (c) 1997--2004 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
19 static int verbose; /* Show detailed information */
20 static int buscentric_view; /* Show bus addresses/IRQ's instead of CPU-visible ones */
21 static int show_hex; /* Show contents of config space as hexadecimal numbers */
22 static struct pci_filter filter; /* Device filter */
23 static int show_tree; /* Show bus tree */
24 static int machine_readable; /* Generate machine-readable output */
25 static int map_mode; /* Bus mapping mode enabled */
27 static char options[] = "nvbxs:d:ti:mgM" GENERIC_OPTIONS ;
29 static char help_msg[] = "\
30 Usage: lspci [<switches>]\n\
33 -n\t\tShow numeric ID's\n\
34 -b\t\tBus-centric view (PCI addresses and IRQ's instead of those seen by the CPU)\n\
35 -x\t\tShow hex-dump of the standard portion of config space\n\
36 -xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n\
37 -s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n\
38 -d [<vendor>]:[<device>]\tShow only selected devices\n\
39 -t\t\tShow bus tree\n\
40 -m\t\tProduce machine-readable output\n\
41 -i <file>\tUse specified ID database instead of %s\n\
42 -M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
46 /* Communication with libpci */
48 static struct pci_access *pacc;
51 * If we aren't being compiled by GCC, use malloc() instead of alloca().
52 * This increases our memory footprint, but only slightly since we don't
60 /* Our view of the PCI bus */
65 unsigned int config_cnt;
69 static struct device *first_dev;
71 static struct device *
72 scan_device(struct pci_dev *p)
74 int how_much = (show_hex > 2) ? 256 : 64;
77 if (!pci_filter_match(&filter, p))
79 d = xmalloc(sizeof(struct device));
82 if (!pci_read_block(p, 0, d->config, how_much))
83 die("Unable to read %d bytes of configuration space.", how_much);
84 if (how_much < 128 && (d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
86 /* For cardbus bridges, we need to fetch 64 bytes more to get the full standard header... */
87 if (!pci_read_block(p, 64, d->config+64, 64))
88 die("Unable to read cardbus bridge extension data.");
91 d->config_cnt = how_much;
92 pci_setup_cache(p, d->config, d->config_cnt);
93 pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
104 for(p=pacc->devices; p; p=p->next)
105 if (d = scan_device(p))
118 static int is_root = -1;
121 is_root = !geteuid();
127 config_fetch(struct device *d, unsigned int pos, unsigned int len)
129 if (pos + len < d->config_cnt)
131 if (pacc->method != PCI_ACCESS_DUMP && !check_root())
133 return pci_read_block(d->dev, pos, d->config + pos, len);
136 /* Config space accesses */
139 get_conf_byte(struct device *d, unsigned int pos)
141 return d->config[pos];
145 get_conf_word(struct device *d, unsigned int pos)
147 return d->config[pos] | (d->config[pos+1] << 8);
151 get_conf_long(struct device *d, unsigned int pos)
153 return d->config[pos] |
154 (d->config[pos+1] << 8) |
155 (d->config[pos+2] << 16) |
156 (d->config[pos+3] << 24);
162 compare_them(const void *A, const void *B)
164 const struct pci_dev *a = (*(const struct device **)A)->dev;
165 const struct pci_dev *b = (*(const struct device **)B)->dev;
167 if (a->domain < b->domain)
169 if (a->domain > b->domain)
179 if (a->func < b->func)
181 if (a->func > b->func)
189 struct device **index, **h, **last_dev;
194 for(d=first_dev; d; d=d->next)
196 h = index = alloca(sizeof(struct device *) * cnt);
197 for(d=first_dev; d; d=d->next)
199 qsort(index, cnt, sizeof(struct device *), compare_them);
200 last_dev = &first_dev;
205 last_dev = &(*h)->next;
213 #define FLAG(x,y) ((x & y) ? '+' : '-')
216 show_slot_name(struct device *d)
218 struct pci_dev *p = d->dev;
221 printf("%04x:", p->domain);
222 printf("%02x:%02x.%d", p->bus, p->dev, p->func);
226 show_terse(struct device *d)
229 struct pci_dev *p = d->dev;
230 byte classbuf[128], devbuf[128];
234 pci_lookup_name(pacc, classbuf, sizeof(classbuf),
236 get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0),
237 pci_lookup_name(pacc, devbuf, sizeof(devbuf),
238 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
239 p->vendor_id, p->device_id, 0, 0));
240 if (c = get_conf_byte(d, PCI_REVISION_ID))
241 printf(" (rev %02x)", c);
245 c = get_conf_byte(d, PCI_CLASS_PROG);
246 x = pci_lookup_name(pacc, devbuf, sizeof(devbuf),
248 get_conf_word(d, PCI_CLASS_DEVICE), c, 0, 0);
251 printf(" (prog-if %02x", c);
261 show_size(pciaddr_t x)
267 printf("%d", (int) x);
268 else if (x < 1048576)
269 printf("%dK", (int)(x / 1024));
270 else if (x < 0x80000000)
271 printf("%dM", (int)(x / 1048576));
273 printf(PCIADDR_T_FMT, x);
278 show_bases(struct device *d, int cnt)
280 struct pci_dev *p = d->dev;
281 word cmd = get_conf_word(d, PCI_COMMAND);
286 pciaddr_t pos = p->base_addr[i];
287 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
288 u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
289 if (flg == 0xffffffff)
291 if (!pos && !flg && !len)
294 printf("\tRegion %d: ", i);
297 if (pos && !flg) /* Reported by the OS, but not by the device */
299 printf("[virtual] ");
302 if (flg & PCI_BASE_ADDRESS_SPACE_IO)
304 pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
305 printf("I/O ports at ");
307 printf(PCIADDR_PORT_FMT, a);
308 else if (flg & PCI_BASE_ADDRESS_IO_MASK)
311 printf("<unassigned>");
312 if (!(cmd & PCI_COMMAND_IO))
313 printf(" [disabled]");
317 int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
318 pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
322 printf("Memory at ");
323 if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
327 printf("<invalid-64bit-slot>");
333 z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
337 printf("%08x" PCIADDR_T_FMT, z, a);
339 printf("<unassigned>");
347 printf(PCIADDR_T_FMT, a);
349 printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
351 printf(" (%s, %sprefetchable)",
352 (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
353 (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
354 (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
355 (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
356 if (!(cmd & PCI_COMMAND_MEMORY))
357 printf(" [disabled]");
365 show_pm(struct device *d, int where, int cap)
368 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
370 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
373 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
374 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
375 FLAG(cap, PCI_PM_CAP_DSI),
376 FLAG(cap, PCI_PM_CAP_D1),
377 FLAG(cap, PCI_PM_CAP_D2),
378 pm_aux_current[(cap >> 6) & 7],
379 FLAG(cap, PCI_PM_CAP_PME_D0),
380 FLAG(cap, PCI_PM_CAP_PME_D1),
381 FLAG(cap, PCI_PM_CAP_PME_D2),
382 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
383 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
384 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
386 t = get_conf_word(d, where + PCI_PM_CTRL);
387 printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
388 t & PCI_PM_CTRL_STATE_MASK,
389 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
390 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
391 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
392 FLAG(t, PCI_PM_CTRL_PME_STATUS));
393 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
395 printf("\t\tBridge: PM%c B3%c\n",
396 FLAG(t, PCI_PM_BPCC_ENABLE),
397 FLAG(~t, PCI_PM_PPB_B2_B3));
401 format_agp_rate(int rate, char *buf, int agp3)
411 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
416 strcpy(buf, "<none>");
420 show_agp(struct device *d, int where, int cap)
427 ver = (cap >> 4) & 0x0f;
429 printf("AGP version %x.%x\n", ver, rev);
432 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
434 t = get_conf_long(d, where + PCI_AGP_STATUS);
435 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
437 format_agp_rate(t & 7, rate, agp3);
438 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
439 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
440 FLAG(t, PCI_AGP_STATUS_ISOCH),
441 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
442 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
443 FLAG(t, PCI_AGP_STATUS_SBA),
444 FLAG(t, PCI_AGP_STATUS_ITA_COH),
445 FLAG(t, PCI_AGP_STATUS_GART64),
446 FLAG(t, PCI_AGP_STATUS_HTRANS),
447 FLAG(t, PCI_AGP_STATUS_64BIT),
448 FLAG(t, PCI_AGP_STATUS_FW),
449 FLAG(t, PCI_AGP_STATUS_AGP3),
451 t = get_conf_long(d, where + PCI_AGP_COMMAND);
452 format_agp_rate(t & 7, rate, agp3);
453 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
454 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
455 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
456 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
457 FLAG(t, PCI_AGP_COMMAND_SBA),
458 FLAG(t, PCI_AGP_COMMAND_AGP),
459 FLAG(t, PCI_AGP_COMMAND_GART64),
460 FLAG(t, PCI_AGP_COMMAND_64BIT),
461 FLAG(t, PCI_AGP_COMMAND_FW),
466 show_pcix_nobridge(struct device *d, int where)
471 printf("PCI-X non-bridge device.\n");
476 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
479 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
480 status = get_conf_long(d, where + PCI_PCIX_STATUS);
481 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
482 FLAG(command, PCI_PCIX_COMMAND_DPERE),
483 FLAG(command, PCI_PCIX_COMMAND_ERO),
484 ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U),
485 ((command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U));
486 printf("\t\tStatus: Bus=%u Dev=%u Func=%u 64bit%c 133MHz%c SCD%c USC%c, DC=%s, DMMRBC=%u, DMOST=%u, DMCRS=%u, RSCEM%c\n",
487 ((status >> 8) & 0xffU), // bus
488 ((status >> 3) & 0x1fU), // dev
489 (status & PCI_PCIX_STATUS_FUNCTION), // function
490 FLAG(status, PCI_PCIX_STATUS_64BIT),
491 FLAG(status, PCI_PCIX_STATUS_133MHZ),
492 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
493 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
494 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
495 ((status >> 21) & 3U),
496 ((status >> 23) & 7U),
497 ((status >> 26) & 7U),
498 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS));
502 show_pcix_bridge(struct device *d, int where)
506 u32 status, upstcr, downstcr;
508 printf("PCI-X bridge device.\n");
513 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
516 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
517 printf("\t\tSecondary Status: 64bit%c, 133MHz%c, SCD%c, USC%c, SCO%c, SRD%c Freq=%d\n",
518 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
519 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
520 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
521 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
522 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
523 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
524 ((secstatus >> 6) & 7));
525 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
526 printf("\t\tStatus: Bus=%u Dev=%u Func=%u 64bit%c 133MHz%c SCD%c USC%c, SCO%c, SRD%c\n",
527 ((status >> 8) & 0xff), // bus
528 ((status >> 3) & 0x1f), // dev
529 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION), // function
530 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
531 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
532 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
533 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
534 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
535 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
536 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
537 printf("\t\t: Upstream: Capacity=%u, Commitment Limit=%u\n",
538 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
539 (upstcr >> 16) & 0xffff);
540 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
541 printf("\t\t: Downstream: Capacity=%u, Commitment Limit=%u\n",
542 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
543 (downstcr >> 16) & 0xffff);
547 show_pcix(struct device *d, int where)
549 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
551 case PCI_HEADER_TYPE_NORMAL:
552 show_pcix_nobridge(d, where);
554 case PCI_HEADER_TYPE_BRIDGE:
555 show_pcix_bridge(d, where);
561 ht_link_width(unsigned width)
563 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
564 return widths[width];
568 ht_link_freq(unsigned freq)
570 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
571 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
576 show_ht_pri(struct device *d, int where, int cmd)
578 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
579 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
581 printf("HyperTransport: Slave or Primary Interface\n");
585 printf("\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n",
586 (cmd & PCI_HT_PRI_CMD_BUID),
587 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
588 FLAG(cmd, PCI_HT_PRI_CMD_MH),
589 FLAG(cmd, PCI_HT_PRI_CMD_DD),
590 FLAG(cmd, PCI_HT_PRI_CMD_DUL));
591 config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0);
592 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
593 printf("\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n",
594 FLAG(lctr0, PCI_HT_LCTR_CFLE),
595 FLAG(lctr0, PCI_HT_LCTR_CST),
596 FLAG(lctr0, PCI_HT_LCTR_CFE),
597 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
598 FLAG(lctr0, PCI_HT_LCTR_INIT),
599 FLAG(lctr0, PCI_HT_LCTR_EOC),
600 FLAG(lctr0, PCI_HT_LCTR_TXO),
601 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
602 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
603 FLAG(lctr0, PCI_HT_LCTR_LSEN),
604 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
605 FLAG(lctr0, PCI_HT_LCTR_64B));
606 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
607 printf("\t\tLink Config 0: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
608 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
609 FLAG(lcnf0, PCI_HT_LCNF_DFI),
610 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
611 FLAG(lcnf0, PCI_HT_LCNF_DFO),
612 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
613 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
614 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
615 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
616 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
617 printf("\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n",
618 FLAG(lctr1, PCI_HT_LCTR_CFLE),
619 FLAG(lctr1, PCI_HT_LCTR_CST),
620 FLAG(lctr1, PCI_HT_LCTR_CFE),
621 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
622 FLAG(lctr1, PCI_HT_LCTR_INIT),
623 FLAG(lctr1, PCI_HT_LCTR_EOC),
624 FLAG(lctr1, PCI_HT_LCTR_TXO),
625 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
626 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
627 FLAG(lctr1, PCI_HT_LCTR_LSEN),
628 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
629 FLAG(lctr1, PCI_HT_LCTR_64B));
630 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
631 printf("\t\tLink Config 1: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
632 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
633 FLAG(lcnf1, PCI_HT_LCNF_DFI),
634 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
635 FLAG(lcnf1, PCI_HT_LCNF_DFO),
636 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
637 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
638 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
639 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
640 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
641 printf("\t\tRevision ID: %u.%02u\n",
642 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
643 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
644 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
645 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
646 FLAG(lfrer0, PCI_HT_LFRER_PROT),
647 FLAG(lfrer0, PCI_HT_LFRER_OV),
648 FLAG(lfrer0, PCI_HT_LFRER_EOC),
649 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
650 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
651 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
652 FLAG(lfcap0, PCI_HT_LFCAP_200),
653 FLAG(lfcap0, PCI_HT_LFCAP_300),
654 FLAG(lfcap0, PCI_HT_LFCAP_400),
655 FLAG(lfcap0, PCI_HT_LFCAP_500),
656 FLAG(lfcap0, PCI_HT_LFCAP_600),
657 FLAG(lfcap0, PCI_HT_LFCAP_800),
658 FLAG(lfcap0, PCI_HT_LFCAP_1000),
659 FLAG(lfcap0, PCI_HT_LFCAP_1200),
660 FLAG(lfcap0, PCI_HT_LFCAP_1400),
661 FLAG(lfcap0, PCI_HT_LFCAP_1600),
662 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
663 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
664 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
665 FLAG(ftr, PCI_HT_FTR_ISOCFC),
666 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
667 FLAG(ftr, PCI_HT_FTR_CRCTM),
668 FLAG(ftr, PCI_HT_FTR_ECTLT),
669 FLAG(ftr, PCI_HT_FTR_64BA),
670 FLAG(ftr, PCI_HT_FTR_UIDRD));
671 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
672 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
673 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
674 FLAG(lfrer1, PCI_HT_LFRER_PROT),
675 FLAG(lfrer1, PCI_HT_LFRER_OV),
676 FLAG(lfrer1, PCI_HT_LFRER_EOC),
677 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
678 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
679 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
680 FLAG(lfcap1, PCI_HT_LFCAP_200),
681 FLAG(lfcap1, PCI_HT_LFCAP_300),
682 FLAG(lfcap1, PCI_HT_LFCAP_400),
683 FLAG(lfcap1, PCI_HT_LFCAP_500),
684 FLAG(lfcap1, PCI_HT_LFCAP_600),
685 FLAG(lfcap1, PCI_HT_LFCAP_800),
686 FLAG(lfcap1, PCI_HT_LFCAP_1000),
687 FLAG(lfcap1, PCI_HT_LFCAP_1200),
688 FLAG(lfcap1, PCI_HT_LFCAP_1400),
689 FLAG(lfcap1, PCI_HT_LFCAP_1600),
690 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
691 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
692 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
693 FLAG(eh, PCI_HT_EH_PFLE),
694 FLAG(eh, PCI_HT_EH_OFLE),
695 FLAG(eh, PCI_HT_EH_PFE),
696 FLAG(eh, PCI_HT_EH_OFE),
697 FLAG(eh, PCI_HT_EH_EOCFE),
698 FLAG(eh, PCI_HT_EH_RFE),
699 FLAG(eh, PCI_HT_EH_CRCFE),
700 FLAG(eh, PCI_HT_EH_SERRFE),
701 FLAG(eh, PCI_HT_EH_CF),
702 FLAG(eh, PCI_HT_EH_RE),
703 FLAG(eh, PCI_HT_EH_PNFE),
704 FLAG(eh, PCI_HT_EH_ONFE),
705 FLAG(eh, PCI_HT_EH_EOCNFE),
706 FLAG(eh, PCI_HT_EH_RNFE),
707 FLAG(eh, PCI_HT_EH_CRCNFE),
708 FLAG(eh, PCI_HT_EH_SERRNFE));
709 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
710 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
711 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
712 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
713 printf("\t\tBus Number: %02x\n", bn);
717 show_ht_sec(struct device *d, int where, int cmd)
719 u16 lctr, lcnf, ftr, eh;
720 u8 rid, lfrer, lfcap, mbu, mlu;
722 printf("HyperTransport: Host or Secondary Interface\n");
726 printf("\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n",
727 FLAG(cmd, PCI_HT_SEC_CMD_WR),
728 FLAG(cmd, PCI_HT_SEC_CMD_DE),
729 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
730 FLAG(cmd, PCI_HT_SEC_CMD_CS),
731 FLAG(cmd, PCI_HT_SEC_CMD_HH),
732 FLAG(cmd, PCI_HT_SEC_CMD_AS),
733 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
734 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
735 config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR);
736 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
737 printf("\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n",
738 FLAG(lctr, PCI_HT_LCTR_CFLE),
739 FLAG(lctr, PCI_HT_LCTR_CST),
740 FLAG(lctr, PCI_HT_LCTR_CFE),
741 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
742 FLAG(lctr, PCI_HT_LCTR_INIT),
743 FLAG(lctr, PCI_HT_LCTR_EOC),
744 FLAG(lctr, PCI_HT_LCTR_TXO),
745 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
746 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
747 FLAG(lctr, PCI_HT_LCTR_LSEN),
748 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
749 FLAG(lctr, PCI_HT_LCTR_64B));
750 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
751 printf("\t\tLink Config: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
752 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
753 FLAG(lcnf, PCI_HT_LCNF_DFI),
754 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
755 FLAG(lcnf, PCI_HT_LCNF_DFO),
756 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
757 FLAG(lcnf, PCI_HT_LCNF_DFIE),
758 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
759 FLAG(lcnf, PCI_HT_LCNF_DFOE));
760 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
761 printf("\t\tRevision ID: %u.%02u\n",
762 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
763 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
764 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
765 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
766 FLAG(lfrer, PCI_HT_LFRER_PROT),
767 FLAG(lfrer, PCI_HT_LFRER_OV),
768 FLAG(lfrer, PCI_HT_LFRER_EOC),
769 FLAG(lfrer, PCI_HT_LFRER_CTLT));
770 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
771 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
772 FLAG(lfcap, PCI_HT_LFCAP_200),
773 FLAG(lfcap, PCI_HT_LFCAP_300),
774 FLAG(lfcap, PCI_HT_LFCAP_400),
775 FLAG(lfcap, PCI_HT_LFCAP_500),
776 FLAG(lfcap, PCI_HT_LFCAP_600),
777 FLAG(lfcap, PCI_HT_LFCAP_800),
778 FLAG(lfcap, PCI_HT_LFCAP_1000),
779 FLAG(lfcap, PCI_HT_LFCAP_1200),
780 FLAG(lfcap, PCI_HT_LFCAP_1400),
781 FLAG(lfcap, PCI_HT_LFCAP_1600),
782 FLAG(lfcap, PCI_HT_LFCAP_VEND));
783 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
784 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
785 FLAG(ftr, PCI_HT_FTR_ISOCFC),
786 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
787 FLAG(ftr, PCI_HT_FTR_CRCTM),
788 FLAG(ftr, PCI_HT_FTR_ECTLT),
789 FLAG(ftr, PCI_HT_FTR_64BA),
790 FLAG(ftr, PCI_HT_FTR_UIDRD),
791 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
792 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
793 if (ftr & PCI_HT_SEC_FTR_EXTRS)
795 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
796 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
797 FLAG(eh, PCI_HT_EH_PFLE),
798 FLAG(eh, PCI_HT_EH_OFLE),
799 FLAG(eh, PCI_HT_EH_PFE),
800 FLAG(eh, PCI_HT_EH_OFE),
801 FLAG(eh, PCI_HT_EH_EOCFE),
802 FLAG(eh, PCI_HT_EH_RFE),
803 FLAG(eh, PCI_HT_EH_CRCFE),
804 FLAG(eh, PCI_HT_EH_SERRFE),
805 FLAG(eh, PCI_HT_EH_CF),
806 FLAG(eh, PCI_HT_EH_RE),
807 FLAG(eh, PCI_HT_EH_PNFE),
808 FLAG(eh, PCI_HT_EH_ONFE),
809 FLAG(eh, PCI_HT_EH_EOCNFE),
810 FLAG(eh, PCI_HT_EH_RNFE),
811 FLAG(eh, PCI_HT_EH_CRCNFE),
812 FLAG(eh, PCI_HT_EH_SERRNFE));
813 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
814 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
815 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
820 show_ht(struct device *d, int where, int cmd)
824 switch (cmd & PCI_HT_CMD_TYP_HI)
826 case PCI_HT_CMD_TYP_HI_PRI:
827 show_ht_pri(d, where, cmd);
829 case PCI_HT_CMD_TYP_HI_SEC:
830 show_ht_sec(d, where, cmd);
834 type = cmd & PCI_HT_CMD_TYP;
837 case PCI_HT_CMD_TYP_SW:
838 printf("HyperTransport: Switch\n");
840 case PCI_HT_CMD_TYP_IDC:
841 printf("HyperTransport: Interrupt Discovery and Configuration\n");
843 case PCI_HT_CMD_TYP_RID:
844 printf("HyperTransport: Revision ID: %u.%02u\n",
845 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
847 case PCI_HT_CMD_TYP_UIDC:
848 printf("HyperTransport: UnitID Clumping\n");
850 case PCI_HT_CMD_TYP_ECSA:
851 printf("HyperTransport: Extended Configuration Space Access\n");
853 case PCI_HT_CMD_TYP_AM:
854 printf("HyperTransport: Address Mapping\n");
856 case PCI_HT_CMD_TYP_MSIM:
857 printf("HyperTransport: MSI Mapping\n");
859 case PCI_HT_CMD_TYP_DR:
860 printf("HyperTransport: DirectRoute\n");
862 case PCI_HT_CMD_TYP_VCS:
863 printf("HyperTransport: VCSet\n");
865 case PCI_HT_CMD_TYP_RM:
866 printf("HyperTransport: Retry Mode\n");
868 case PCI_HT_CMD_TYP_X86:
869 printf("HyperTransport: X86 (reserved)\n");
872 printf("HyperTransport: #%02x\n", type >> 11);
877 show_rom(struct device *d)
879 struct pci_dev *p = d->dev;
880 pciaddr_t rom = p->rom_base_addr;
881 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
885 printf("\tExpansion ROM at ");
886 if (rom & PCI_ROM_ADDRESS_MASK)
887 printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
889 printf("<unassigned>");
890 if (!(rom & PCI_ROM_ADDRESS_ENABLE))
891 printf(" [disabled]");
897 show_msi(struct device *d, int where, int cap)
903 printf("Message Signalled Interrupts: 64bit%c Queue=%d/%d Enable%c\n",
904 FLAG(cap, PCI_MSI_FLAGS_64BIT),
905 (cap & PCI_MSI_FLAGS_QSIZE) >> 4,
906 (cap & PCI_MSI_FLAGS_QMASK) >> 1,
907 FLAG(cap, PCI_MSI_FLAGS_ENABLE));
910 is64 = cap & PCI_MSI_FLAGS_64BIT;
911 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
913 printf("\t\tAddress: ");
916 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
917 w = get_conf_word(d, where + PCI_MSI_DATA_64);
921 w = get_conf_word(d, where + PCI_MSI_DATA_32);
922 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
923 printf("%08x Data: %04x\n", t, w);
929 int esr = cap & 0xff;
932 printf("Slot ID: %d slots, First%c, chassis %02x\n",
933 esr & PCI_SID_ESR_NSLOTS,
934 FLAG(esr, PCI_SID_ESR_FIC),
939 show_caps(struct device *d)
941 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
943 int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
947 printf("\tCapabilities: ");
948 if (!config_fetch(d, where, 4))
950 puts("<available only to root>");
953 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
954 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
955 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
956 printf("[%02x] ", where);
959 printf("<chain broken>\n");
965 show_pm(d, where, cap);
968 show_agp(d, where, cap);
971 printf("Vital Product Data\n");
973 case PCI_CAP_ID_SLOTID:
977 show_msi(d, where, cap);
979 case PCI_CAP_ID_PCIX:
983 show_ht(d, where, cap);
986 printf("#%02x [%04x]\n", id, cap);
994 show_htype0(struct device *d)
1002 show_htype1(struct device *d)
1004 u32 io_base = get_conf_byte(d, PCI_IO_BASE);
1005 u32 io_limit = get_conf_byte(d, PCI_IO_LIMIT);
1006 u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
1007 u32 mem_base = get_conf_word(d, PCI_MEMORY_BASE);
1008 u32 mem_limit = get_conf_word(d, PCI_MEMORY_LIMIT);
1009 u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
1010 u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE);
1011 u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT);
1012 u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
1013 word sec_stat = get_conf_word(d, PCI_SEC_STATUS);
1014 word brc = get_conf_word(d, PCI_BRIDGE_CONTROL);
1015 int verb = verbose > 2;
1018 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1019 get_conf_byte(d, PCI_PRIMARY_BUS),
1020 get_conf_byte(d, PCI_SECONDARY_BUS),
1021 get_conf_byte(d, PCI_SUBORDINATE_BUS),
1022 get_conf_byte(d, PCI_SEC_LATENCY_TIMER));
1024 if (io_type != (io_limit & PCI_IO_RANGE_TYPE_MASK) ||
1025 (io_type != PCI_IO_RANGE_TYPE_16 && io_type != PCI_IO_RANGE_TYPE_32))
1026 printf("\t!!! Unknown I/O range types %x/%x\n", io_base, io_limit);
1029 io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
1030 io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
1031 if (io_type == PCI_IO_RANGE_TYPE_32)
1033 io_base |= (get_conf_word(d, PCI_IO_BASE_UPPER16) << 16);
1034 io_limit |= (get_conf_word(d, PCI_IO_LIMIT_UPPER16) << 16);
1036 if (io_base <= io_limit || verb)
1037 printf("\tI/O behind bridge: %08x-%08x\n", io_base, io_limit+0xfff);
1040 if (mem_type != (mem_limit & PCI_MEMORY_RANGE_TYPE_MASK) ||
1042 printf("\t!!! Unknown memory range types %x/%x\n", mem_base, mem_limit);
1045 mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
1046 mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
1047 if (mem_base <= mem_limit || verb)
1048 printf("\tMemory behind bridge: %08x-%08x\n", mem_base, mem_limit + 0xfffff);
1051 if (pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
1052 (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64))
1053 printf("\t!!! Unknown prefetchable memory range types %x/%x\n", pref_base, pref_limit);
1056 pref_base = (pref_base & PCI_PREF_RANGE_MASK) << 16;
1057 pref_limit = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
1058 if (pref_base <= pref_limit || verb)
1060 if (pref_type == PCI_PREF_RANGE_TYPE_32)
1061 printf("\tPrefetchable memory behind bridge: %08x-%08x\n", pref_base, pref_limit + 0xfffff);
1063 printf("\tPrefetchable memory behind bridge: %08x%08x-%08x%08x\n",
1064 get_conf_long(d, PCI_PREF_BASE_UPPER32),
1066 get_conf_long(d, PCI_PREF_LIMIT_UPPER32),
1072 printf("\tSecondary status: 66Mhz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c\n",
1073 FLAG(sec_stat, PCI_STATUS_66MHZ),
1074 FLAG(sec_stat, PCI_STATUS_FAST_BACK),
1075 FLAG(sec_stat, PCI_STATUS_PARITY),
1076 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1077 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1078 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1079 FLAG(sec_stat, PCI_STATUS_SIG_TARGET_ABORT),
1080 FLAG(sec_stat, PCI_STATUS_REC_TARGET_ABORT),
1081 FLAG(sec_stat, PCI_STATUS_REC_MASTER_ABORT),
1082 FLAG(sec_stat, PCI_STATUS_SIG_SYSTEM_ERROR),
1083 FLAG(sec_stat, PCI_STATUS_DETECTED_PARITY));
1088 printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
1089 FLAG(brc, PCI_BRIDGE_CTL_PARITY),
1090 FLAG(brc, PCI_BRIDGE_CTL_SERR),
1091 FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
1092 FLAG(brc, PCI_BRIDGE_CTL_VGA),
1093 FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
1094 FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
1095 FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
1101 show_htype2(struct device *d)
1104 word cmd = get_conf_word(d, PCI_COMMAND);
1105 word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
1106 word exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
1107 int verb = verbose > 2;
1110 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1111 get_conf_byte(d, PCI_CB_PRIMARY_BUS),
1112 get_conf_byte(d, PCI_CB_CARD_BUS),
1113 get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
1114 get_conf_byte(d, PCI_CB_LATENCY_TIMER));
1118 u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
1119 u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
1120 if (limit > base || verb)
1121 printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
1122 (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
1123 (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
1128 u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
1129 u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
1130 if (!(base & PCI_IO_RANGE_TYPE_32))
1135 base &= PCI_CB_IO_RANGE_MASK;
1136 limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
1137 if (base <= limit || verb)
1138 printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
1139 (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
1142 if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
1143 printf("\tSecondary status: SERR\n");
1145 printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
1146 FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
1147 FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
1148 FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
1149 FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
1150 FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
1151 FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
1152 FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
1153 FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
1155 printf("\t16-bit legacy interface ports at %04x\n", exca);
1159 show_verbose(struct device *d)
1161 struct pci_dev *p = d->dev;
1162 word status = get_conf_word(d, PCI_STATUS);
1163 word cmd = get_conf_word(d, PCI_COMMAND);
1164 word class = get_conf_word(d, PCI_CLASS_DEVICE);
1165 byte bist = get_conf_byte(d, PCI_BIST);
1166 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1167 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
1168 byte cache_line = get_conf_byte(d, PCI_CACHE_LINE_SIZE);
1169 byte max_lat, min_gnt;
1170 byte int_pin = get_conf_byte(d, PCI_INTERRUPT_PIN);
1171 unsigned int irq = p->irq;
1172 word subsys_v, subsys_d;
1173 char ssnamebuf[256];
1179 case PCI_HEADER_TYPE_NORMAL:
1180 if (class == PCI_CLASS_BRIDGE_PCI)
1181 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1182 max_lat = get_conf_byte(d, PCI_MAX_LAT);
1183 min_gnt = get_conf_byte(d, PCI_MIN_GNT);
1184 subsys_v = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1185 subsys_d = get_conf_word(d, PCI_SUBSYSTEM_ID);
1187 case PCI_HEADER_TYPE_BRIDGE:
1188 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1189 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1190 irq = int_pin = min_gnt = max_lat = 0;
1191 subsys_v = subsys_d = 0;
1193 case PCI_HEADER_TYPE_CARDBUS:
1194 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1195 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1196 min_gnt = max_lat = 0;
1197 subsys_v = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1198 subsys_d = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1201 printf("\t!!! Unknown header type %02x\n", htype);
1205 if (subsys_v && subsys_v != 0xffff)
1206 printf("\tSubsystem: %s\n",
1207 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1208 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1209 p->vendor_id, p->device_id, subsys_v, subsys_d));
1213 printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c\n",
1214 FLAG(cmd, PCI_COMMAND_IO),
1215 FLAG(cmd, PCI_COMMAND_MEMORY),
1216 FLAG(cmd, PCI_COMMAND_MASTER),
1217 FLAG(cmd, PCI_COMMAND_SPECIAL),
1218 FLAG(cmd, PCI_COMMAND_INVALIDATE),
1219 FLAG(cmd, PCI_COMMAND_VGA_PALETTE),
1220 FLAG(cmd, PCI_COMMAND_PARITY),
1221 FLAG(cmd, PCI_COMMAND_WAIT),
1222 FLAG(cmd, PCI_COMMAND_SERR),
1223 FLAG(cmd, PCI_COMMAND_FAST_BACK));
1224 printf("\tStatus: Cap%c 66Mhz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c\n",
1225 FLAG(status, PCI_STATUS_CAP_LIST),
1226 FLAG(status, PCI_STATUS_66MHZ),
1227 FLAG(status, PCI_STATUS_UDF),
1228 FLAG(status, PCI_STATUS_FAST_BACK),
1229 FLAG(status, PCI_STATUS_PARITY),
1230 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1231 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1232 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1233 FLAG(status, PCI_STATUS_SIG_TARGET_ABORT),
1234 FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
1235 FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
1236 FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
1237 FLAG(status, PCI_STATUS_DETECTED_PARITY));
1238 if (cmd & PCI_COMMAND_MASTER)
1240 printf("\tLatency: %d", latency);
1241 if (min_gnt || max_lat)
1245 printf("%dns min", min_gnt*250);
1246 if (min_gnt && max_lat)
1249 printf("%dns max", max_lat*250);
1253 printf(", Cache Line Size %02x", cache_line);
1257 printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n",
1258 (int_pin ? 'A' + int_pin - 1 : '?'), irq);
1262 printf("\tFlags: ");
1263 if (cmd & PCI_COMMAND_MASTER)
1264 printf("bus master, ");
1265 if (cmd & PCI_COMMAND_VGA_PALETTE)
1266 printf("VGA palette snoop, ");
1267 if (cmd & PCI_COMMAND_WAIT)
1268 printf("stepping, ");
1269 if (cmd & PCI_COMMAND_FAST_BACK)
1270 printf("fast Back2Back, ");
1271 if (status & PCI_STATUS_66MHZ)
1273 if (status & PCI_STATUS_UDF)
1274 printf("user-definable features, ");
1276 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1277 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1278 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??");
1279 if (cmd & PCI_COMMAND_MASTER)
1280 printf(", latency %d", latency);
1282 printf(", IRQ " PCIIRQ_FMT, irq);
1286 if (bist & PCI_BIST_CAPABLE)
1288 if (bist & PCI_BIST_START)
1289 printf("\tBIST is running\n");
1291 printf("\tBIST result: %02x\n", bist & PCI_BIST_CODE_MASK);
1296 case PCI_HEADER_TYPE_NORMAL:
1299 case PCI_HEADER_TYPE_BRIDGE:
1302 case PCI_HEADER_TYPE_CARDBUS:
1309 show_hex_dump(struct device *d)
1313 for(i=0; i<d->config_cnt; i++)
1317 printf(" %02x", get_conf_byte(d, i));
1324 show_machine(struct device *d)
1326 struct pci_dev *p = d->dev;
1328 word sv_id=0, sd_id=0;
1329 char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
1331 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
1333 case PCI_HEADER_TYPE_NORMAL:
1334 sv_id = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1335 sd_id = get_conf_word(d, PCI_SUBSYSTEM_ID);
1337 case PCI_HEADER_TYPE_CARDBUS:
1338 sv_id = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1339 sd_id = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1345 printf("Device:\t");
1348 printf("Class:\t%s\n",
1349 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0));
1350 printf("Vendor:\t%s\n",
1351 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, 0, 0));
1352 printf("Device:\t%s\n",
1353 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, 0, 0));
1354 if (sv_id && sv_id != 0xffff)
1356 printf("SVendor:\t%s\n",
1357 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, sv_id, sd_id));
1358 printf("SDevice:\t%s\n",
1359 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1361 if (c = get_conf_byte(d, PCI_REVISION_ID))
1362 printf("Rev:\t%02x\n", c);
1363 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1364 printf("ProgIf:\t%02x\n", c);
1369 printf(" \"%s\" \"%s\" \"%s\"",
1370 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS,
1371 get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0),
1372 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR,
1373 p->vendor_id, p->device_id, 0, 0),
1374 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE,
1375 p->vendor_id, p->device_id, 0, 0));
1376 if (c = get_conf_byte(d, PCI_REVISION_ID))
1377 printf(" -r%02x", c);
1378 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1379 printf(" -p%02x", c);
1380 if (sv_id && sv_id != 0xffff)
1381 printf(" \"%s\" \"%s\"",
1382 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, sv_id, sd_id),
1383 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1385 printf(" \"\" \"\"");
1391 show_device(struct device *d)
1393 if (machine_readable)
1401 if (verbose || show_hex)
1410 for(d=first_dev; d; d=d->next)
1417 struct bridge *chain; /* Single-linked list of bridges */
1418 struct bridge *next, *child; /* Tree of bridges */
1419 struct bus *first_bus; /* List of busses connected to this bridge */
1420 unsigned int domain;
1421 unsigned int primary, secondary, subordinate; /* Bus numbers */
1422 struct device *br_dev;
1426 unsigned int domain;
1427 unsigned int number;
1428 struct bus *sibling;
1429 struct device *first_dev, **last_dev;
1432 static struct bridge host_bridge = { NULL, NULL, NULL, NULL, 0, ~0, 0, ~0, NULL };
1435 find_bus(struct bridge *b, unsigned int domain, unsigned int n)
1439 for(bus=b->first_bus; bus; bus=bus->sibling)
1440 if (bus->domain == domain && bus->number == n)
1446 new_bus(struct bridge *b, unsigned int domain, unsigned int n)
1448 struct bus *bus = xmalloc(sizeof(struct bus));
1450 bus = xmalloc(sizeof(struct bus));
1451 bus->domain = domain;
1453 bus->sibling = b->first_bus;
1454 bus->first_dev = NULL;
1455 bus->last_dev = &bus->first_dev;
1461 insert_dev(struct device *d, struct bridge *b)
1463 struct pci_dev *p = d->dev;
1466 if (! (bus = find_bus(b, p->domain, p->bus)))
1469 for(c=b->child; c; c=c->next)
1470 if (c->domain == p->domain && c->secondary <= p->bus && p->bus <= c->subordinate)
1475 bus = new_bus(b, p->domain, p->bus);
1477 /* Simple insertion at the end _does_ guarantee the correct order as the
1478 * original device list was sorted by (domain, bus, devfn) lexicographically
1479 * and all devices on the new list have the same bus number.
1482 bus->last_dev = &d->next;
1489 struct device *d, *d2;
1490 struct bridge **last_br, *b;
1492 /* Build list of bridges */
1494 last_br = &host_bridge.chain;
1495 for(d=first_dev; d; d=d->next)
1497 word class = get_conf_word(d, PCI_CLASS_DEVICE);
1498 byte ht = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1499 if (class == PCI_CLASS_BRIDGE_PCI &&
1500 (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS))
1502 b = xmalloc(sizeof(struct bridge));
1503 b->domain = d->dev->domain;
1504 if (ht == PCI_HEADER_TYPE_BRIDGE)
1506 b->primary = get_conf_byte(d, PCI_CB_PRIMARY_BUS);
1507 b->secondary = get_conf_byte(d, PCI_CB_CARD_BUS);
1508 b->subordinate = get_conf_byte(d, PCI_CB_SUBORDINATE_BUS);
1512 b->primary = get_conf_byte(d, PCI_PRIMARY_BUS);
1513 b->secondary = get_conf_byte(d, PCI_SECONDARY_BUS);
1514 b->subordinate = get_conf_byte(d, PCI_SUBORDINATE_BUS);
1517 last_br = &b->chain;
1518 b->next = b->child = NULL;
1519 b->first_bus = NULL;
1525 /* Create a bridge tree */
1527 for(b=&host_bridge; b; b=b->chain)
1529 struct bridge *c, *best;
1531 for(c=&host_bridge; c; c=c->chain)
1532 if (c != b && (c == &host_bridge || b->domain == c->domain) &&
1533 b->primary >= c->secondary && b->primary <= c->subordinate &&
1534 (!best || best->subordinate - best->primary > c->subordinate - c->primary))
1538 b->next = best->child;
1543 /* Insert secondary bus for each bridge */
1545 for(b=&host_bridge; b; b=b->chain)
1546 if (!find_bus(b, b->domain, b->secondary))
1547 new_bus(b, b->domain, b->secondary);
1549 /* Create bus structs and link devices */
1551 for(d=first_dev; d;)
1554 insert_dev(d, &host_bridge);
1560 print_it(byte *line, byte *p)
1564 fputs(line, stdout);
1565 for(p=line; *p; p++)
1566 if (*p == '+' || *p == '|')
1572 static void show_tree_bridge(struct bridge *, byte *, byte *);
1575 show_tree_dev(struct device *d, byte *line, byte *p)
1577 struct pci_dev *q = d->dev;
1581 p += sprintf(p, "%02x.%x", q->dev, q->func);
1582 for(b=&host_bridge; b; b=b->chain)
1585 if (b->secondary == b->subordinate)
1586 p += sprintf(p, "-[%04x:%02x]-", b->domain, b->secondary);
1588 p += sprintf(p, "-[%04x:%02x-%02x]-", b->domain, b->secondary, b->subordinate);
1589 show_tree_bridge(b, line, p);
1593 p += sprintf(p, " %s",
1594 pci_lookup_name(pacc, namebuf, sizeof(namebuf),
1595 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1596 q->vendor_id, q->device_id, 0, 0));
1601 show_tree_bus(struct bus *b, byte *line, byte *p)
1605 else if (!b->first_dev->next)
1609 show_tree_dev(b->first_dev, line, p);
1613 struct device *d = b->first_dev;
1618 show_tree_dev(d, line, p+2);
1623 show_tree_dev(d, line, p+2);
1628 show_tree_bridge(struct bridge *b, byte *line, byte *p)
1631 if (!b->first_bus->sibling)
1633 if (b == &host_bridge)
1634 p += sprintf(p, "[%04x:%02x]-", b->domain, b->first_bus->number);
1635 show_tree_bus(b->first_bus, line, p);
1639 struct bus *u = b->first_bus;
1644 k = p + sprintf(p, "+-[%04x:%02x]-", u->domain, u->number);
1645 show_tree_bus(u, line, k);
1648 k = p + sprintf(p, "\\-[%04x:%02x]-", u->domain, u->number);
1649 show_tree_bus(u, line, k);
1659 show_tree_bridge(&host_bridge, line, line);
1662 /* Bus mapping mode */
1665 struct bus_bridge *next;
1666 byte this, dev, func, first, last, bug;
1672 struct bus_bridge *bridges, *via;
1675 static struct bus_info *bus_info;
1678 map_bridge(struct bus_info *bi, struct device *d, int np, int ns, int nl)
1680 struct bus_bridge *b = xmalloc(sizeof(struct bus_bridge));
1681 struct pci_dev *p = d->dev;
1683 b->next = bi->bridges;
1685 b->this = get_conf_byte(d, np);
1688 b->first = get_conf_byte(d, ns);
1689 b->last = get_conf_byte(d, nl);
1690 printf("## %02x.%02x:%d is a bridge from %02x to %02x-%02x\n",
1691 p->bus, p->dev, p->func, b->this, b->first, b->last);
1692 if (b->this != p->bus)
1693 printf("!!! Bridge points to invalid primary bus.\n");
1694 if (b->first > b->last)
1696 printf("!!! Bridge points to invalid bus range.\n");
1705 int verbose = pacc->debugging;
1706 struct bus_info *bi = bus_info + bus;
1710 printf("Mapping bus %02x\n", bus);
1711 for(dev = 0; dev < 32; dev++)
1712 if (filter.slot < 0 || filter.slot == dev)
1715 for(func = 0; func < func_limit; func++)
1716 if (filter.func < 0 || filter.func == func)
1718 /* XXX: Bus mapping supports only domain 0 */
1719 struct pci_dev *p = pci_get_dev(pacc, 0, bus, dev, func);
1720 u16 vendor = pci_read_word(p, PCI_VENDOR_ID);
1721 if (vendor && vendor != 0xffff)
1723 if (!func && (pci_read_byte(p, PCI_HEADER_TYPE) & 0x80))
1726 printf("Discovered device %02x:%02x.%d\n", bus, dev, func);
1728 if (d = scan_device(p))
1731 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
1733 case PCI_HEADER_TYPE_BRIDGE:
1734 map_bridge(bi, d, PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS);
1736 case PCI_HEADER_TYPE_CARDBUS:
1737 map_bridge(bi, d, PCI_CB_PRIMARY_BUS, PCI_CB_CARD_BUS, PCI_CB_SUBORDINATE_BUS);
1743 printf("But it was filtered out.\n");
1751 do_map_bridges(int bus, int min, int max)
1753 struct bus_info *bi = bus_info + bus;
1754 struct bus_bridge *b;
1757 for(b=bi->bridges; b; b=b->next)
1759 if (bus_info[b->first].guestbook)
1761 else if (b->first < min || b->last > max)
1765 bus_info[b->first].via = b;
1766 do_map_bridges(b->first, b->first, b->last);
1776 printf("\nSummary of buses:\n\n");
1777 for(i=0; i<256; i++)
1778 if (bus_info[i].exists && !bus_info[i].guestbook)
1779 do_map_bridges(i, 0, 255);
1780 for(i=0; i<256; i++)
1782 struct bus_info *bi = bus_info + i;
1783 struct bus_bridge *b = bi->via;
1787 printf("%02x: ", i);
1789 printf("Entered via %02x:%02x.%d\n", b->this, b->dev, b->func);
1791 printf("Primary host bus\n");
1793 printf("Secondary host bus (?)\n");
1795 for(b=bi->bridges; b; b=b->next)
1797 printf("\t%02x.%d Bridge to %02x-%02x", b->dev, b->func, b->first, b->last);
1801 printf(" <overlap bug>");
1804 printf(" <crossing bug>");
1815 if (pacc->method == PCI_ACCESS_PROC_BUS_PCI ||
1816 pacc->method == PCI_ACCESS_DUMP)
1817 printf("WARNING: Bus mapping can be reliable only with direct hardware access enabled.\n\n");
1818 else if (!check_root())
1819 die("Only root can map the bus.");
1820 bus_info = xmalloc(sizeof(struct bus_info) * 256);
1821 bzero(bus_info, sizeof(struct bus_info) * 256);
1822 if (filter.bus >= 0)
1823 do_map_bus(filter.bus);
1827 for(bus=0; bus<256; bus++)
1836 main(int argc, char **argv)
1841 if (argc == 2 && !strcmp(argv[1], "--version"))
1843 puts("lspci version " PCIUTILS_VERSION);
1849 pci_filter_init(pacc, &filter);
1851 while ((i = getopt(argc, argv, options)) != -1)
1855 pacc->numeric_ids = 1;
1861 pacc->buscentric = 1;
1862 buscentric_view = 1;
1865 if (msg = pci_filter_parse_slot(&filter, optarg))
1869 if (msg = pci_filter_parse_id(&filter, optarg))
1879 pacc->id_file_name = optarg;
1888 if (parse_generic_option(i, pacc, optarg))
1891 fprintf(stderr, help_msg, pacc->id_file_name);