2 * The PCI Utilities -- List All PCI Devices
4 * Copyright (c) 1997--2004 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
19 static int verbose; /* Show detailed information */
20 static int buscentric_view; /* Show bus addresses/IRQ's instead of CPU-visible ones */
21 static int show_hex; /* Show contents of config space as hexadecimal numbers */
22 static struct pci_filter filter; /* Device filter */
23 static int show_tree; /* Show bus tree */
24 static int machine_readable; /* Generate machine-readable output */
25 static int map_mode; /* Bus mapping mode enabled */
27 static char options[] = "nvbxs:d:ti:mgM" GENERIC_OPTIONS ;
29 static char help_msg[] = "\
30 Usage: lspci [<switches>]\n\
33 -n\t\tShow numeric ID's\n\
34 -b\t\tBus-centric view (PCI addresses and IRQ's instead of those seen by the CPU)\n\
35 -x\t\tShow hex-dump of the standard portion of config space\n\
36 -xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n\
37 -s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n\
38 -d [<vendor>]:[<device>]\tShow only selected devices\n\
39 -t\t\tShow bus tree\n\
40 -m\t\tProduce machine-readable output\n\
41 -i <file>\tUse specified ID database instead of %s\n\
42 -M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
46 /* Communication with libpci */
48 static struct pci_access *pacc;
51 * If we aren't being compiled by GCC, use malloc() instead of alloca().
52 * This increases our memory footprint, but only slightly since we don't
60 /* Our view of the PCI bus */
65 unsigned int config_cnt;
69 static struct device *first_dev;
71 static struct device *
72 scan_device(struct pci_dev *p)
74 int how_much = (show_hex > 2) ? 256 : 64;
77 if (!pci_filter_match(&filter, p))
79 d = xmalloc(sizeof(struct device));
82 if (!pci_read_block(p, 0, d->config, how_much))
83 die("Unable to read %d bytes of configuration space.", how_much);
84 if (how_much < 128 && (d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
86 /* For cardbus bridges, we need to fetch 64 bytes more to get the full standard header... */
87 if (!pci_read_block(p, 64, d->config+64, 64))
88 die("Unable to read cardbus bridge extension data.");
91 d->config_cnt = how_much;
92 pci_setup_cache(p, d->config, d->config_cnt);
93 pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
104 for(p=pacc->devices; p; p=p->next)
105 if (d = scan_device(p))
115 static int is_root = -1;
118 is_root = !geteuid();
123 config_fetch(struct device *d, unsigned int pos, unsigned int len)
125 if (pos + len < d->config_cnt)
127 if (pacc->method != PCI_ACCESS_DUMP && !check_root())
129 return pci_read_block(d->dev, pos, d->config + pos, len);
132 /* Config space accesses */
135 get_conf_byte(struct device *d, unsigned int pos)
137 return d->config[pos];
141 get_conf_word(struct device *d, unsigned int pos)
143 return d->config[pos] | (d->config[pos+1] << 8);
147 get_conf_long(struct device *d, unsigned int pos)
149 return d->config[pos] |
150 (d->config[pos+1] << 8) |
151 (d->config[pos+2] << 16) |
152 (d->config[pos+3] << 24);
158 compare_them(const void *A, const void *B)
160 const struct pci_dev *a = (*(const struct device **)A)->dev;
161 const struct pci_dev *b = (*(const struct device **)B)->dev;
163 if (a->domain < b->domain)
165 if (a->domain > b->domain)
175 if (a->func < b->func)
177 if (a->func > b->func)
185 struct device **index, **h, **last_dev;
190 for(d=first_dev; d; d=d->next)
192 h = index = alloca(sizeof(struct device *) * cnt);
193 for(d=first_dev; d; d=d->next)
195 qsort(index, cnt, sizeof(struct device *), compare_them);
196 last_dev = &first_dev;
201 last_dev = &(*h)->next;
209 #define FLAG(x,y) ((x & y) ? '+' : '-')
212 show_slot_name(struct device *d)
214 struct pci_dev *p = d->dev;
217 printf("%04x:", p->domain);
218 printf("%02x:%02x.%d", p->bus, p->dev, p->func);
222 show_terse(struct device *d)
225 struct pci_dev *p = d->dev;
226 byte classbuf[128], devbuf[128];
230 pci_lookup_name(pacc, classbuf, sizeof(classbuf),
232 get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0),
233 pci_lookup_name(pacc, devbuf, sizeof(devbuf),
234 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
235 p->vendor_id, p->device_id, 0, 0));
236 if (c = get_conf_byte(d, PCI_REVISION_ID))
237 printf(" (rev %02x)", c);
241 c = get_conf_byte(d, PCI_CLASS_PROG);
242 x = pci_lookup_name(pacc, devbuf, sizeof(devbuf),
244 get_conf_word(d, PCI_CLASS_DEVICE), c, 0, 0);
247 printf(" (prog-if %02x", c);
257 show_size(pciaddr_t x)
263 printf("%d", (int) x);
264 else if (x < 1048576)
265 printf("%dK", (int)(x / 1024));
266 else if (x < 0x80000000)
267 printf("%dM", (int)(x / 1048576));
269 printf(PCIADDR_T_FMT, x);
274 show_bases(struct device *d, int cnt)
276 struct pci_dev *p = d->dev;
277 word cmd = get_conf_word(d, PCI_COMMAND);
282 pciaddr_t pos = p->base_addr[i];
283 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
284 u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
285 if (flg == 0xffffffff)
287 if (!pos && !flg && !len)
290 printf("\tRegion %d: ", i);
293 if (pos && !flg) /* Reported by the OS, but not by the device */
295 printf("[virtual] ");
298 if (flg & PCI_BASE_ADDRESS_SPACE_IO)
300 pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
301 printf("I/O ports at ");
303 printf(PCIADDR_PORT_FMT, a);
304 else if (flg & PCI_BASE_ADDRESS_IO_MASK)
307 printf("<unassigned>");
308 if (!(cmd & PCI_COMMAND_IO))
309 printf(" [disabled]");
313 int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
314 pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
318 printf("Memory at ");
319 if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
323 printf("<invalid-64bit-slot>");
329 z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
333 printf("%08x" PCIADDR_T_FMT, z, a);
335 printf("<unassigned>");
343 printf(PCIADDR_T_FMT, a);
345 printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
347 printf(" (%s, %sprefetchable)",
348 (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
349 (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
350 (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
351 (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
352 if (!(cmd & PCI_COMMAND_MEMORY))
353 printf(" [disabled]");
361 show_pm(struct device *d, int where, int cap)
364 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
366 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
369 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
370 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
371 FLAG(cap, PCI_PM_CAP_DSI),
372 FLAG(cap, PCI_PM_CAP_D1),
373 FLAG(cap, PCI_PM_CAP_D2),
374 pm_aux_current[(cap >> 6) & 7],
375 FLAG(cap, PCI_PM_CAP_PME_D0),
376 FLAG(cap, PCI_PM_CAP_PME_D1),
377 FLAG(cap, PCI_PM_CAP_PME_D2),
378 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
379 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
380 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
382 t = get_conf_word(d, where + PCI_PM_CTRL);
383 printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
384 t & PCI_PM_CTRL_STATE_MASK,
385 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
386 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
387 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
388 FLAG(t, PCI_PM_CTRL_PME_STATUS));
389 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
391 printf("\t\tBridge: PM%c B3%c\n",
392 FLAG(t, PCI_PM_BPCC_ENABLE),
393 FLAG(~t, PCI_PM_PPB_B2_B3));
397 format_agp_rate(int rate, char *buf, int agp3)
408 *c++ = '0' + (1 << (i + 2*agp3));
413 strcpy(buf, "<none>");
417 show_agp(struct device *d, int where, int cap)
424 ver = (cap >> 4) & 0x0f;
426 printf("AGP version %x.%x\n", ver, rev);
429 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
431 t = get_conf_long(d, where + PCI_AGP_STATUS);
432 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
434 format_agp_rate(t & 7, rate, agp3);
435 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
436 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
437 FLAG(t, PCI_AGP_STATUS_ISOCH),
438 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
439 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
440 FLAG(t, PCI_AGP_STATUS_SBA),
441 FLAG(t, PCI_AGP_STATUS_ITA_COH),
442 FLAG(t, PCI_AGP_STATUS_GART64),
443 FLAG(t, PCI_AGP_STATUS_HTRANS),
444 FLAG(t, PCI_AGP_STATUS_64BIT),
445 FLAG(t, PCI_AGP_STATUS_FW),
446 FLAG(t, PCI_AGP_STATUS_AGP3),
448 t = get_conf_long(d, where + PCI_AGP_COMMAND);
449 format_agp_rate(t & 7, rate, agp3);
450 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
451 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
452 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
453 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
454 FLAG(t, PCI_AGP_COMMAND_SBA),
455 FLAG(t, PCI_AGP_COMMAND_AGP),
456 FLAG(t, PCI_AGP_COMMAND_GART64),
457 FLAG(t, PCI_AGP_COMMAND_64BIT),
458 FLAG(t, PCI_AGP_COMMAND_FW),
463 show_pcix_nobridge(struct device *d, int where)
468 printf("PCI-X non-bridge device.\n");
473 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
476 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
477 status = get_conf_long(d, where + PCI_PCIX_STATUS);
478 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
479 FLAG(command, PCI_PCIX_COMMAND_DPERE),
480 FLAG(command, PCI_PCIX_COMMAND_ERO),
481 ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U),
482 ((command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U));
483 printf("\t\tStatus: Bus=%u Dev=%u Func=%u 64bit%c 133MHz%c SCD%c USC%c, DC=%s, DMMRBC=%u, DMOST=%u, DMCRS=%u, RSCEM%c\n",
484 ((status >> 8) & 0xffU), // bus
485 ((status >> 3) & 0x1fU), // dev
486 (status & PCI_PCIX_STATUS_FUNCTION), // function
487 FLAG(status, PCI_PCIX_STATUS_64BIT),
488 FLAG(status, PCI_PCIX_STATUS_133MHZ),
489 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
490 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
491 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
492 ((status >> 21) & 3U),
493 ((status >> 23) & 7U),
494 ((status >> 26) & 7U),
495 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS));
499 show_pcix_bridge(struct device *d, int where)
503 u32 status, upstcr, downstcr;
505 printf("PCI-X bridge device.\n");
510 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
513 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
514 printf("\t\tSecondary Status: 64bit%c, 133MHz%c, SCD%c, USC%c, SCO%c, SRD%c Freq=%d\n",
515 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
516 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
517 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
518 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
519 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
520 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
521 ((secstatus >> 6) & 7));
522 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
523 printf("\t\tStatus: Bus=%u Dev=%u Func=%u 64bit%c 133MHz%c SCD%c USC%c, SCO%c, SRD%c\n",
524 ((status >> 8) & 0xff), // bus
525 ((status >> 3) & 0x1f), // dev
526 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION), // function
527 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
528 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
529 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
530 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
531 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
532 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
533 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
534 printf("\t\t: Upstream: Capacity=%u, Commitment Limit=%u\n",
535 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
536 (upstcr >> 16) & 0xffff);
537 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
538 printf("\t\t: Downstream: Capacity=%u, Commitment Limit=%u\n",
539 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
540 (downstcr >> 16) & 0xffff);
544 show_pcix(struct device *d, int where)
546 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
548 case PCI_HEADER_TYPE_NORMAL:
549 show_pcix_nobridge(d, where);
551 case PCI_HEADER_TYPE_BRIDGE:
552 show_pcix_bridge(d, where);
558 ht_link_width(unsigned width)
560 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
561 return widths[width];
565 ht_link_freq(unsigned freq)
567 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
568 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
573 show_ht_pri(struct device *d, int where, int cmd)
575 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
576 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
578 printf("HyperTransport: Slave or Primary Interface\n");
582 printf("\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n",
583 (cmd & PCI_HT_PRI_CMD_BUID),
584 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
585 FLAG(cmd, PCI_HT_PRI_CMD_MH),
586 FLAG(cmd, PCI_HT_PRI_CMD_DD),
587 FLAG(cmd, PCI_HT_PRI_CMD_DUL));
588 config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0);
589 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
590 printf("\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n",
591 FLAG(lctr0, PCI_HT_LCTR_CFLE),
592 FLAG(lctr0, PCI_HT_LCTR_CST),
593 FLAG(lctr0, PCI_HT_LCTR_CFE),
594 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
595 FLAG(lctr0, PCI_HT_LCTR_INIT),
596 FLAG(lctr0, PCI_HT_LCTR_EOC),
597 FLAG(lctr0, PCI_HT_LCTR_TXO),
598 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
599 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
600 FLAG(lctr0, PCI_HT_LCTR_LSEN),
601 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
602 FLAG(lctr0, PCI_HT_LCTR_64B));
603 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
604 printf("\t\tLink Config 0: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
605 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
606 FLAG(lcnf0, PCI_HT_LCNF_DFI),
607 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
608 FLAG(lcnf0, PCI_HT_LCNF_DFO),
609 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
610 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
611 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
612 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
613 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
614 printf("\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n",
615 FLAG(lctr1, PCI_HT_LCTR_CFLE),
616 FLAG(lctr1, PCI_HT_LCTR_CST),
617 FLAG(lctr1, PCI_HT_LCTR_CFE),
618 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
619 FLAG(lctr1, PCI_HT_LCTR_INIT),
620 FLAG(lctr1, PCI_HT_LCTR_EOC),
621 FLAG(lctr1, PCI_HT_LCTR_TXO),
622 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
623 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
624 FLAG(lctr1, PCI_HT_LCTR_LSEN),
625 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
626 FLAG(lctr1, PCI_HT_LCTR_64B));
627 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
628 printf("\t\tLink Config 1: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
629 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
630 FLAG(lcnf1, PCI_HT_LCNF_DFI),
631 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
632 FLAG(lcnf1, PCI_HT_LCNF_DFO),
633 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
634 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
635 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
636 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
637 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
638 printf("\t\tRevision ID: %u.%02u\n",
639 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
640 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
641 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
642 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
643 FLAG(lfrer0, PCI_HT_LFRER_PROT),
644 FLAG(lfrer0, PCI_HT_LFRER_OV),
645 FLAG(lfrer0, PCI_HT_LFRER_EOC),
646 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
647 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
648 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
649 FLAG(lfcap0, PCI_HT_LFCAP_200),
650 FLAG(lfcap0, PCI_HT_LFCAP_300),
651 FLAG(lfcap0, PCI_HT_LFCAP_400),
652 FLAG(lfcap0, PCI_HT_LFCAP_500),
653 FLAG(lfcap0, PCI_HT_LFCAP_600),
654 FLAG(lfcap0, PCI_HT_LFCAP_800),
655 FLAG(lfcap0, PCI_HT_LFCAP_1000),
656 FLAG(lfcap0, PCI_HT_LFCAP_1200),
657 FLAG(lfcap0, PCI_HT_LFCAP_1400),
658 FLAG(lfcap0, PCI_HT_LFCAP_1600),
659 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
660 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
661 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
662 FLAG(ftr, PCI_HT_FTR_ISOCFC),
663 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
664 FLAG(ftr, PCI_HT_FTR_CRCTM),
665 FLAG(ftr, PCI_HT_FTR_ECTLT),
666 FLAG(ftr, PCI_HT_FTR_64BA),
667 FLAG(ftr, PCI_HT_FTR_UIDRD));
668 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
669 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
670 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
671 FLAG(lfrer1, PCI_HT_LFRER_PROT),
672 FLAG(lfrer1, PCI_HT_LFRER_OV),
673 FLAG(lfrer1, PCI_HT_LFRER_EOC),
674 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
675 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
676 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
677 FLAG(lfcap1, PCI_HT_LFCAP_200),
678 FLAG(lfcap1, PCI_HT_LFCAP_300),
679 FLAG(lfcap1, PCI_HT_LFCAP_400),
680 FLAG(lfcap1, PCI_HT_LFCAP_500),
681 FLAG(lfcap1, PCI_HT_LFCAP_600),
682 FLAG(lfcap1, PCI_HT_LFCAP_800),
683 FLAG(lfcap1, PCI_HT_LFCAP_1000),
684 FLAG(lfcap1, PCI_HT_LFCAP_1200),
685 FLAG(lfcap1, PCI_HT_LFCAP_1400),
686 FLAG(lfcap1, PCI_HT_LFCAP_1600),
687 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
688 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
689 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
690 FLAG(eh, PCI_HT_EH_PFLE),
691 FLAG(eh, PCI_HT_EH_OFLE),
692 FLAG(eh, PCI_HT_EH_PFE),
693 FLAG(eh, PCI_HT_EH_OFE),
694 FLAG(eh, PCI_HT_EH_EOCFE),
695 FLAG(eh, PCI_HT_EH_RFE),
696 FLAG(eh, PCI_HT_EH_CRCFE),
697 FLAG(eh, PCI_HT_EH_SERRFE),
698 FLAG(eh, PCI_HT_EH_CF),
699 FLAG(eh, PCI_HT_EH_RE),
700 FLAG(eh, PCI_HT_EH_PNFE),
701 FLAG(eh, PCI_HT_EH_ONFE),
702 FLAG(eh, PCI_HT_EH_EOCNFE),
703 FLAG(eh, PCI_HT_EH_RNFE),
704 FLAG(eh, PCI_HT_EH_CRCNFE),
705 FLAG(eh, PCI_HT_EH_SERRNFE));
706 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
707 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
708 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
709 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
710 printf("\t\tBus Number: %02x\n", bn);
714 show_ht_sec(struct device *d, int where, int cmd)
716 u16 lctr, lcnf, ftr, eh;
717 u8 rid, lfrer, lfcap, mbu, mlu;
719 printf("HyperTransport: Host or Secondary Interface\n");
723 printf("\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n",
724 FLAG(cmd, PCI_HT_SEC_CMD_WR),
725 FLAG(cmd, PCI_HT_SEC_CMD_DE),
726 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
727 FLAG(cmd, PCI_HT_SEC_CMD_CS),
728 FLAG(cmd, PCI_HT_SEC_CMD_HH),
729 FLAG(cmd, PCI_HT_SEC_CMD_AS),
730 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
731 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
732 config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR);
733 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
734 printf("\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n",
735 FLAG(lctr, PCI_HT_LCTR_CFLE),
736 FLAG(lctr, PCI_HT_LCTR_CST),
737 FLAG(lctr, PCI_HT_LCTR_CFE),
738 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
739 FLAG(lctr, PCI_HT_LCTR_INIT),
740 FLAG(lctr, PCI_HT_LCTR_EOC),
741 FLAG(lctr, PCI_HT_LCTR_TXO),
742 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
743 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
744 FLAG(lctr, PCI_HT_LCTR_LSEN),
745 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
746 FLAG(lctr, PCI_HT_LCTR_64B));
747 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
748 printf("\t\tLink Config: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
749 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
750 FLAG(lcnf, PCI_HT_LCNF_DFI),
751 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
752 FLAG(lcnf, PCI_HT_LCNF_DFO),
753 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
754 FLAG(lcnf, PCI_HT_LCNF_DFIE),
755 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
756 FLAG(lcnf, PCI_HT_LCNF_DFOE));
757 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
758 printf("\t\tRevision ID: %u.%02u\n",
759 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
760 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
761 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
762 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
763 FLAG(lfrer, PCI_HT_LFRER_PROT),
764 FLAG(lfrer, PCI_HT_LFRER_OV),
765 FLAG(lfrer, PCI_HT_LFRER_EOC),
766 FLAG(lfrer, PCI_HT_LFRER_CTLT));
767 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
768 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
769 FLAG(lfcap, PCI_HT_LFCAP_200),
770 FLAG(lfcap, PCI_HT_LFCAP_300),
771 FLAG(lfcap, PCI_HT_LFCAP_400),
772 FLAG(lfcap, PCI_HT_LFCAP_500),
773 FLAG(lfcap, PCI_HT_LFCAP_600),
774 FLAG(lfcap, PCI_HT_LFCAP_800),
775 FLAG(lfcap, PCI_HT_LFCAP_1000),
776 FLAG(lfcap, PCI_HT_LFCAP_1200),
777 FLAG(lfcap, PCI_HT_LFCAP_1400),
778 FLAG(lfcap, PCI_HT_LFCAP_1600),
779 FLAG(lfcap, PCI_HT_LFCAP_VEND));
780 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
781 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
782 FLAG(ftr, PCI_HT_FTR_ISOCFC),
783 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
784 FLAG(ftr, PCI_HT_FTR_CRCTM),
785 FLAG(ftr, PCI_HT_FTR_ECTLT),
786 FLAG(ftr, PCI_HT_FTR_64BA),
787 FLAG(ftr, PCI_HT_FTR_UIDRD),
788 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
789 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
790 if (ftr & PCI_HT_SEC_FTR_EXTRS)
792 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
793 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
794 FLAG(eh, PCI_HT_EH_PFLE),
795 FLAG(eh, PCI_HT_EH_OFLE),
796 FLAG(eh, PCI_HT_EH_PFE),
797 FLAG(eh, PCI_HT_EH_OFE),
798 FLAG(eh, PCI_HT_EH_EOCFE),
799 FLAG(eh, PCI_HT_EH_RFE),
800 FLAG(eh, PCI_HT_EH_CRCFE),
801 FLAG(eh, PCI_HT_EH_SERRFE),
802 FLAG(eh, PCI_HT_EH_CF),
803 FLAG(eh, PCI_HT_EH_RE),
804 FLAG(eh, PCI_HT_EH_PNFE),
805 FLAG(eh, PCI_HT_EH_ONFE),
806 FLAG(eh, PCI_HT_EH_EOCNFE),
807 FLAG(eh, PCI_HT_EH_RNFE),
808 FLAG(eh, PCI_HT_EH_CRCNFE),
809 FLAG(eh, PCI_HT_EH_SERRNFE));
810 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
811 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
812 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
817 show_ht(struct device *d, int where, int cmd)
821 switch (cmd & PCI_HT_CMD_TYP_HI)
823 case PCI_HT_CMD_TYP_HI_PRI:
824 show_ht_pri(d, where, cmd);
826 case PCI_HT_CMD_TYP_HI_SEC:
827 show_ht_sec(d, where, cmd);
831 type = cmd & PCI_HT_CMD_TYP;
834 case PCI_HT_CMD_TYP_SW:
835 printf("HyperTransport: Switch\n");
837 case PCI_HT_CMD_TYP_IDC:
838 printf("HyperTransport: Interrupt Discovery and Configuration\n");
840 case PCI_HT_CMD_TYP_RID:
841 printf("HyperTransport: Revision ID: %u.%02u\n",
842 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
844 case PCI_HT_CMD_TYP_UIDC:
845 printf("HyperTransport: UnitID Clumping\n");
847 case PCI_HT_CMD_TYP_ECSA:
848 printf("HyperTransport: Extended Configuration Space Access\n");
850 case PCI_HT_CMD_TYP_AM:
851 printf("HyperTransport: Address Mapping\n");
853 case PCI_HT_CMD_TYP_MSIM:
854 printf("HyperTransport: MSI Mapping\n");
856 case PCI_HT_CMD_TYP_DR:
857 printf("HyperTransport: DirectRoute\n");
859 case PCI_HT_CMD_TYP_VCS:
860 printf("HyperTransport: VCSet\n");
862 case PCI_HT_CMD_TYP_RM:
863 printf("HyperTransport: Retry Mode\n");
865 case PCI_HT_CMD_TYP_X86:
866 printf("HyperTransport: X86 (reserved)\n");
869 printf("HyperTransport: #%02x\n", type >> 11);
874 show_rom(struct device *d)
876 struct pci_dev *p = d->dev;
877 pciaddr_t rom = p->rom_base_addr;
878 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
882 printf("\tExpansion ROM at ");
883 if (rom & PCI_ROM_ADDRESS_MASK)
884 printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
886 printf("<unassigned>");
887 if (!(rom & PCI_ROM_ADDRESS_ENABLE))
888 printf(" [disabled]");
894 show_msi(struct device *d, int where, int cap)
900 printf("Message Signalled Interrupts: 64bit%c Queue=%d/%d Enable%c\n",
901 FLAG(cap, PCI_MSI_FLAGS_64BIT),
902 (cap & PCI_MSI_FLAGS_QSIZE) >> 4,
903 (cap & PCI_MSI_FLAGS_QMASK) >> 1,
904 FLAG(cap, PCI_MSI_FLAGS_ENABLE));
907 is64 = cap & PCI_MSI_FLAGS_64BIT;
908 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
910 printf("\t\tAddress: ");
913 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
914 w = get_conf_word(d, where + PCI_MSI_DATA_64);
918 w = get_conf_word(d, where + PCI_MSI_DATA_32);
919 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
920 printf("%08x Data: %04x\n", t, w);
926 int esr = cap & 0xff;
929 printf("Slot ID: %d slots, First%c, chassis %02x\n",
930 esr & PCI_SID_ESR_NSLOTS,
931 FLAG(esr, PCI_SID_ESR_FIC),
936 show_caps(struct device *d)
938 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
940 int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
944 printf("\tCapabilities: ");
945 if (!config_fetch(d, where, 4))
947 puts("<available only to root>");
950 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
951 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
952 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
953 printf("[%02x] ", where);
956 printf("<chain broken>\n");
962 show_pm(d, where, cap);
965 show_agp(d, where, cap);
968 printf("Vital Product Data\n");
970 case PCI_CAP_ID_SLOTID:
974 show_msi(d, where, cap);
976 case PCI_CAP_ID_PCIX:
980 show_ht(d, where, cap);
983 printf("#%02x [%04x]\n", id, cap);
991 show_htype0(struct device *d)
999 show_htype1(struct device *d)
1001 u32 io_base = get_conf_byte(d, PCI_IO_BASE);
1002 u32 io_limit = get_conf_byte(d, PCI_IO_LIMIT);
1003 u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
1004 u32 mem_base = get_conf_word(d, PCI_MEMORY_BASE);
1005 u32 mem_limit = get_conf_word(d, PCI_MEMORY_LIMIT);
1006 u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
1007 u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE);
1008 u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT);
1009 u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
1010 word sec_stat = get_conf_word(d, PCI_SEC_STATUS);
1011 word brc = get_conf_word(d, PCI_BRIDGE_CONTROL);
1012 int verb = verbose > 2;
1015 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1016 get_conf_byte(d, PCI_PRIMARY_BUS),
1017 get_conf_byte(d, PCI_SECONDARY_BUS),
1018 get_conf_byte(d, PCI_SUBORDINATE_BUS),
1019 get_conf_byte(d, PCI_SEC_LATENCY_TIMER));
1021 if (io_type != (io_limit & PCI_IO_RANGE_TYPE_MASK) ||
1022 (io_type != PCI_IO_RANGE_TYPE_16 && io_type != PCI_IO_RANGE_TYPE_32))
1023 printf("\t!!! Unknown I/O range types %x/%x\n", io_base, io_limit);
1026 io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
1027 io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
1028 if (io_type == PCI_IO_RANGE_TYPE_32)
1030 io_base |= (get_conf_word(d, PCI_IO_BASE_UPPER16) << 16);
1031 io_limit |= (get_conf_word(d, PCI_IO_LIMIT_UPPER16) << 16);
1033 if (io_base <= io_limit || verb)
1034 printf("\tI/O behind bridge: %08x-%08x\n", io_base, io_limit+0xfff);
1037 if (mem_type != (mem_limit & PCI_MEMORY_RANGE_TYPE_MASK) ||
1039 printf("\t!!! Unknown memory range types %x/%x\n", mem_base, mem_limit);
1042 mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
1043 mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
1044 if (mem_base <= mem_limit || verb)
1045 printf("\tMemory behind bridge: %08x-%08x\n", mem_base, mem_limit + 0xfffff);
1048 if (pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
1049 (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64))
1050 printf("\t!!! Unknown prefetchable memory range types %x/%x\n", pref_base, pref_limit);
1053 pref_base = (pref_base & PCI_PREF_RANGE_MASK) << 16;
1054 pref_limit = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
1055 if (pref_base <= pref_limit || verb)
1057 if (pref_type == PCI_PREF_RANGE_TYPE_32)
1058 printf("\tPrefetchable memory behind bridge: %08x-%08x\n", pref_base, pref_limit + 0xfffff);
1060 printf("\tPrefetchable memory behind bridge: %08x%08x-%08x%08x\n",
1061 get_conf_long(d, PCI_PREF_BASE_UPPER32),
1063 get_conf_long(d, PCI_PREF_LIMIT_UPPER32),
1069 printf("\tSecondary status: 66Mhz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c\n",
1070 FLAG(sec_stat, PCI_STATUS_66MHZ),
1071 FLAG(sec_stat, PCI_STATUS_FAST_BACK),
1072 FLAG(sec_stat, PCI_STATUS_PARITY),
1073 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1074 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1075 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1076 FLAG(sec_stat, PCI_STATUS_SIG_TARGET_ABORT),
1077 FLAG(sec_stat, PCI_STATUS_REC_TARGET_ABORT),
1078 FLAG(sec_stat, PCI_STATUS_REC_MASTER_ABORT),
1079 FLAG(sec_stat, PCI_STATUS_SIG_SYSTEM_ERROR),
1080 FLAG(sec_stat, PCI_STATUS_DETECTED_PARITY));
1085 printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
1086 FLAG(brc, PCI_BRIDGE_CTL_PARITY),
1087 FLAG(brc, PCI_BRIDGE_CTL_SERR),
1088 FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
1089 FLAG(brc, PCI_BRIDGE_CTL_VGA),
1090 FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
1091 FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
1092 FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
1098 show_htype2(struct device *d)
1101 word cmd = get_conf_word(d, PCI_COMMAND);
1102 word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
1103 word exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
1104 int verb = verbose > 2;
1107 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1108 get_conf_byte(d, PCI_CB_PRIMARY_BUS),
1109 get_conf_byte(d, PCI_CB_CARD_BUS),
1110 get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
1111 get_conf_byte(d, PCI_CB_LATENCY_TIMER));
1115 u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
1116 u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
1117 if (limit > base || verb)
1118 printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
1119 (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
1120 (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
1125 u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
1126 u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
1127 if (!(base & PCI_IO_RANGE_TYPE_32))
1132 base &= PCI_CB_IO_RANGE_MASK;
1133 limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
1134 if (base <= limit || verb)
1135 printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
1136 (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
1139 if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
1140 printf("\tSecondary status: SERR\n");
1142 printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
1143 FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
1144 FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
1145 FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
1146 FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
1147 FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
1148 FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
1149 FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
1150 FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
1152 printf("\t16-bit legacy interface ports at %04x\n", exca);
1156 show_verbose(struct device *d)
1158 struct pci_dev *p = d->dev;
1159 word status = get_conf_word(d, PCI_STATUS);
1160 word cmd = get_conf_word(d, PCI_COMMAND);
1161 word class = get_conf_word(d, PCI_CLASS_DEVICE);
1162 byte bist = get_conf_byte(d, PCI_BIST);
1163 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1164 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
1165 byte cache_line = get_conf_byte(d, PCI_CACHE_LINE_SIZE);
1166 byte max_lat, min_gnt;
1167 byte int_pin = get_conf_byte(d, PCI_INTERRUPT_PIN);
1168 unsigned int irq = p->irq;
1169 word subsys_v, subsys_d;
1170 char ssnamebuf[256];
1176 case PCI_HEADER_TYPE_NORMAL:
1177 if (class == PCI_CLASS_BRIDGE_PCI)
1178 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1179 max_lat = get_conf_byte(d, PCI_MAX_LAT);
1180 min_gnt = get_conf_byte(d, PCI_MIN_GNT);
1181 subsys_v = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1182 subsys_d = get_conf_word(d, PCI_SUBSYSTEM_ID);
1184 case PCI_HEADER_TYPE_BRIDGE:
1185 if (class != PCI_CLASS_BRIDGE_PCI)
1186 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1187 irq = int_pin = min_gnt = max_lat = 0;
1188 subsys_v = subsys_d = 0;
1190 case PCI_HEADER_TYPE_CARDBUS:
1191 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1192 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1193 min_gnt = max_lat = 0;
1194 subsys_v = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1195 subsys_d = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1198 printf("\t!!! Unknown header type %02x\n", htype);
1202 if (subsys_v && subsys_v != 0xffff)
1203 printf("\tSubsystem: %s\n",
1204 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1205 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1206 p->vendor_id, p->device_id, subsys_v, subsys_d));
1210 printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c\n",
1211 FLAG(cmd, PCI_COMMAND_IO),
1212 FLAG(cmd, PCI_COMMAND_MEMORY),
1213 FLAG(cmd, PCI_COMMAND_MASTER),
1214 FLAG(cmd, PCI_COMMAND_SPECIAL),
1215 FLAG(cmd, PCI_COMMAND_INVALIDATE),
1216 FLAG(cmd, PCI_COMMAND_VGA_PALETTE),
1217 FLAG(cmd, PCI_COMMAND_PARITY),
1218 FLAG(cmd, PCI_COMMAND_WAIT),
1219 FLAG(cmd, PCI_COMMAND_SERR),
1220 FLAG(cmd, PCI_COMMAND_FAST_BACK));
1221 printf("\tStatus: Cap%c 66Mhz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c\n",
1222 FLAG(status, PCI_STATUS_CAP_LIST),
1223 FLAG(status, PCI_STATUS_66MHZ),
1224 FLAG(status, PCI_STATUS_UDF),
1225 FLAG(status, PCI_STATUS_FAST_BACK),
1226 FLAG(status, PCI_STATUS_PARITY),
1227 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1228 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1229 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1230 FLAG(status, PCI_STATUS_SIG_TARGET_ABORT),
1231 FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
1232 FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
1233 FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
1234 FLAG(status, PCI_STATUS_DETECTED_PARITY));
1235 if (cmd & PCI_COMMAND_MASTER)
1237 printf("\tLatency: %d", latency);
1238 if (min_gnt || max_lat)
1242 printf("%dns min", min_gnt*250);
1243 if (min_gnt && max_lat)
1246 printf("%dns max", max_lat*250);
1250 printf(", Cache Line Size %02x", cache_line);
1254 printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n",
1255 (int_pin ? 'A' + int_pin - 1 : '?'), irq);
1259 printf("\tFlags: ");
1260 if (cmd & PCI_COMMAND_MASTER)
1261 printf("bus master, ");
1262 if (cmd & PCI_COMMAND_VGA_PALETTE)
1263 printf("VGA palette snoop, ");
1264 if (cmd & PCI_COMMAND_WAIT)
1265 printf("stepping, ");
1266 if (cmd & PCI_COMMAND_FAST_BACK)
1267 printf("fast Back2Back, ");
1268 if (status & PCI_STATUS_66MHZ)
1270 if (status & PCI_STATUS_UDF)
1271 printf("user-definable features, ");
1273 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1274 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1275 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??");
1276 if (cmd & PCI_COMMAND_MASTER)
1277 printf(", latency %d", latency);
1279 printf(", IRQ " PCIIRQ_FMT, irq);
1283 if (bist & PCI_BIST_CAPABLE)
1285 if (bist & PCI_BIST_START)
1286 printf("\tBIST is running\n");
1288 printf("\tBIST result: %02x\n", bist & PCI_BIST_CODE_MASK);
1293 case PCI_HEADER_TYPE_NORMAL:
1296 case PCI_HEADER_TYPE_BRIDGE:
1299 case PCI_HEADER_TYPE_CARDBUS:
1306 show_hex_dump(struct device *d)
1310 for(i=0; i<d->config_cnt; i++)
1314 printf(" %02x", get_conf_byte(d, i));
1321 show_machine(struct device *d)
1323 struct pci_dev *p = d->dev;
1325 word sv_id=0, sd_id=0;
1326 char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
1328 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
1330 case PCI_HEADER_TYPE_NORMAL:
1331 sv_id = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1332 sd_id = get_conf_word(d, PCI_SUBSYSTEM_ID);
1334 case PCI_HEADER_TYPE_CARDBUS:
1335 sv_id = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1336 sd_id = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1342 printf("Device:\t");
1345 printf("Class:\t%s\n",
1346 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0));
1347 printf("Vendor:\t%s\n",
1348 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, 0, 0));
1349 printf("Device:\t%s\n",
1350 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, 0, 0));
1351 if (sv_id && sv_id != 0xffff)
1353 printf("SVendor:\t%s\n",
1354 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, sv_id, sd_id));
1355 printf("SDevice:\t%s\n",
1356 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1358 if (c = get_conf_byte(d, PCI_REVISION_ID))
1359 printf("Rev:\t%02x\n", c);
1360 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1361 printf("ProgIf:\t%02x\n", c);
1366 printf(" \"%s\" \"%s\" \"%s\"",
1367 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS,
1368 get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0),
1369 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR,
1370 p->vendor_id, p->device_id, 0, 0),
1371 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE,
1372 p->vendor_id, p->device_id, 0, 0));
1373 if (c = get_conf_byte(d, PCI_REVISION_ID))
1374 printf(" -r%02x", c);
1375 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1376 printf(" -p%02x", c);
1377 if (sv_id && sv_id != 0xffff)
1378 printf(" \"%s\" \"%s\"",
1379 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, sv_id, sd_id),
1380 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1382 printf(" \"\" \"\"");
1388 show_device(struct device *d)
1390 if (machine_readable)
1398 if (verbose || show_hex)
1407 for(d=first_dev; d; d=d->next)
1414 struct bridge *chain; /* Single-linked list of bridges */
1415 struct bridge *next, *child; /* Tree of bridges */
1416 struct bus *first_bus; /* List of busses connected to this bridge */
1417 unsigned int domain;
1418 unsigned int primary, secondary, subordinate; /* Bus numbers */
1419 struct device *br_dev;
1423 unsigned int domain;
1424 unsigned int number;
1425 struct bus *sibling;
1426 struct device *first_dev, **last_dev;
1429 static struct bridge host_bridge = { NULL, NULL, NULL, NULL, 0, ~0, 0, ~0, NULL };
1432 find_bus(struct bridge *b, unsigned int domain, unsigned int n)
1436 for(bus=b->first_bus; bus; bus=bus->sibling)
1437 if (bus->domain == domain && bus->number == n)
1443 new_bus(struct bridge *b, unsigned int domain, unsigned int n)
1445 struct bus *bus = xmalloc(sizeof(struct bus));
1447 bus = xmalloc(sizeof(struct bus));
1448 bus->domain = domain;
1450 bus->sibling = b->first_bus;
1451 bus->first_dev = NULL;
1452 bus->last_dev = &bus->first_dev;
1458 insert_dev(struct device *d, struct bridge *b)
1460 struct pci_dev *p = d->dev;
1463 if (! (bus = find_bus(b, p->domain, p->bus)))
1466 for(c=b->child; c; c=c->next)
1467 if (c->domain == p->domain && c->secondary <= p->bus && p->bus <= c->subordinate)
1472 bus = new_bus(b, p->domain, p->bus);
1474 /* Simple insertion at the end _does_ guarantee the correct order as the
1475 * original device list was sorted by (domain, bus, devfn) lexicographically
1476 * and all devices on the new list have the same bus number.
1479 bus->last_dev = &d->next;
1486 struct device *d, *d2;
1487 struct bridge **last_br, *b;
1489 /* Build list of bridges */
1491 last_br = &host_bridge.chain;
1492 for(d=first_dev; d; d=d->next)
1494 word class = get_conf_word(d, PCI_CLASS_DEVICE);
1495 byte ht = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1496 if (class == PCI_CLASS_BRIDGE_PCI &&
1497 (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS))
1499 b = xmalloc(sizeof(struct bridge));
1500 b->domain = d->dev->domain;
1501 if (ht == PCI_HEADER_TYPE_BRIDGE)
1503 b->primary = get_conf_byte(d, PCI_CB_PRIMARY_BUS);
1504 b->secondary = get_conf_byte(d, PCI_CB_CARD_BUS);
1505 b->subordinate = get_conf_byte(d, PCI_CB_SUBORDINATE_BUS);
1509 b->primary = get_conf_byte(d, PCI_PRIMARY_BUS);
1510 b->secondary = get_conf_byte(d, PCI_SECONDARY_BUS);
1511 b->subordinate = get_conf_byte(d, PCI_SUBORDINATE_BUS);
1514 last_br = &b->chain;
1515 b->next = b->child = NULL;
1516 b->first_bus = NULL;
1522 /* Create a bridge tree */
1524 for(b=&host_bridge; b; b=b->chain)
1526 struct bridge *c, *best;
1528 for(c=&host_bridge; c; c=c->chain)
1529 if (c != b && (c == &host_bridge || b->domain == c->domain) &&
1530 b->primary >= c->secondary && b->primary <= c->subordinate &&
1531 (!best || best->subordinate - best->primary > c->subordinate - c->primary))
1535 b->next = best->child;
1540 /* Insert secondary bus for each bridge */
1542 for(b=&host_bridge; b; b=b->chain)
1543 if (!find_bus(b, b->domain, b->secondary))
1544 new_bus(b, b->domain, b->secondary);
1546 /* Create bus structs and link devices */
1548 for(d=first_dev; d;)
1551 insert_dev(d, &host_bridge);
1557 print_it(byte *line, byte *p)
1561 fputs(line, stdout);
1562 for(p=line; *p; p++)
1563 if (*p == '+' || *p == '|')
1569 static void show_tree_bridge(struct bridge *, byte *, byte *);
1572 show_tree_dev(struct device *d, byte *line, byte *p)
1574 struct pci_dev *q = d->dev;
1578 p += sprintf(p, "%02x.%x", q->dev, q->func);
1579 for(b=&host_bridge; b; b=b->chain)
1582 if (b->secondary == b->subordinate)
1583 p += sprintf(p, "-[%04x:%02x]-", b->domain, b->secondary);
1585 p += sprintf(p, "-[%04x:%02x-%02x]-", b->domain, b->secondary, b->subordinate);
1586 show_tree_bridge(b, line, p);
1590 p += sprintf(p, " %s",
1591 pci_lookup_name(pacc, namebuf, sizeof(namebuf),
1592 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1593 q->vendor_id, q->device_id, 0, 0));
1598 show_tree_bus(struct bus *b, byte *line, byte *p)
1602 else if (!b->first_dev->next)
1606 show_tree_dev(b->first_dev, line, p);
1610 struct device *d = b->first_dev;
1615 show_tree_dev(d, line, p+2);
1620 show_tree_dev(d, line, p+2);
1625 show_tree_bridge(struct bridge *b, byte *line, byte *p)
1628 if (!b->first_bus->sibling)
1630 if (b == &host_bridge)
1631 p += sprintf(p, "[%04x:%02x]-", b->domain, b->first_bus->number);
1632 show_tree_bus(b->first_bus, line, p);
1636 struct bus *u = b->first_bus;
1641 k = p + sprintf(p, "+-[%04x:%02x]-", u->domain, u->number);
1642 show_tree_bus(u, line, k);
1645 k = p + sprintf(p, "\\-[%04x:%02x]-", u->domain, u->number);
1646 show_tree_bus(u, line, k);
1656 show_tree_bridge(&host_bridge, line, line);
1659 /* Bus mapping mode */
1662 struct bus_bridge *next;
1663 byte this, dev, func, first, last, bug;
1669 struct bus_bridge *bridges, *via;
1672 static struct bus_info *bus_info;
1675 map_bridge(struct bus_info *bi, struct device *d, int np, int ns, int nl)
1677 struct bus_bridge *b = xmalloc(sizeof(struct bus_bridge));
1678 struct pci_dev *p = d->dev;
1680 b->next = bi->bridges;
1682 b->this = get_conf_byte(d, np);
1685 b->first = get_conf_byte(d, ns);
1686 b->last = get_conf_byte(d, nl);
1687 printf("## %02x.%02x:%d is a bridge from %02x to %02x-%02x\n",
1688 p->bus, p->dev, p->func, b->this, b->first, b->last);
1689 if (b->this != p->bus)
1690 printf("!!! Bridge points to invalid primary bus.\n");
1691 if (b->first > b->last)
1693 printf("!!! Bridge points to invalid bus range.\n");
1702 int verbose = pacc->debugging;
1703 struct bus_info *bi = bus_info + bus;
1707 printf("Mapping bus %02x\n", bus);
1708 for(dev = 0; dev < 32; dev++)
1709 if (filter.slot < 0 || filter.slot == dev)
1712 for(func = 0; func < func_limit; func++)
1713 if (filter.func < 0 || filter.func == func)
1715 /* XXX: Bus mapping supports only domain 0 */
1716 struct pci_dev *p = pci_get_dev(pacc, 0, bus, dev, func);
1717 u16 vendor = pci_read_word(p, PCI_VENDOR_ID);
1718 if (vendor && vendor != 0xffff)
1720 if (!func && (pci_read_byte(p, PCI_HEADER_TYPE) & 0x80))
1723 printf("Discovered device %02x:%02x.%d\n", bus, dev, func);
1725 if (d = scan_device(p))
1728 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
1730 case PCI_HEADER_TYPE_BRIDGE:
1731 map_bridge(bi, d, PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS);
1733 case PCI_HEADER_TYPE_CARDBUS:
1734 map_bridge(bi, d, PCI_CB_PRIMARY_BUS, PCI_CB_CARD_BUS, PCI_CB_SUBORDINATE_BUS);
1740 printf("But it was filtered out.\n");
1748 do_map_bridges(int bus, int min, int max)
1750 struct bus_info *bi = bus_info + bus;
1751 struct bus_bridge *b;
1754 for(b=bi->bridges; b; b=b->next)
1756 if (bus_info[b->first].guestbook)
1758 else if (b->first < min || b->last > max)
1762 bus_info[b->first].via = b;
1763 do_map_bridges(b->first, b->first, b->last);
1773 printf("\nSummary of buses:\n\n");
1774 for(i=0; i<256; i++)
1775 if (bus_info[i].exists && !bus_info[i].guestbook)
1776 do_map_bridges(i, 0, 255);
1777 for(i=0; i<256; i++)
1779 struct bus_info *bi = bus_info + i;
1780 struct bus_bridge *b = bi->via;
1784 printf("%02x: ", i);
1786 printf("Entered via %02x:%02x.%d\n", b->this, b->dev, b->func);
1788 printf("Primary host bus\n");
1790 printf("Secondary host bus (?)\n");
1792 for(b=bi->bridges; b; b=b->next)
1794 printf("\t%02x.%d Bridge to %02x-%02x", b->dev, b->func, b->first, b->last);
1798 printf(" <overlap bug>");
1801 printf(" <crossing bug>");
1812 if (pacc->method == PCI_ACCESS_PROC_BUS_PCI ||
1813 pacc->method == PCI_ACCESS_DUMP)
1814 printf("WARNING: Bus mapping can be reliable only with direct hardware access enabled.\n\n");
1815 else if (!check_root())
1816 die("Only root can map the bus.");
1817 bus_info = xmalloc(sizeof(struct bus_info) * 256);
1818 bzero(bus_info, sizeof(struct bus_info) * 256);
1819 if (filter.bus >= 0)
1820 do_map_bus(filter.bus);
1824 for(bus=0; bus<256; bus++)
1833 main(int argc, char **argv)
1838 if (argc == 2 && !strcmp(argv[1], "--version"))
1840 puts("lspci version " PCIUTILS_VERSION);
1846 pci_filter_init(pacc, &filter);
1848 while ((i = getopt(argc, argv, options)) != -1)
1852 pacc->numeric_ids = 1;
1858 pacc->buscentric = 1;
1859 buscentric_view = 1;
1862 if (msg = pci_filter_parse_slot(&filter, optarg))
1866 if (msg = pci_filter_parse_id(&filter, optarg))
1876 pacc->id_file_name = optarg;
1885 if (parse_generic_option(i, pacc, optarg))
1888 fprintf(stderr, help_msg, pacc->id_file_name);