2 * The PCI Utilities -- List All PCI Devices
4 * Copyright (c) 1997--2004 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
19 static int verbose; /* Show detailed information */
20 static int buscentric_view; /* Show bus addresses/IRQ's instead of CPU-visible ones */
21 static int show_hex; /* Show contents of config space as hexadecimal numbers */
22 static struct pci_filter filter; /* Device filter */
23 static int show_tree; /* Show bus tree */
24 static int machine_readable; /* Generate machine-readable output */
25 static int map_mode; /* Bus mapping mode enabled */
27 static char options[] = "nvbxs:d:ti:mgM" GENERIC_OPTIONS ;
29 static char help_msg[] = "\
30 Usage: lspci [<switches>]\n\
33 -n\t\tShow numeric ID's\n\
34 -b\t\tBus-centric view (PCI addresses and IRQ's instead of those seen by the CPU)\n\
35 -x\t\tShow hex-dump of the standard portion of config space\n\
36 -xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n\
37 -xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n\
38 -s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n\
39 -d [<vendor>]:[<device>]\tShow only selected devices\n\
40 -t\t\tShow bus tree\n\
41 -m\t\tProduce machine-readable output\n\
42 -i <file>\tUse specified ID database instead of %s\n\
43 -M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
47 /* Communication with libpci */
49 static struct pci_access *pacc;
52 * If we aren't being compiled by GCC, use malloc() instead of alloca().
53 * This increases our memory footprint, but only slightly since we don't
61 /* Our view of the PCI bus */
66 unsigned int config_cnt;
70 static struct device *first_dev;
72 static struct device *
73 scan_device(struct pci_dev *p)
77 if (!pci_filter_match(&filter, p))
79 d = xmalloc(sizeof(struct device));
83 if (!pci_read_block(p, 0, d->config, 64))
84 die("Unable to read the configuration space header.");
85 if ((d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
87 /* For cardbus bridges, we need to fetch 64 bytes more to get the full standard header... */
88 if (!pci_read_block(p, 64, d->config+64, 64))
89 die("Unable to read cardbus bridge extension data.");
92 pci_setup_cache(p, d->config, d->config_cnt);
93 pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
104 for(p=pacc->devices; p; p=p->next)
105 if (d = scan_device(p))
113 config_fetch(struct device *d, unsigned int pos, unsigned int len)
115 if (pos + len < d->config_cnt)
117 return pci_read_block(d->dev, pos, d->config + pos, len);
120 /* Config space accesses */
123 get_conf_byte(struct device *d, unsigned int pos)
125 return d->config[pos];
129 get_conf_word(struct device *d, unsigned int pos)
131 return d->config[pos] | (d->config[pos+1] << 8);
135 get_conf_long(struct device *d, unsigned int pos)
137 return d->config[pos] |
138 (d->config[pos+1] << 8) |
139 (d->config[pos+2] << 16) |
140 (d->config[pos+3] << 24);
146 compare_them(const void *A, const void *B)
148 const struct pci_dev *a = (*(const struct device **)A)->dev;
149 const struct pci_dev *b = (*(const struct device **)B)->dev;
151 if (a->domain < b->domain)
153 if (a->domain > b->domain)
163 if (a->func < b->func)
165 if (a->func > b->func)
173 struct device **index, **h, **last_dev;
178 for(d=first_dev; d; d=d->next)
180 h = index = alloca(sizeof(struct device *) * cnt);
181 for(d=first_dev; d; d=d->next)
183 qsort(index, cnt, sizeof(struct device *), compare_them);
184 last_dev = &first_dev;
189 last_dev = &(*h)->next;
197 #define FLAG(x,y) ((x & y) ? '+' : '-')
200 show_slot_name(struct device *d)
202 struct pci_dev *p = d->dev;
205 printf("%04x:", p->domain);
206 printf("%02x:%02x.%d", p->bus, p->dev, p->func);
210 show_terse(struct device *d)
213 struct pci_dev *p = d->dev;
214 byte classbuf[128], devbuf[128];
218 pci_lookup_name(pacc, classbuf, sizeof(classbuf),
220 get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0),
221 pci_lookup_name(pacc, devbuf, sizeof(devbuf),
222 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
223 p->vendor_id, p->device_id, 0, 0));
224 if (c = get_conf_byte(d, PCI_REVISION_ID))
225 printf(" (rev %02x)", c);
229 c = get_conf_byte(d, PCI_CLASS_PROG);
230 x = pci_lookup_name(pacc, devbuf, sizeof(devbuf),
232 get_conf_word(d, PCI_CLASS_DEVICE), c, 0, 0);
235 printf(" (prog-if %02x", c);
245 show_size(pciaddr_t x)
251 printf("%d", (int) x);
252 else if (x < 1048576)
253 printf("%dK", (int)(x / 1024));
254 else if (x < 0x80000000)
255 printf("%dM", (int)(x / 1048576));
257 printf(PCIADDR_T_FMT, x);
262 show_bases(struct device *d, int cnt)
264 struct pci_dev *p = d->dev;
265 word cmd = get_conf_word(d, PCI_COMMAND);
270 pciaddr_t pos = p->base_addr[i];
271 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
272 u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
273 if (flg == 0xffffffff)
275 if (!pos && !flg && !len)
278 printf("\tRegion %d: ", i);
281 if (pos && !flg) /* Reported by the OS, but not by the device */
283 printf("[virtual] ");
286 if (flg & PCI_BASE_ADDRESS_SPACE_IO)
288 pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
289 printf("I/O ports at ");
291 printf(PCIADDR_PORT_FMT, a);
292 else if (flg & PCI_BASE_ADDRESS_IO_MASK)
295 printf("<unassigned>");
296 if (!(cmd & PCI_COMMAND_IO))
297 printf(" [disabled]");
301 int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
302 pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
306 printf("Memory at ");
307 if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
311 printf("<invalid-64bit-slot>");
317 z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
321 printf("%08x" PCIADDR_T_FMT, z, a);
323 printf("<unassigned>");
331 printf(PCIADDR_T_FMT, a);
333 printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
335 printf(" (%s, %sprefetchable)",
336 (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
337 (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
338 (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
339 (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
340 if (!(cmd & PCI_COMMAND_MEMORY))
341 printf(" [disabled]");
349 show_pm(struct device *d, int where, int cap)
352 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
354 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
357 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
358 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
359 FLAG(cap, PCI_PM_CAP_DSI),
360 FLAG(cap, PCI_PM_CAP_D1),
361 FLAG(cap, PCI_PM_CAP_D2),
362 pm_aux_current[(cap >> 6) & 7],
363 FLAG(cap, PCI_PM_CAP_PME_D0),
364 FLAG(cap, PCI_PM_CAP_PME_D1),
365 FLAG(cap, PCI_PM_CAP_PME_D2),
366 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
367 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
368 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
370 t = get_conf_word(d, where + PCI_PM_CTRL);
371 printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
372 t & PCI_PM_CTRL_STATE_MASK,
373 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
374 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
375 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
376 FLAG(t, PCI_PM_CTRL_PME_STATUS));
377 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
379 printf("\t\tBridge: PM%c B3%c\n",
380 FLAG(t, PCI_PM_BPCC_ENABLE),
381 FLAG(~t, PCI_PM_PPB_B2_B3));
385 format_agp_rate(int rate, char *buf, int agp3)
395 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
400 strcpy(buf, "<none>");
404 show_agp(struct device *d, int where, int cap)
411 ver = (cap >> 4) & 0x0f;
413 printf("AGP version %x.%x\n", ver, rev);
416 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
418 t = get_conf_long(d, where + PCI_AGP_STATUS);
419 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
421 format_agp_rate(t & 7, rate, agp3);
422 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
423 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
424 FLAG(t, PCI_AGP_STATUS_ISOCH),
425 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
426 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
427 FLAG(t, PCI_AGP_STATUS_SBA),
428 FLAG(t, PCI_AGP_STATUS_ITA_COH),
429 FLAG(t, PCI_AGP_STATUS_GART64),
430 FLAG(t, PCI_AGP_STATUS_HTRANS),
431 FLAG(t, PCI_AGP_STATUS_64BIT),
432 FLAG(t, PCI_AGP_STATUS_FW),
433 FLAG(t, PCI_AGP_STATUS_AGP3),
435 t = get_conf_long(d, where + PCI_AGP_COMMAND);
436 format_agp_rate(t & 7, rate, agp3);
437 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
438 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
439 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
440 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
441 FLAG(t, PCI_AGP_COMMAND_SBA),
442 FLAG(t, PCI_AGP_COMMAND_AGP),
443 FLAG(t, PCI_AGP_COMMAND_GART64),
444 FLAG(t, PCI_AGP_COMMAND_64BIT),
445 FLAG(t, PCI_AGP_COMMAND_FW),
450 show_pcix_nobridge(struct device *d, int where)
455 printf("PCI-X non-bridge device.\n");
460 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
463 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
464 status = get_conf_long(d, where + PCI_PCIX_STATUS);
465 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
466 FLAG(command, PCI_PCIX_COMMAND_DPERE),
467 FLAG(command, PCI_PCIX_COMMAND_ERO),
468 ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U),
469 ((command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U));
470 printf("\t\tStatus: Bus=%u Dev=%u Func=%u 64bit%c 133MHz%c SCD%c USC%c, DC=%s, DMMRBC=%u, DMOST=%u, DMCRS=%u, RSCEM%c\n",
471 ((status >> 8) & 0xffU), // bus
472 ((status >> 3) & 0x1fU), // dev
473 (status & PCI_PCIX_STATUS_FUNCTION), // function
474 FLAG(status, PCI_PCIX_STATUS_64BIT),
475 FLAG(status, PCI_PCIX_STATUS_133MHZ),
476 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
477 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
478 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
479 ((status >> 21) & 3U),
480 ((status >> 23) & 7U),
481 ((status >> 26) & 7U),
482 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS));
486 show_pcix_bridge(struct device *d, int where)
490 u32 status, upstcr, downstcr;
492 printf("PCI-X bridge device.\n");
497 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
500 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
501 printf("\t\tSecondary Status: 64bit%c, 133MHz%c, SCD%c, USC%c, SCO%c, SRD%c Freq=%d\n",
502 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
503 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
504 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
505 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
506 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
507 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
508 ((secstatus >> 6) & 7));
509 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
510 printf("\t\tStatus: Bus=%u Dev=%u Func=%u 64bit%c 133MHz%c SCD%c USC%c, SCO%c, SRD%c\n",
511 ((status >> 8) & 0xff), // bus
512 ((status >> 3) & 0x1f), // dev
513 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION), // function
514 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
515 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
516 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
517 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
518 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
519 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
520 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
521 printf("\t\t: Upstream: Capacity=%u, Commitment Limit=%u\n",
522 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
523 (upstcr >> 16) & 0xffff);
524 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
525 printf("\t\t: Downstream: Capacity=%u, Commitment Limit=%u\n",
526 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
527 (downstcr >> 16) & 0xffff);
531 show_pcix(struct device *d, int where)
533 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
535 case PCI_HEADER_TYPE_NORMAL:
536 show_pcix_nobridge(d, where);
538 case PCI_HEADER_TYPE_BRIDGE:
539 show_pcix_bridge(d, where);
545 ht_link_width(unsigned width)
547 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
548 return widths[width];
552 ht_link_freq(unsigned freq)
554 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
555 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
560 show_ht_pri(struct device *d, int where, int cmd)
562 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
563 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
565 printf("HyperTransport: Slave or Primary Interface\n");
569 printf("\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n",
570 (cmd & PCI_HT_PRI_CMD_BUID),
571 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
572 FLAG(cmd, PCI_HT_PRI_CMD_MH),
573 FLAG(cmd, PCI_HT_PRI_CMD_DD),
574 FLAG(cmd, PCI_HT_PRI_CMD_DUL));
575 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
577 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
578 printf("\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n",
579 FLAG(lctr0, PCI_HT_LCTR_CFLE),
580 FLAG(lctr0, PCI_HT_LCTR_CST),
581 FLAG(lctr0, PCI_HT_LCTR_CFE),
582 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
583 FLAG(lctr0, PCI_HT_LCTR_INIT),
584 FLAG(lctr0, PCI_HT_LCTR_EOC),
585 FLAG(lctr0, PCI_HT_LCTR_TXO),
586 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
587 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
588 FLAG(lctr0, PCI_HT_LCTR_LSEN),
589 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
590 FLAG(lctr0, PCI_HT_LCTR_64B));
591 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
592 printf("\t\tLink Config 0: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
593 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
594 FLAG(lcnf0, PCI_HT_LCNF_DFI),
595 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
596 FLAG(lcnf0, PCI_HT_LCNF_DFO),
597 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
598 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
599 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
600 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
601 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
602 printf("\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n",
603 FLAG(lctr1, PCI_HT_LCTR_CFLE),
604 FLAG(lctr1, PCI_HT_LCTR_CST),
605 FLAG(lctr1, PCI_HT_LCTR_CFE),
606 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
607 FLAG(lctr1, PCI_HT_LCTR_INIT),
608 FLAG(lctr1, PCI_HT_LCTR_EOC),
609 FLAG(lctr1, PCI_HT_LCTR_TXO),
610 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
611 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
612 FLAG(lctr1, PCI_HT_LCTR_LSEN),
613 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
614 FLAG(lctr1, PCI_HT_LCTR_64B));
615 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
616 printf("\t\tLink Config 1: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
617 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
618 FLAG(lcnf1, PCI_HT_LCNF_DFI),
619 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
620 FLAG(lcnf1, PCI_HT_LCNF_DFO),
621 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
622 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
623 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
624 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
625 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
626 printf("\t\tRevision ID: %u.%02u\n",
627 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
628 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
629 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
630 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
631 FLAG(lfrer0, PCI_HT_LFRER_PROT),
632 FLAG(lfrer0, PCI_HT_LFRER_OV),
633 FLAG(lfrer0, PCI_HT_LFRER_EOC),
634 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
635 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
636 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
637 FLAG(lfcap0, PCI_HT_LFCAP_200),
638 FLAG(lfcap0, PCI_HT_LFCAP_300),
639 FLAG(lfcap0, PCI_HT_LFCAP_400),
640 FLAG(lfcap0, PCI_HT_LFCAP_500),
641 FLAG(lfcap0, PCI_HT_LFCAP_600),
642 FLAG(lfcap0, PCI_HT_LFCAP_800),
643 FLAG(lfcap0, PCI_HT_LFCAP_1000),
644 FLAG(lfcap0, PCI_HT_LFCAP_1200),
645 FLAG(lfcap0, PCI_HT_LFCAP_1400),
646 FLAG(lfcap0, PCI_HT_LFCAP_1600),
647 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
648 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
649 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
650 FLAG(ftr, PCI_HT_FTR_ISOCFC),
651 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
652 FLAG(ftr, PCI_HT_FTR_CRCTM),
653 FLAG(ftr, PCI_HT_FTR_ECTLT),
654 FLAG(ftr, PCI_HT_FTR_64BA),
655 FLAG(ftr, PCI_HT_FTR_UIDRD));
656 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
657 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
658 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
659 FLAG(lfrer1, PCI_HT_LFRER_PROT),
660 FLAG(lfrer1, PCI_HT_LFRER_OV),
661 FLAG(lfrer1, PCI_HT_LFRER_EOC),
662 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
663 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
664 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
665 FLAG(lfcap1, PCI_HT_LFCAP_200),
666 FLAG(lfcap1, PCI_HT_LFCAP_300),
667 FLAG(lfcap1, PCI_HT_LFCAP_400),
668 FLAG(lfcap1, PCI_HT_LFCAP_500),
669 FLAG(lfcap1, PCI_HT_LFCAP_600),
670 FLAG(lfcap1, PCI_HT_LFCAP_800),
671 FLAG(lfcap1, PCI_HT_LFCAP_1000),
672 FLAG(lfcap1, PCI_HT_LFCAP_1200),
673 FLAG(lfcap1, PCI_HT_LFCAP_1400),
674 FLAG(lfcap1, PCI_HT_LFCAP_1600),
675 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
676 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
677 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
678 FLAG(eh, PCI_HT_EH_PFLE),
679 FLAG(eh, PCI_HT_EH_OFLE),
680 FLAG(eh, PCI_HT_EH_PFE),
681 FLAG(eh, PCI_HT_EH_OFE),
682 FLAG(eh, PCI_HT_EH_EOCFE),
683 FLAG(eh, PCI_HT_EH_RFE),
684 FLAG(eh, PCI_HT_EH_CRCFE),
685 FLAG(eh, PCI_HT_EH_SERRFE),
686 FLAG(eh, PCI_HT_EH_CF),
687 FLAG(eh, PCI_HT_EH_RE),
688 FLAG(eh, PCI_HT_EH_PNFE),
689 FLAG(eh, PCI_HT_EH_ONFE),
690 FLAG(eh, PCI_HT_EH_EOCNFE),
691 FLAG(eh, PCI_HT_EH_RNFE),
692 FLAG(eh, PCI_HT_EH_CRCNFE),
693 FLAG(eh, PCI_HT_EH_SERRNFE));
694 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
695 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
696 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
697 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
698 printf("\t\tBus Number: %02x\n", bn);
702 show_ht_sec(struct device *d, int where, int cmd)
704 u16 lctr, lcnf, ftr, eh;
705 u8 rid, lfrer, lfcap, mbu, mlu;
707 printf("HyperTransport: Host or Secondary Interface\n");
711 printf("\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n",
712 FLAG(cmd, PCI_HT_SEC_CMD_WR),
713 FLAG(cmd, PCI_HT_SEC_CMD_DE),
714 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
715 FLAG(cmd, PCI_HT_SEC_CMD_CS),
716 FLAG(cmd, PCI_HT_SEC_CMD_HH),
717 FLAG(cmd, PCI_HT_SEC_CMD_AS),
718 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
719 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
720 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
722 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
723 printf("\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n",
724 FLAG(lctr, PCI_HT_LCTR_CFLE),
725 FLAG(lctr, PCI_HT_LCTR_CST),
726 FLAG(lctr, PCI_HT_LCTR_CFE),
727 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
728 FLAG(lctr, PCI_HT_LCTR_INIT),
729 FLAG(lctr, PCI_HT_LCTR_EOC),
730 FLAG(lctr, PCI_HT_LCTR_TXO),
731 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
732 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
733 FLAG(lctr, PCI_HT_LCTR_LSEN),
734 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
735 FLAG(lctr, PCI_HT_LCTR_64B));
736 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
737 printf("\t\tLink Config: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
738 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
739 FLAG(lcnf, PCI_HT_LCNF_DFI),
740 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
741 FLAG(lcnf, PCI_HT_LCNF_DFO),
742 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
743 FLAG(lcnf, PCI_HT_LCNF_DFIE),
744 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
745 FLAG(lcnf, PCI_HT_LCNF_DFOE));
746 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
747 printf("\t\tRevision ID: %u.%02u\n",
748 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
749 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
750 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
751 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
752 FLAG(lfrer, PCI_HT_LFRER_PROT),
753 FLAG(lfrer, PCI_HT_LFRER_OV),
754 FLAG(lfrer, PCI_HT_LFRER_EOC),
755 FLAG(lfrer, PCI_HT_LFRER_CTLT));
756 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
757 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
758 FLAG(lfcap, PCI_HT_LFCAP_200),
759 FLAG(lfcap, PCI_HT_LFCAP_300),
760 FLAG(lfcap, PCI_HT_LFCAP_400),
761 FLAG(lfcap, PCI_HT_LFCAP_500),
762 FLAG(lfcap, PCI_HT_LFCAP_600),
763 FLAG(lfcap, PCI_HT_LFCAP_800),
764 FLAG(lfcap, PCI_HT_LFCAP_1000),
765 FLAG(lfcap, PCI_HT_LFCAP_1200),
766 FLAG(lfcap, PCI_HT_LFCAP_1400),
767 FLAG(lfcap, PCI_HT_LFCAP_1600),
768 FLAG(lfcap, PCI_HT_LFCAP_VEND));
769 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
770 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
771 FLAG(ftr, PCI_HT_FTR_ISOCFC),
772 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
773 FLAG(ftr, PCI_HT_FTR_CRCTM),
774 FLAG(ftr, PCI_HT_FTR_ECTLT),
775 FLAG(ftr, PCI_HT_FTR_64BA),
776 FLAG(ftr, PCI_HT_FTR_UIDRD),
777 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
778 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
779 if (ftr & PCI_HT_SEC_FTR_EXTRS)
781 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
782 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
783 FLAG(eh, PCI_HT_EH_PFLE),
784 FLAG(eh, PCI_HT_EH_OFLE),
785 FLAG(eh, PCI_HT_EH_PFE),
786 FLAG(eh, PCI_HT_EH_OFE),
787 FLAG(eh, PCI_HT_EH_EOCFE),
788 FLAG(eh, PCI_HT_EH_RFE),
789 FLAG(eh, PCI_HT_EH_CRCFE),
790 FLAG(eh, PCI_HT_EH_SERRFE),
791 FLAG(eh, PCI_HT_EH_CF),
792 FLAG(eh, PCI_HT_EH_RE),
793 FLAG(eh, PCI_HT_EH_PNFE),
794 FLAG(eh, PCI_HT_EH_ONFE),
795 FLAG(eh, PCI_HT_EH_EOCNFE),
796 FLAG(eh, PCI_HT_EH_RNFE),
797 FLAG(eh, PCI_HT_EH_CRCNFE),
798 FLAG(eh, PCI_HT_EH_SERRNFE));
799 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
800 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
801 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
806 show_ht(struct device *d, int where, int cmd)
810 switch (cmd & PCI_HT_CMD_TYP_HI)
812 case PCI_HT_CMD_TYP_HI_PRI:
813 show_ht_pri(d, where, cmd);
815 case PCI_HT_CMD_TYP_HI_SEC:
816 show_ht_sec(d, where, cmd);
820 type = cmd & PCI_HT_CMD_TYP;
823 case PCI_HT_CMD_TYP_SW:
824 printf("HyperTransport: Switch\n");
826 case PCI_HT_CMD_TYP_IDC:
827 printf("HyperTransport: Interrupt Discovery and Configuration\n");
829 case PCI_HT_CMD_TYP_RID:
830 printf("HyperTransport: Revision ID: %u.%02u\n",
831 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
833 case PCI_HT_CMD_TYP_UIDC:
834 printf("HyperTransport: UnitID Clumping\n");
836 case PCI_HT_CMD_TYP_ECSA:
837 printf("HyperTransport: Extended Configuration Space Access\n");
839 case PCI_HT_CMD_TYP_AM:
840 printf("HyperTransport: Address Mapping\n");
842 case PCI_HT_CMD_TYP_MSIM:
843 printf("HyperTransport: MSI Mapping\n");
845 case PCI_HT_CMD_TYP_DR:
846 printf("HyperTransport: DirectRoute\n");
848 case PCI_HT_CMD_TYP_VCS:
849 printf("HyperTransport: VCSet\n");
851 case PCI_HT_CMD_TYP_RM:
852 printf("HyperTransport: Retry Mode\n");
854 case PCI_HT_CMD_TYP_X86:
855 printf("HyperTransport: X86 (reserved)\n");
858 printf("HyperTransport: #%02x\n", type >> 11);
863 show_rom(struct device *d)
865 struct pci_dev *p = d->dev;
866 pciaddr_t rom = p->rom_base_addr;
867 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
871 printf("\tExpansion ROM at ");
872 if (rom & PCI_ROM_ADDRESS_MASK)
873 printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
875 printf("<unassigned>");
876 if (!(rom & PCI_ROM_ADDRESS_ENABLE))
877 printf(" [disabled]");
883 show_msi(struct device *d, int where, int cap)
889 printf("Message Signalled Interrupts: 64bit%c Queue=%d/%d Enable%c\n",
890 FLAG(cap, PCI_MSI_FLAGS_64BIT),
891 (cap & PCI_MSI_FLAGS_QSIZE) >> 4,
892 (cap & PCI_MSI_FLAGS_QMASK) >> 1,
893 FLAG(cap, PCI_MSI_FLAGS_ENABLE));
896 is64 = cap & PCI_MSI_FLAGS_64BIT;
897 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
899 printf("\t\tAddress: ");
902 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
903 w = get_conf_word(d, where + PCI_MSI_DATA_64);
907 w = get_conf_word(d, where + PCI_MSI_DATA_32);
908 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
909 printf("%08x Data: %04x\n", t, w);
912 static void show_vendor(void)
914 printf("Vendor Specific Information\n");
917 static void show_debug(void)
919 printf("Debug port\n");
922 static float power_limit(int value, int scale)
924 float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
925 return value * scales[scale];
929 show_express(struct device *d, int where, int cap)
933 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
938 case PCI_EXP_TYPE_ENDPOINT:
941 case PCI_EXP_TYPE_LEG_END:
942 printf("Legacy Endpoint");
944 case PCI_EXP_TYPE_ROOT_PORT:
945 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
947 case PCI_EXP_TYPE_UPSTREAM:
948 printf("Upstream Port");
950 case PCI_EXP_TYPE_DOWNSTREAM:
951 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
953 case PCI_EXP_TYPE_PCI_BRIDGE:
954 printf("PCI Bridge");
957 printf("Unknown type");
959 printf(" IRQ %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
963 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
964 printf("\t\tMaxPayloadSizeSupported %d\n", 128 << (t & PCI_EXP_DEVCAP_PAYLOAD));
965 printf("\t\tPhantomFunctions %d\n", 1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3));
966 printf("\t\tExtendedTags%c\n", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
967 printf("\t\tL0sLatency <%dns\n", 64 << ((t & PCI_EXP_DEVCAP_L0S) >> 6));
968 printf("\t\tL1Latency <%dus\n", 1 << ((t & PCI_EXP_DEVCAP_L1) >> 9));
969 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END))
970 printf("\t\tAtnBtn%c AtnInd%c PwrInd%c\n", FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
971 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
972 if (type == PCI_EXP_TYPE_ROOT_PORT)
973 printf("\t\tMaxReadRequestSizeSupported %d\n", 128 << ((t & PCI_EXP_DEVCAP_READRQ) >> 15));
974 if (type == PCI_EXP_TYPE_UPSTREAM)
975 printf("\t\tSlotPowerLimit %f\n",
976 power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
977 (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
979 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
980 printf("\t\tError Reporting: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
981 FLAG(w, PCI_EXP_DEVCTL_CERE),
982 FLAG(w, PCI_EXP_DEVCTL_NFERE),
983 FLAG(w, PCI_EXP_DEVCTL_FERE),
984 FLAG(w, PCI_EXP_DEVCTL_URRE));
988 show_msix(struct device *d, int where, int cap)
992 printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
993 FLAG(cap, PCI_MSIX_ENABLE),
994 FLAG(cap, PCI_MSIX_MASK),
995 (cap & PCI_MSIX_TABSIZE) + 1);
996 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
999 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1000 printf("\t\tVector table: BAR=%d offset=%08x\n",
1001 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1002 off = get_conf_long(d, where + PCI_MSIX_PBA);
1003 printf("\t\tPBA: BAR=%d offset=%08x\n",
1004 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1008 show_slotid(int cap)
1010 int esr = cap & 0xff;
1013 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1014 esr & PCI_SID_ESR_NSLOTS,
1015 FLAG(esr, PCI_SID_ESR_FIC),
1020 show_caps(struct device *d)
1022 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1024 int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
1028 printf("\tCapabilities: ");
1029 if (!config_fetch(d, where, 4))
1031 puts("<available only to root>");
1034 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1035 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1036 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1037 printf("[%02x] ", where);
1040 printf("<chain broken>\n");
1046 show_pm(d, where, cap);
1048 case PCI_CAP_ID_AGP:
1049 show_agp(d, where, cap);
1051 case PCI_CAP_ID_VPD:
1052 printf("Vital Product Data\n");
1054 case PCI_CAP_ID_SLOTID:
1057 case PCI_CAP_ID_MSI:
1058 show_msi(d, where, cap);
1060 case PCI_CAP_ID_PCIX:
1061 show_pcix(d, where);
1064 show_ht(d, where, cap);
1066 case PCI_CAP_ID_VNDR:
1069 case PCI_CAP_ID_DBG:
1072 case PCI_CAP_ID_EXP:
1073 show_express(d, where, cap);
1075 case PCI_CAP_ID_MSIX:
1076 show_msix(d, where, cap);
1079 printf("#%02x [%04x]\n", id, cap);
1087 show_htype0(struct device *d)
1095 show_htype1(struct device *d)
1097 u32 io_base = get_conf_byte(d, PCI_IO_BASE);
1098 u32 io_limit = get_conf_byte(d, PCI_IO_LIMIT);
1099 u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
1100 u32 mem_base = get_conf_word(d, PCI_MEMORY_BASE);
1101 u32 mem_limit = get_conf_word(d, PCI_MEMORY_LIMIT);
1102 u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
1103 u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE);
1104 u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT);
1105 u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
1106 word sec_stat = get_conf_word(d, PCI_SEC_STATUS);
1107 word brc = get_conf_word(d, PCI_BRIDGE_CONTROL);
1108 int verb = verbose > 2;
1111 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1112 get_conf_byte(d, PCI_PRIMARY_BUS),
1113 get_conf_byte(d, PCI_SECONDARY_BUS),
1114 get_conf_byte(d, PCI_SUBORDINATE_BUS),
1115 get_conf_byte(d, PCI_SEC_LATENCY_TIMER));
1117 if (io_type != (io_limit & PCI_IO_RANGE_TYPE_MASK) ||
1118 (io_type != PCI_IO_RANGE_TYPE_16 && io_type != PCI_IO_RANGE_TYPE_32))
1119 printf("\t!!! Unknown I/O range types %x/%x\n", io_base, io_limit);
1122 io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
1123 io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
1124 if (io_type == PCI_IO_RANGE_TYPE_32)
1126 io_base |= (get_conf_word(d, PCI_IO_BASE_UPPER16) << 16);
1127 io_limit |= (get_conf_word(d, PCI_IO_LIMIT_UPPER16) << 16);
1129 if (io_base <= io_limit || verb)
1130 printf("\tI/O behind bridge: %08x-%08x\n", io_base, io_limit+0xfff);
1133 if (mem_type != (mem_limit & PCI_MEMORY_RANGE_TYPE_MASK) ||
1135 printf("\t!!! Unknown memory range types %x/%x\n", mem_base, mem_limit);
1138 mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
1139 mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
1140 if (mem_base <= mem_limit || verb)
1141 printf("\tMemory behind bridge: %08x-%08x\n", mem_base, mem_limit + 0xfffff);
1144 if (pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
1145 (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64))
1146 printf("\t!!! Unknown prefetchable memory range types %x/%x\n", pref_base, pref_limit);
1149 pref_base = (pref_base & PCI_PREF_RANGE_MASK) << 16;
1150 pref_limit = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
1151 if (pref_base <= pref_limit || verb)
1153 if (pref_type == PCI_PREF_RANGE_TYPE_32)
1154 printf("\tPrefetchable memory behind bridge: %08x-%08x\n", pref_base, pref_limit + 0xfffff);
1156 printf("\tPrefetchable memory behind bridge: %08x%08x-%08x%08x\n",
1157 get_conf_long(d, PCI_PREF_BASE_UPPER32),
1159 get_conf_long(d, PCI_PREF_LIMIT_UPPER32),
1165 printf("\tSecondary status: 66Mhz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c\n",
1166 FLAG(sec_stat, PCI_STATUS_66MHZ),
1167 FLAG(sec_stat, PCI_STATUS_FAST_BACK),
1168 FLAG(sec_stat, PCI_STATUS_PARITY),
1169 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1170 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1171 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1172 FLAG(sec_stat, PCI_STATUS_SIG_TARGET_ABORT),
1173 FLAG(sec_stat, PCI_STATUS_REC_TARGET_ABORT),
1174 FLAG(sec_stat, PCI_STATUS_REC_MASTER_ABORT),
1175 FLAG(sec_stat, PCI_STATUS_SIG_SYSTEM_ERROR),
1176 FLAG(sec_stat, PCI_STATUS_DETECTED_PARITY));
1181 printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
1182 FLAG(brc, PCI_BRIDGE_CTL_PARITY),
1183 FLAG(brc, PCI_BRIDGE_CTL_SERR),
1184 FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
1185 FLAG(brc, PCI_BRIDGE_CTL_VGA),
1186 FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
1187 FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
1188 FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
1194 show_htype2(struct device *d)
1197 word cmd = get_conf_word(d, PCI_COMMAND);
1198 word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
1199 word exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
1200 int verb = verbose > 2;
1203 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1204 get_conf_byte(d, PCI_CB_PRIMARY_BUS),
1205 get_conf_byte(d, PCI_CB_CARD_BUS),
1206 get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
1207 get_conf_byte(d, PCI_CB_LATENCY_TIMER));
1211 u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
1212 u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
1213 if (limit > base || verb)
1214 printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
1215 (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
1216 (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
1221 u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
1222 u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
1223 if (!(base & PCI_IO_RANGE_TYPE_32))
1228 base &= PCI_CB_IO_RANGE_MASK;
1229 limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
1230 if (base <= limit || verb)
1231 printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
1232 (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
1235 if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
1236 printf("\tSecondary status: SERR\n");
1238 printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
1239 FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
1240 FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
1241 FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
1242 FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
1243 FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
1244 FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
1245 FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
1246 FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
1248 printf("\t16-bit legacy interface ports at %04x\n", exca);
1252 show_verbose(struct device *d)
1254 struct pci_dev *p = d->dev;
1255 word status = get_conf_word(d, PCI_STATUS);
1256 word cmd = get_conf_word(d, PCI_COMMAND);
1257 word class = get_conf_word(d, PCI_CLASS_DEVICE);
1258 byte bist = get_conf_byte(d, PCI_BIST);
1259 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1260 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
1261 byte cache_line = get_conf_byte(d, PCI_CACHE_LINE_SIZE);
1262 byte max_lat, min_gnt;
1263 byte int_pin = get_conf_byte(d, PCI_INTERRUPT_PIN);
1264 unsigned int irq = p->irq;
1265 word subsys_v, subsys_d;
1266 char ssnamebuf[256];
1272 case PCI_HEADER_TYPE_NORMAL:
1273 if (class == PCI_CLASS_BRIDGE_PCI)
1274 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1275 max_lat = get_conf_byte(d, PCI_MAX_LAT);
1276 min_gnt = get_conf_byte(d, PCI_MIN_GNT);
1277 subsys_v = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1278 subsys_d = get_conf_word(d, PCI_SUBSYSTEM_ID);
1280 case PCI_HEADER_TYPE_BRIDGE:
1281 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1282 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1283 irq = int_pin = min_gnt = max_lat = 0;
1284 subsys_v = subsys_d = 0;
1286 case PCI_HEADER_TYPE_CARDBUS:
1287 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1288 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1289 min_gnt = max_lat = 0;
1290 subsys_v = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1291 subsys_d = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1294 printf("\t!!! Unknown header type %02x\n", htype);
1298 if (subsys_v && subsys_v != 0xffff)
1299 printf("\tSubsystem: %s\n",
1300 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1301 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1302 p->vendor_id, p->device_id, subsys_v, subsys_d));
1306 printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c\n",
1307 FLAG(cmd, PCI_COMMAND_IO),
1308 FLAG(cmd, PCI_COMMAND_MEMORY),
1309 FLAG(cmd, PCI_COMMAND_MASTER),
1310 FLAG(cmd, PCI_COMMAND_SPECIAL),
1311 FLAG(cmd, PCI_COMMAND_INVALIDATE),
1312 FLAG(cmd, PCI_COMMAND_VGA_PALETTE),
1313 FLAG(cmd, PCI_COMMAND_PARITY),
1314 FLAG(cmd, PCI_COMMAND_WAIT),
1315 FLAG(cmd, PCI_COMMAND_SERR),
1316 FLAG(cmd, PCI_COMMAND_FAST_BACK));
1317 printf("\tStatus: Cap%c 66Mhz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c\n",
1318 FLAG(status, PCI_STATUS_CAP_LIST),
1319 FLAG(status, PCI_STATUS_66MHZ),
1320 FLAG(status, PCI_STATUS_UDF),
1321 FLAG(status, PCI_STATUS_FAST_BACK),
1322 FLAG(status, PCI_STATUS_PARITY),
1323 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1324 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1325 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1326 FLAG(status, PCI_STATUS_SIG_TARGET_ABORT),
1327 FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
1328 FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
1329 FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
1330 FLAG(status, PCI_STATUS_DETECTED_PARITY));
1331 if (cmd & PCI_COMMAND_MASTER)
1333 printf("\tLatency: %d", latency);
1334 if (min_gnt || max_lat)
1338 printf("%dns min", min_gnt*250);
1339 if (min_gnt && max_lat)
1342 printf("%dns max", max_lat*250);
1346 printf(", Cache Line Size %02x", cache_line);
1350 printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n",
1351 (int_pin ? 'A' + int_pin - 1 : '?'), irq);
1355 printf("\tFlags: ");
1356 if (cmd & PCI_COMMAND_MASTER)
1357 printf("bus master, ");
1358 if (cmd & PCI_COMMAND_VGA_PALETTE)
1359 printf("VGA palette snoop, ");
1360 if (cmd & PCI_COMMAND_WAIT)
1361 printf("stepping, ");
1362 if (cmd & PCI_COMMAND_FAST_BACK)
1363 printf("fast Back2Back, ");
1364 if (status & PCI_STATUS_66MHZ)
1366 if (status & PCI_STATUS_UDF)
1367 printf("user-definable features, ");
1369 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1370 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1371 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??");
1372 if (cmd & PCI_COMMAND_MASTER)
1373 printf(", latency %d", latency);
1375 printf(", IRQ " PCIIRQ_FMT, irq);
1379 if (bist & PCI_BIST_CAPABLE)
1381 if (bist & PCI_BIST_START)
1382 printf("\tBIST is running\n");
1384 printf("\tBIST result: %02x\n", bist & PCI_BIST_CODE_MASK);
1389 case PCI_HEADER_TYPE_NORMAL:
1392 case PCI_HEADER_TYPE_BRIDGE:
1395 case PCI_HEADER_TYPE_CARDBUS:
1402 show_hex_dump(struct device *d)
1404 unsigned int i, cnt;
1406 cnt = d->config_cnt;
1407 if (show_hex >= 3 && config_fetch(d, cnt, 256-cnt))
1410 if (show_hex >= 4 && config_fetch(d, 256, 4096-256))
1414 for(i=0; i<cnt; i++)
1418 printf(" %02x", get_conf_byte(d, i));
1425 show_machine(struct device *d)
1427 struct pci_dev *p = d->dev;
1429 word sv_id=0, sd_id=0;
1430 char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
1432 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
1434 case PCI_HEADER_TYPE_NORMAL:
1435 sv_id = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1436 sd_id = get_conf_word(d, PCI_SUBSYSTEM_ID);
1438 case PCI_HEADER_TYPE_CARDBUS:
1439 sv_id = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1440 sd_id = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1446 printf("Device:\t");
1449 printf("Class:\t%s\n",
1450 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0));
1451 printf("Vendor:\t%s\n",
1452 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, 0, 0));
1453 printf("Device:\t%s\n",
1454 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, 0, 0));
1455 if (sv_id && sv_id != 0xffff)
1457 printf("SVendor:\t%s\n",
1458 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, sv_id, sd_id));
1459 printf("SDevice:\t%s\n",
1460 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1462 if (c = get_conf_byte(d, PCI_REVISION_ID))
1463 printf("Rev:\t%02x\n", c);
1464 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1465 printf("ProgIf:\t%02x\n", c);
1470 printf(" \"%s\" \"%s\" \"%s\"",
1471 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS,
1472 get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0),
1473 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR,
1474 p->vendor_id, p->device_id, 0, 0),
1475 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE,
1476 p->vendor_id, p->device_id, 0, 0));
1477 if (c = get_conf_byte(d, PCI_REVISION_ID))
1478 printf(" -r%02x", c);
1479 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1480 printf(" -p%02x", c);
1481 if (sv_id && sv_id != 0xffff)
1482 printf(" \"%s\" \"%s\"",
1483 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, sv_id, sd_id),
1484 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1486 printf(" \"\" \"\"");
1492 show_device(struct device *d)
1494 if (machine_readable)
1502 if (verbose || show_hex)
1511 for(d=first_dev; d; d=d->next)
1518 struct bridge *chain; /* Single-linked list of bridges */
1519 struct bridge *next, *child; /* Tree of bridges */
1520 struct bus *first_bus; /* List of busses connected to this bridge */
1521 unsigned int domain;
1522 unsigned int primary, secondary, subordinate; /* Bus numbers */
1523 struct device *br_dev;
1527 unsigned int domain;
1528 unsigned int number;
1529 struct bus *sibling;
1530 struct device *first_dev, **last_dev;
1533 static struct bridge host_bridge = { NULL, NULL, NULL, NULL, 0, ~0, 0, ~0, NULL };
1536 find_bus(struct bridge *b, unsigned int domain, unsigned int n)
1540 for(bus=b->first_bus; bus; bus=bus->sibling)
1541 if (bus->domain == domain && bus->number == n)
1547 new_bus(struct bridge *b, unsigned int domain, unsigned int n)
1549 struct bus *bus = xmalloc(sizeof(struct bus));
1551 bus = xmalloc(sizeof(struct bus));
1552 bus->domain = domain;
1554 bus->sibling = b->first_bus;
1555 bus->first_dev = NULL;
1556 bus->last_dev = &bus->first_dev;
1562 insert_dev(struct device *d, struct bridge *b)
1564 struct pci_dev *p = d->dev;
1567 if (! (bus = find_bus(b, p->domain, p->bus)))
1570 for(c=b->child; c; c=c->next)
1571 if (c->domain == p->domain && c->secondary <= p->bus && p->bus <= c->subordinate)
1576 bus = new_bus(b, p->domain, p->bus);
1578 /* Simple insertion at the end _does_ guarantee the correct order as the
1579 * original device list was sorted by (domain, bus, devfn) lexicographically
1580 * and all devices on the new list have the same bus number.
1583 bus->last_dev = &d->next;
1590 struct device *d, *d2;
1591 struct bridge **last_br, *b;
1593 /* Build list of bridges */
1595 last_br = &host_bridge.chain;
1596 for(d=first_dev; d; d=d->next)
1598 word class = get_conf_word(d, PCI_CLASS_DEVICE);
1599 byte ht = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1600 if (class == PCI_CLASS_BRIDGE_PCI &&
1601 (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS))
1603 b = xmalloc(sizeof(struct bridge));
1604 b->domain = d->dev->domain;
1605 if (ht == PCI_HEADER_TYPE_BRIDGE)
1607 b->primary = get_conf_byte(d, PCI_CB_PRIMARY_BUS);
1608 b->secondary = get_conf_byte(d, PCI_CB_CARD_BUS);
1609 b->subordinate = get_conf_byte(d, PCI_CB_SUBORDINATE_BUS);
1613 b->primary = get_conf_byte(d, PCI_PRIMARY_BUS);
1614 b->secondary = get_conf_byte(d, PCI_SECONDARY_BUS);
1615 b->subordinate = get_conf_byte(d, PCI_SUBORDINATE_BUS);
1618 last_br = &b->chain;
1619 b->next = b->child = NULL;
1620 b->first_bus = NULL;
1626 /* Create a bridge tree */
1628 for(b=&host_bridge; b; b=b->chain)
1630 struct bridge *c, *best;
1632 for(c=&host_bridge; c; c=c->chain)
1633 if (c != b && (c == &host_bridge || b->domain == c->domain) &&
1634 b->primary >= c->secondary && b->primary <= c->subordinate &&
1635 (!best || best->subordinate - best->primary > c->subordinate - c->primary))
1639 b->next = best->child;
1644 /* Insert secondary bus for each bridge */
1646 for(b=&host_bridge; b; b=b->chain)
1647 if (!find_bus(b, b->domain, b->secondary))
1648 new_bus(b, b->domain, b->secondary);
1650 /* Create bus structs and link devices */
1652 for(d=first_dev; d;)
1655 insert_dev(d, &host_bridge);
1661 print_it(byte *line, byte *p)
1665 fputs(line, stdout);
1666 for(p=line; *p; p++)
1667 if (*p == '+' || *p == '|')
1673 static void show_tree_bridge(struct bridge *, byte *, byte *);
1676 show_tree_dev(struct device *d, byte *line, byte *p)
1678 struct pci_dev *q = d->dev;
1682 p += sprintf(p, "%02x.%x", q->dev, q->func);
1683 for(b=&host_bridge; b; b=b->chain)
1686 if (b->secondary == b->subordinate)
1687 p += sprintf(p, "-[%04x:%02x]-", b->domain, b->secondary);
1689 p += sprintf(p, "-[%04x:%02x-%02x]-", b->domain, b->secondary, b->subordinate);
1690 show_tree_bridge(b, line, p);
1694 p += sprintf(p, " %s",
1695 pci_lookup_name(pacc, namebuf, sizeof(namebuf),
1696 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1697 q->vendor_id, q->device_id, 0, 0));
1702 show_tree_bus(struct bus *b, byte *line, byte *p)
1706 else if (!b->first_dev->next)
1710 show_tree_dev(b->first_dev, line, p);
1714 struct device *d = b->first_dev;
1719 show_tree_dev(d, line, p+2);
1724 show_tree_dev(d, line, p+2);
1729 show_tree_bridge(struct bridge *b, byte *line, byte *p)
1732 if (!b->first_bus->sibling)
1734 if (b == &host_bridge)
1735 p += sprintf(p, "[%04x:%02x]-", b->domain, b->first_bus->number);
1736 show_tree_bus(b->first_bus, line, p);
1740 struct bus *u = b->first_bus;
1745 k = p + sprintf(p, "+-[%04x:%02x]-", u->domain, u->number);
1746 show_tree_bus(u, line, k);
1749 k = p + sprintf(p, "\\-[%04x:%02x]-", u->domain, u->number);
1750 show_tree_bus(u, line, k);
1760 show_tree_bridge(&host_bridge, line, line);
1763 /* Bus mapping mode */
1766 struct bus_bridge *next;
1767 byte this, dev, func, first, last, bug;
1773 struct bus_bridge *bridges, *via;
1776 static struct bus_info *bus_info;
1779 map_bridge(struct bus_info *bi, struct device *d, int np, int ns, int nl)
1781 struct bus_bridge *b = xmalloc(sizeof(struct bus_bridge));
1782 struct pci_dev *p = d->dev;
1784 b->next = bi->bridges;
1786 b->this = get_conf_byte(d, np);
1789 b->first = get_conf_byte(d, ns);
1790 b->last = get_conf_byte(d, nl);
1791 printf("## %02x.%02x:%d is a bridge from %02x to %02x-%02x\n",
1792 p->bus, p->dev, p->func, b->this, b->first, b->last);
1793 if (b->this != p->bus)
1794 printf("!!! Bridge points to invalid primary bus.\n");
1795 if (b->first > b->last)
1797 printf("!!! Bridge points to invalid bus range.\n");
1806 int verbose = pacc->debugging;
1807 struct bus_info *bi = bus_info + bus;
1811 printf("Mapping bus %02x\n", bus);
1812 for(dev = 0; dev < 32; dev++)
1813 if (filter.slot < 0 || filter.slot == dev)
1816 for(func = 0; func < func_limit; func++)
1817 if (filter.func < 0 || filter.func == func)
1819 /* XXX: Bus mapping supports only domain 0 */
1820 struct pci_dev *p = pci_get_dev(pacc, 0, bus, dev, func);
1821 u16 vendor = pci_read_word(p, PCI_VENDOR_ID);
1822 if (vendor && vendor != 0xffff)
1824 if (!func && (pci_read_byte(p, PCI_HEADER_TYPE) & 0x80))
1827 printf("Discovered device %02x:%02x.%d\n", bus, dev, func);
1829 if (d = scan_device(p))
1832 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
1834 case PCI_HEADER_TYPE_BRIDGE:
1835 map_bridge(bi, d, PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS);
1837 case PCI_HEADER_TYPE_CARDBUS:
1838 map_bridge(bi, d, PCI_CB_PRIMARY_BUS, PCI_CB_CARD_BUS, PCI_CB_SUBORDINATE_BUS);
1844 printf("But it was filtered out.\n");
1852 do_map_bridges(int bus, int min, int max)
1854 struct bus_info *bi = bus_info + bus;
1855 struct bus_bridge *b;
1858 for(b=bi->bridges; b; b=b->next)
1860 if (bus_info[b->first].guestbook)
1862 else if (b->first < min || b->last > max)
1866 bus_info[b->first].via = b;
1867 do_map_bridges(b->first, b->first, b->last);
1877 printf("\nSummary of buses:\n\n");
1878 for(i=0; i<256; i++)
1879 if (bus_info[i].exists && !bus_info[i].guestbook)
1880 do_map_bridges(i, 0, 255);
1881 for(i=0; i<256; i++)
1883 struct bus_info *bi = bus_info + i;
1884 struct bus_bridge *b = bi->via;
1888 printf("%02x: ", i);
1890 printf("Entered via %02x:%02x.%d\n", b->this, b->dev, b->func);
1892 printf("Primary host bus\n");
1894 printf("Secondary host bus (?)\n");
1896 for(b=bi->bridges; b; b=b->next)
1898 printf("\t%02x.%d Bridge to %02x-%02x", b->dev, b->func, b->first, b->last);
1902 printf(" <overlap bug>");
1905 printf(" <crossing bug>");
1916 if (pacc->method == PCI_ACCESS_PROC_BUS_PCI ||
1917 pacc->method == PCI_ACCESS_DUMP)
1918 printf("WARNING: Bus mapping can be reliable only with direct hardware access enabled.\n\n");
1919 bus_info = xmalloc(sizeof(struct bus_info) * 256);
1920 bzero(bus_info, sizeof(struct bus_info) * 256);
1921 if (filter.bus >= 0)
1922 do_map_bus(filter.bus);
1926 for(bus=0; bus<256; bus++)
1935 main(int argc, char **argv)
1940 if (argc == 2 && !strcmp(argv[1], "--version"))
1942 puts("lspci version " PCIUTILS_VERSION);
1948 pci_filter_init(pacc, &filter);
1950 while ((i = getopt(argc, argv, options)) != -1)
1954 pacc->numeric_ids = 1;
1960 pacc->buscentric = 1;
1961 buscentric_view = 1;
1964 if (msg = pci_filter_parse_slot(&filter, optarg))
1968 if (msg = pci_filter_parse_id(&filter, optarg))
1978 pacc->id_file_name = optarg;
1987 if (parse_generic_option(i, pacc, optarg))
1990 fprintf(stderr, help_msg, pacc->id_file_name);