2 * The PCI Utilities -- List All PCI Devices
4 * Copyright (c) 1997--2005 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
19 static int verbose; /* Show detailed information */
20 static int buscentric_view; /* Show bus addresses/IRQ's instead of CPU-visible ones */
21 static int show_hex; /* Show contents of config space as hexadecimal numbers */
22 static struct pci_filter filter; /* Device filter */
23 static int show_tree; /* Show bus tree */
24 static int machine_readable; /* Generate machine-readable output */
25 static int map_mode; /* Bus mapping mode enabled */
27 static char options[] = "nvbxs:d:ti:mgM" GENERIC_OPTIONS ;
29 static char help_msg[] = "\
30 Usage: lspci [<switches>]\n\
33 -n\t\tShow numeric ID's\n\
34 -b\t\tBus-centric view (PCI addresses and IRQ's instead of those seen by the CPU)\n\
35 -x\t\tShow hex-dump of the standard portion of config space\n\
36 -xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n\
37 -xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n\
38 -s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n\
39 -d [<vendor>]:[<device>]\tShow only selected devices\n\
40 -t\t\tShow bus tree\n\
41 -m\t\tProduce machine-readable output\n\
42 -i <file>\tUse specified ID database instead of %s\n\
43 -M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
47 /* Communication with libpci */
49 static struct pci_access *pacc;
52 * If we aren't being compiled by GCC, use malloc() instead of alloca().
53 * This increases our memory footprint, but only slightly since we don't
61 /* Our view of the PCI bus */
66 unsigned int config_cnt, config_bufsize;
70 static struct device *first_dev;
73 config_fetch(struct device *d, unsigned int pos, unsigned int len)
75 unsigned int end = pos+len;
77 if (end <= d->config_cnt)
79 if (end > d->config_bufsize)
81 while (end > d->config_bufsize)
82 d->config_bufsize *= 2;
83 d->config = xrealloc(d->config, d->config_bufsize);
85 result = pci_read_block(d->dev, pos, d->config + pos, len);
86 if (result && pos == d->config_cnt)
91 static struct device *
92 scan_device(struct pci_dev *p)
96 if (!pci_filter_match(&filter, p))
98 d = xmalloc(sizeof(struct device));
101 d->config_cnt = d->config_bufsize = 64;
102 d->config = xmalloc(64);
103 if (!pci_read_block(p, 0, d->config, 64))
104 die("Unable to read the configuration space header.");
105 if ((d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
107 /* For cardbus bridges, we need to fetch 64 bytes more to get the
108 * full standard header... */
109 if (!config_fetch(d, 64, 64))
110 die("Unable to read cardbus bridge extension data.");
112 pci_setup_cache(p, d->config, d->config_cnt);
113 pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
124 for(p=pacc->devices; p; p=p->next)
125 if (d = scan_device(p))
132 /* Config space accesses */
135 get_conf_byte(struct device *d, unsigned int pos)
137 return d->config[pos];
141 get_conf_word(struct device *d, unsigned int pos)
143 return d->config[pos] | (d->config[pos+1] << 8);
147 get_conf_long(struct device *d, unsigned int pos)
149 return d->config[pos] |
150 (d->config[pos+1] << 8) |
151 (d->config[pos+2] << 16) |
152 (d->config[pos+3] << 24);
158 compare_them(const void *A, const void *B)
160 const struct pci_dev *a = (*(const struct device **)A)->dev;
161 const struct pci_dev *b = (*(const struct device **)B)->dev;
163 if (a->domain < b->domain)
165 if (a->domain > b->domain)
175 if (a->func < b->func)
177 if (a->func > b->func)
185 struct device **index, **h, **last_dev;
190 for(d=first_dev; d; d=d->next)
192 h = index = alloca(sizeof(struct device *) * cnt);
193 for(d=first_dev; d; d=d->next)
195 qsort(index, cnt, sizeof(struct device *), compare_them);
196 last_dev = &first_dev;
201 last_dev = &(*h)->next;
209 #define FLAG(x,y) ((x & y) ? '+' : '-')
212 show_slot_name(struct device *d)
214 struct pci_dev *p = d->dev;
217 printf("%04x:", p->domain);
218 printf("%02x:%02x.%d", p->bus, p->dev, p->func);
222 show_terse(struct device *d)
225 struct pci_dev *p = d->dev;
226 byte classbuf[128], devbuf[128];
230 pci_lookup_name(pacc, classbuf, sizeof(classbuf),
232 get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0),
233 pci_lookup_name(pacc, devbuf, sizeof(devbuf),
234 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
235 p->vendor_id, p->device_id, 0, 0));
236 if (c = get_conf_byte(d, PCI_REVISION_ID))
237 printf(" (rev %02x)", c);
241 c = get_conf_byte(d, PCI_CLASS_PROG);
242 x = pci_lookup_name(pacc, devbuf, sizeof(devbuf),
244 get_conf_word(d, PCI_CLASS_DEVICE), c, 0, 0);
247 printf(" (prog-if %02x", c);
257 show_size(pciaddr_t x)
263 printf("%d", (int) x);
264 else if (x < 1048576)
265 printf("%dK", (int)(x / 1024));
266 else if (x < 0x80000000)
267 printf("%dM", (int)(x / 1048576));
269 printf(PCIADDR_T_FMT, x);
274 show_bases(struct device *d, int cnt)
276 struct pci_dev *p = d->dev;
277 word cmd = get_conf_word(d, PCI_COMMAND);
282 pciaddr_t pos = p->base_addr[i];
283 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
284 u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
285 if (flg == 0xffffffff)
287 if (!pos && !flg && !len)
290 printf("\tRegion %d: ", i);
293 if (pos && !flg) /* Reported by the OS, but not by the device */
295 printf("[virtual] ");
298 if (flg & PCI_BASE_ADDRESS_SPACE_IO)
300 pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
301 printf("I/O ports at ");
303 printf(PCIADDR_PORT_FMT, a);
304 else if (flg & PCI_BASE_ADDRESS_IO_MASK)
307 printf("<unassigned>");
308 if (!(cmd & PCI_COMMAND_IO))
309 printf(" [disabled]");
313 int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
314 pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
318 printf("Memory at ");
319 if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
323 printf("<invalid-64bit-slot>");
329 z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
333 printf("%08x" PCIADDR_T_FMT, z, a);
335 printf("<unassigned>");
343 printf(PCIADDR_T_FMT, a);
345 printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
347 printf(" (%s, %sprefetchable)",
348 (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
349 (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
350 (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
351 (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
352 if (!(cmd & PCI_COMMAND_MEMORY))
353 printf(" [disabled]");
361 show_pm(struct device *d, int where, int cap)
364 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
366 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
369 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
370 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
371 FLAG(cap, PCI_PM_CAP_DSI),
372 FLAG(cap, PCI_PM_CAP_D1),
373 FLAG(cap, PCI_PM_CAP_D2),
374 pm_aux_current[(cap >> 6) & 7],
375 FLAG(cap, PCI_PM_CAP_PME_D0),
376 FLAG(cap, PCI_PM_CAP_PME_D1),
377 FLAG(cap, PCI_PM_CAP_PME_D2),
378 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
379 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
380 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
382 t = get_conf_word(d, where + PCI_PM_CTRL);
383 printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
384 t & PCI_PM_CTRL_STATE_MASK,
385 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
386 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
387 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
388 FLAG(t, PCI_PM_CTRL_PME_STATUS));
389 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
391 printf("\t\tBridge: PM%c B3%c\n",
392 FLAG(t, PCI_PM_BPCC_ENABLE),
393 FLAG(~t, PCI_PM_PPB_B2_B3));
397 format_agp_rate(int rate, char *buf, int agp3)
407 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
412 strcpy(buf, "<none>");
416 show_agp(struct device *d, int where, int cap)
423 ver = (cap >> 4) & 0x0f;
425 printf("AGP version %x.%x\n", ver, rev);
428 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
430 t = get_conf_long(d, where + PCI_AGP_STATUS);
431 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
433 format_agp_rate(t & 7, rate, agp3);
434 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
435 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
436 FLAG(t, PCI_AGP_STATUS_ISOCH),
437 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
438 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
439 FLAG(t, PCI_AGP_STATUS_SBA),
440 FLAG(t, PCI_AGP_STATUS_ITA_COH),
441 FLAG(t, PCI_AGP_STATUS_GART64),
442 FLAG(t, PCI_AGP_STATUS_HTRANS),
443 FLAG(t, PCI_AGP_STATUS_64BIT),
444 FLAG(t, PCI_AGP_STATUS_FW),
445 FLAG(t, PCI_AGP_STATUS_AGP3),
447 t = get_conf_long(d, where + PCI_AGP_COMMAND);
448 format_agp_rate(t & 7, rate, agp3);
449 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
450 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
451 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
452 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
453 FLAG(t, PCI_AGP_COMMAND_SBA),
454 FLAG(t, PCI_AGP_COMMAND_AGP),
455 FLAG(t, PCI_AGP_COMMAND_GART64),
456 FLAG(t, PCI_AGP_COMMAND_64BIT),
457 FLAG(t, PCI_AGP_COMMAND_FW),
462 show_pcix_nobridge(struct device *d, int where)
467 printf("PCI-X non-bridge device.\n");
472 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
475 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
476 status = get_conf_long(d, where + PCI_PCIX_STATUS);
477 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
478 FLAG(command, PCI_PCIX_COMMAND_DPERE),
479 FLAG(command, PCI_PCIX_COMMAND_ERO),
480 ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U),
481 ((command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U));
482 printf("\t\tStatus: Bus=%u Dev=%u Func=%u 64bit%c 133MHz%c SCD%c USC%c, DC=%s, DMMRBC=%u, DMOST=%u, DMCRS=%u, RSCEM%c\n",
483 ((status >> 8) & 0xffU), // bus
484 ((status >> 3) & 0x1fU), // dev
485 (status & PCI_PCIX_STATUS_FUNCTION), // function
486 FLAG(status, PCI_PCIX_STATUS_64BIT),
487 FLAG(status, PCI_PCIX_STATUS_133MHZ),
488 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
489 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
490 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
491 ((status >> 21) & 3U),
492 ((status >> 23) & 7U),
493 ((status >> 26) & 7U),
494 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS));
498 show_pcix_bridge(struct device *d, int where)
502 u32 status, upstcr, downstcr;
504 printf("PCI-X bridge device.\n");
509 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
512 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
513 printf("\t\tSecondary Status: 64bit%c, 133MHz%c, SCD%c, USC%c, SCO%c, SRD%c Freq=%d\n",
514 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
515 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
516 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
517 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
518 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
519 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
520 ((secstatus >> 6) & 7));
521 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
522 printf("\t\tStatus: Bus=%u Dev=%u Func=%u 64bit%c 133MHz%c SCD%c USC%c, SCO%c, SRD%c\n",
523 ((status >> 8) & 0xff), // bus
524 ((status >> 3) & 0x1f), // dev
525 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION), // function
526 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
527 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
528 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
529 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
530 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
531 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
532 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
533 printf("\t\t: Upstream: Capacity=%u, Commitment Limit=%u\n",
534 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
535 (upstcr >> 16) & 0xffff);
536 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
537 printf("\t\t: Downstream: Capacity=%u, Commitment Limit=%u\n",
538 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
539 (downstcr >> 16) & 0xffff);
543 show_pcix(struct device *d, int where)
545 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
547 case PCI_HEADER_TYPE_NORMAL:
548 show_pcix_nobridge(d, where);
550 case PCI_HEADER_TYPE_BRIDGE:
551 show_pcix_bridge(d, where);
557 ht_link_width(unsigned width)
559 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
560 return widths[width];
564 ht_link_freq(unsigned freq)
566 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
567 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
572 show_ht_pri(struct device *d, int where, int cmd)
574 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
575 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
578 printf("HyperTransport: Slave or Primary Interface\n");
582 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
584 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
585 if (rid < 0x23 && rid > 0x11)
586 printf("\t!!! Possibly incomplete decoding\n");
589 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
591 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
593 (cmd & PCI_HT_PRI_CMD_BUID),
594 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
595 FLAG(cmd, PCI_HT_PRI_CMD_MH),
596 FLAG(cmd, PCI_HT_PRI_CMD_DD),
597 FLAG(cmd, PCI_HT_PRI_CMD_DUL));
598 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
600 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
602 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
604 FLAG(lctr0, PCI_HT_LCTR_CFLE),
605 FLAG(lctr0, PCI_HT_LCTR_CST),
606 FLAG(lctr0, PCI_HT_LCTR_CFE),
607 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
608 FLAG(lctr0, PCI_HT_LCTR_INIT),
609 FLAG(lctr0, PCI_HT_LCTR_EOC),
610 FLAG(lctr0, PCI_HT_LCTR_TXO),
611 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
612 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
613 FLAG(lctr0, PCI_HT_LCTR_LSEN),
614 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
615 FLAG(lctr0, PCI_HT_LCTR_64B));
616 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
618 fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
620 fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
622 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
623 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
624 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
625 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
626 FLAG(lcnf0, PCI_HT_LCNF_DFI),
627 FLAG(lcnf0, PCI_HT_LCNF_DFO),
628 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
629 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
630 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
632 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
634 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
636 FLAG(lctr1, PCI_HT_LCTR_CFLE),
637 FLAG(lctr1, PCI_HT_LCTR_CST),
638 FLAG(lctr1, PCI_HT_LCTR_CFE),
639 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
640 FLAG(lctr1, PCI_HT_LCTR_INIT),
641 FLAG(lctr1, PCI_HT_LCTR_EOC),
642 FLAG(lctr1, PCI_HT_LCTR_TXO),
643 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
644 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
645 FLAG(lctr1, PCI_HT_LCTR_LSEN),
646 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
647 FLAG(lctr1, PCI_HT_LCTR_64B));
648 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
650 fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
652 fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
654 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
655 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
656 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
657 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
658 FLAG(lcnf1, PCI_HT_LCNF_DFI),
659 FLAG(lcnf1, PCI_HT_LCNF_DFO),
660 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
661 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
662 printf("\t\tRevision ID: %u.%02u\n",
663 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
666 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
667 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
668 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
669 FLAG(lfrer0, PCI_HT_LFRER_PROT),
670 FLAG(lfrer0, PCI_HT_LFRER_OV),
671 FLAG(lfrer0, PCI_HT_LFRER_EOC),
672 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
673 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
674 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
675 FLAG(lfcap0, PCI_HT_LFCAP_200),
676 FLAG(lfcap0, PCI_HT_LFCAP_300),
677 FLAG(lfcap0, PCI_HT_LFCAP_400),
678 FLAG(lfcap0, PCI_HT_LFCAP_500),
679 FLAG(lfcap0, PCI_HT_LFCAP_600),
680 FLAG(lfcap0, PCI_HT_LFCAP_800),
681 FLAG(lfcap0, PCI_HT_LFCAP_1000),
682 FLAG(lfcap0, PCI_HT_LFCAP_1200),
683 FLAG(lfcap0, PCI_HT_LFCAP_1400),
684 FLAG(lfcap0, PCI_HT_LFCAP_1600),
685 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
686 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
687 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
688 FLAG(ftr, PCI_HT_FTR_ISOCFC),
689 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
690 FLAG(ftr, PCI_HT_FTR_CRCTM),
691 FLAG(ftr, PCI_HT_FTR_ECTLT),
692 FLAG(ftr, PCI_HT_FTR_64BA),
693 FLAG(ftr, PCI_HT_FTR_UIDRD));
694 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
695 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
696 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
697 FLAG(lfrer1, PCI_HT_LFRER_PROT),
698 FLAG(lfrer1, PCI_HT_LFRER_OV),
699 FLAG(lfrer1, PCI_HT_LFRER_EOC),
700 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
701 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
702 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
703 FLAG(lfcap1, PCI_HT_LFCAP_200),
704 FLAG(lfcap1, PCI_HT_LFCAP_300),
705 FLAG(lfcap1, PCI_HT_LFCAP_400),
706 FLAG(lfcap1, PCI_HT_LFCAP_500),
707 FLAG(lfcap1, PCI_HT_LFCAP_600),
708 FLAG(lfcap1, PCI_HT_LFCAP_800),
709 FLAG(lfcap1, PCI_HT_LFCAP_1000),
710 FLAG(lfcap1, PCI_HT_LFCAP_1200),
711 FLAG(lfcap1, PCI_HT_LFCAP_1400),
712 FLAG(lfcap1, PCI_HT_LFCAP_1600),
713 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
714 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
715 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
716 FLAG(eh, PCI_HT_EH_PFLE),
717 FLAG(eh, PCI_HT_EH_OFLE),
718 FLAG(eh, PCI_HT_EH_PFE),
719 FLAG(eh, PCI_HT_EH_OFE),
720 FLAG(eh, PCI_HT_EH_EOCFE),
721 FLAG(eh, PCI_HT_EH_RFE),
722 FLAG(eh, PCI_HT_EH_CRCFE),
723 FLAG(eh, PCI_HT_EH_SERRFE),
724 FLAG(eh, PCI_HT_EH_CF),
725 FLAG(eh, PCI_HT_EH_RE),
726 FLAG(eh, PCI_HT_EH_PNFE),
727 FLAG(eh, PCI_HT_EH_ONFE),
728 FLAG(eh, PCI_HT_EH_EOCNFE),
729 FLAG(eh, PCI_HT_EH_RNFE),
730 FLAG(eh, PCI_HT_EH_CRCNFE),
731 FLAG(eh, PCI_HT_EH_SERRNFE));
732 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
733 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
734 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
735 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
736 printf("\t\tBus Number: %02x\n", bn);
740 show_ht_sec(struct device *d, int where, int cmd)
742 u16 lctr, lcnf, ftr, eh;
743 u8 rid, lfrer, lfcap, mbu, mlu;
746 printf("HyperTransport: Host or Secondary Interface\n");
750 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
752 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
753 if (rid < 0x23 && rid > 0x11)
754 printf("\t!!! Possibly incomplete decoding\n");
757 fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
759 fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
761 FLAG(cmd, PCI_HT_SEC_CMD_WR),
762 FLAG(cmd, PCI_HT_SEC_CMD_DE),
763 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
764 FLAG(cmd, PCI_HT_SEC_CMD_CS),
765 FLAG(cmd, PCI_HT_SEC_CMD_HH),
766 FLAG(cmd, PCI_HT_SEC_CMD_AS),
767 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
768 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
769 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
771 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
773 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
775 FLAG(lctr, PCI_HT_LCTR_CFLE),
776 FLAG(lctr, PCI_HT_LCTR_CST),
777 FLAG(lctr, PCI_HT_LCTR_CFE),
778 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
779 FLAG(lctr, PCI_HT_LCTR_INIT),
780 FLAG(lctr, PCI_HT_LCTR_EOC),
781 FLAG(lctr, PCI_HT_LCTR_TXO),
782 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
783 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
784 FLAG(lctr, PCI_HT_LCTR_LSEN),
785 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
786 FLAG(lctr, PCI_HT_LCTR_64B));
787 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
789 fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
791 fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
793 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
794 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
795 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
796 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
797 FLAG(lcnf, PCI_HT_LCNF_DFI),
798 FLAG(lcnf, PCI_HT_LCNF_DFO),
799 FLAG(lcnf, PCI_HT_LCNF_DFIE),
800 FLAG(lcnf, PCI_HT_LCNF_DFOE));
801 printf("\t\tRevision ID: %u.%02u\n",
802 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
805 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
806 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
807 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
808 FLAG(lfrer, PCI_HT_LFRER_PROT),
809 FLAG(lfrer, PCI_HT_LFRER_OV),
810 FLAG(lfrer, PCI_HT_LFRER_EOC),
811 FLAG(lfrer, PCI_HT_LFRER_CTLT));
812 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
813 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
814 FLAG(lfcap, PCI_HT_LFCAP_200),
815 FLAG(lfcap, PCI_HT_LFCAP_300),
816 FLAG(lfcap, PCI_HT_LFCAP_400),
817 FLAG(lfcap, PCI_HT_LFCAP_500),
818 FLAG(lfcap, PCI_HT_LFCAP_600),
819 FLAG(lfcap, PCI_HT_LFCAP_800),
820 FLAG(lfcap, PCI_HT_LFCAP_1000),
821 FLAG(lfcap, PCI_HT_LFCAP_1200),
822 FLAG(lfcap, PCI_HT_LFCAP_1400),
823 FLAG(lfcap, PCI_HT_LFCAP_1600),
824 FLAG(lfcap, PCI_HT_LFCAP_VEND));
825 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
826 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
827 FLAG(ftr, PCI_HT_FTR_ISOCFC),
828 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
829 FLAG(ftr, PCI_HT_FTR_CRCTM),
830 FLAG(ftr, PCI_HT_FTR_ECTLT),
831 FLAG(ftr, PCI_HT_FTR_64BA),
832 FLAG(ftr, PCI_HT_FTR_UIDRD),
833 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
834 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
835 if (ftr & PCI_HT_SEC_FTR_EXTRS)
837 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
838 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
839 FLAG(eh, PCI_HT_EH_PFLE),
840 FLAG(eh, PCI_HT_EH_OFLE),
841 FLAG(eh, PCI_HT_EH_PFE),
842 FLAG(eh, PCI_HT_EH_OFE),
843 FLAG(eh, PCI_HT_EH_EOCFE),
844 FLAG(eh, PCI_HT_EH_RFE),
845 FLAG(eh, PCI_HT_EH_CRCFE),
846 FLAG(eh, PCI_HT_EH_SERRFE),
847 FLAG(eh, PCI_HT_EH_CF),
848 FLAG(eh, PCI_HT_EH_RE),
849 FLAG(eh, PCI_HT_EH_PNFE),
850 FLAG(eh, PCI_HT_EH_ONFE),
851 FLAG(eh, PCI_HT_EH_EOCNFE),
852 FLAG(eh, PCI_HT_EH_RNFE),
853 FLAG(eh, PCI_HT_EH_CRCNFE),
854 FLAG(eh, PCI_HT_EH_SERRNFE));
855 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
856 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
857 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
862 show_ht(struct device *d, int where, int cmd)
866 switch (cmd & PCI_HT_CMD_TYP_HI)
868 case PCI_HT_CMD_TYP_HI_PRI:
869 show_ht_pri(d, where, cmd);
871 case PCI_HT_CMD_TYP_HI_SEC:
872 show_ht_sec(d, where, cmd);
876 type = cmd & PCI_HT_CMD_TYP;
879 case PCI_HT_CMD_TYP_SW:
880 printf("HyperTransport: Switch\n");
882 case PCI_HT_CMD_TYP_IDC:
883 printf("HyperTransport: Interrupt Discovery and Configuration\n");
885 case PCI_HT_CMD_TYP_RID:
886 printf("HyperTransport: Revision ID: %u.%02u\n",
887 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
889 case PCI_HT_CMD_TYP_UIDC:
890 printf("HyperTransport: UnitID Clumping\n");
892 case PCI_HT_CMD_TYP_ECSA:
893 printf("HyperTransport: Extended Configuration Space Access\n");
895 case PCI_HT_CMD_TYP_AM:
896 printf("HyperTransport: Address Mapping\n");
898 case PCI_HT_CMD_TYP_MSIM:
899 printf("HyperTransport: MSI Mapping\n");
901 case PCI_HT_CMD_TYP_DR:
902 printf("HyperTransport: DirectRoute\n");
904 case PCI_HT_CMD_TYP_VCS:
905 printf("HyperTransport: VCSet\n");
907 case PCI_HT_CMD_TYP_RM:
908 printf("HyperTransport: Retry Mode\n");
910 case PCI_HT_CMD_TYP_X86:
911 printf("HyperTransport: X86 (reserved)\n");
914 printf("HyperTransport: #%02x\n", type >> 11);
919 show_rom(struct device *d, int reg)
921 struct pci_dev *p = d->dev;
922 pciaddr_t rom = p->rom_base_addr;
923 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
924 u32 flg = get_conf_long(d, reg);
925 word cmd = get_conf_word(d, PCI_COMMAND);
927 if (!rom && !flg && !len)
930 if ((rom & PCI_ROM_ADDRESS_MASK) && !(flg & PCI_ROM_ADDRESS_MASK))
932 printf("[virtual] ");
935 printf("Expansion ROM at ");
936 if (rom & PCI_ROM_ADDRESS_MASK)
937 printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
938 else if (flg & PCI_ROM_ADDRESS_MASK)
941 printf("<unassigned>");
942 if (!(flg & PCI_ROM_ADDRESS_ENABLE))
943 printf(" [disabled]");
944 else if (!(cmd & PCI_COMMAND_MEMORY))
945 printf(" [disabled by cmd]");
951 show_msi(struct device *d, int where, int cap)
957 printf("Message Signalled Interrupts: 64bit%c Queue=%d/%d Enable%c\n",
958 FLAG(cap, PCI_MSI_FLAGS_64BIT),
959 (cap & PCI_MSI_FLAGS_QSIZE) >> 4,
960 (cap & PCI_MSI_FLAGS_QMASK) >> 1,
961 FLAG(cap, PCI_MSI_FLAGS_ENABLE));
964 is64 = cap & PCI_MSI_FLAGS_64BIT;
965 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
967 printf("\t\tAddress: ");
970 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
971 w = get_conf_word(d, where + PCI_MSI_DATA_64);
975 w = get_conf_word(d, where + PCI_MSI_DATA_32);
976 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
977 printf("%08x Data: %04x\n", t, w);
980 static void show_vendor(void)
982 printf("Vendor Specific Information\n");
985 static void show_debug(void)
987 printf("Debug port\n");
990 static float power_limit(int value, int scale)
992 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
993 return value * scales[scale];
996 static const char *latency_l0s(int value)
998 static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
999 return latencies[value];
1002 static const char *latency_l1(int value)
1004 static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
1005 return latencies[value];
1008 static void show_express_dev(struct device *d, int where, int type)
1013 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
1014 printf("\t\tDevice: Supported: MaxPayload %d bytes, PhantFunc %d, ExtTag%c\n",
1015 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
1016 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
1017 FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
1018 printf("\t\tDevice: Latency L0s %s, L1 %s\n",
1019 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
1020 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
1021 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
1022 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
1023 printf("\t\tDevice: AtnBtn%c AtnInd%c PwrInd%c\n",
1024 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
1025 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
1026 if (type == PCI_EXP_TYPE_UPSTREAM)
1027 printf("\t\tDevice: SlotPowerLimit %f\n",
1028 power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
1029 (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
1031 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
1032 printf("\t\tDevice: Errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
1033 FLAG(w, PCI_EXP_DEVCTL_CERE),
1034 FLAG(w, PCI_EXP_DEVCTL_NFERE),
1035 FLAG(w, PCI_EXP_DEVCTL_FERE),
1036 FLAG(w, PCI_EXP_DEVCTL_URRE));
1037 printf("\t\tDevice: RlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c\n",
1038 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
1039 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
1040 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
1041 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
1042 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
1043 printf("\t\tDevice: MaxPayload %d bytes, MaxReadReq %d bytes\n",
1044 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
1045 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
1048 static char *link_speed(int speed)
1059 static char *aspm_support(int code)
1072 static const char *aspm_enabled(int code)
1074 static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
1078 static void show_express_link(struct device *d, int where, int type)
1083 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
1084 printf("\t\tLink: Supported Speed %s, Width x%d, ASPM %s, Port %d\n",
1085 link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
1086 aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
1088 printf("\t\tLink: Latency L0s %s, L1 %s\n",
1089 latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
1090 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
1091 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
1092 printf("\t\tLink: ASPM %s", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
1093 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
1094 (type == PCI_EXP_TYPE_LEG_END))
1095 printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
1096 if (w & PCI_EXP_LNKCTL_DISABLE)
1097 printf(" Disabled");
1098 printf(" CommClk%c ExtSynch%c\n", FLAG(w, PCI_EXP_LNKCTL_CLOCK),
1099 FLAG(w, PCI_EXP_LNKCTL_XSYNCH));
1100 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
1101 printf("\t\tLink: Speed %s, Width x%d\n",
1102 link_speed(t & PCI_EXP_LNKSTA_SPEED), (t & PCI_EXP_LNKSTA_WIDTH) >> 4);
1105 static const char *indicator(int code)
1107 static const char *names[] = { "Unknown", "On", "Blink", "Off" };
1111 static void show_express_slot(struct device *d, int where)
1116 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
1117 printf("\t\tSlot: AtnBtn%c PwrCtrl%c MRL%c AtnInd%c PwrInd%c HotPlug%c Surpise%c\n",
1118 FLAG(t, PCI_EXP_SLTCAP_ATNB),
1119 FLAG(t, PCI_EXP_SLTCAP_PWRC),
1120 FLAG(t, PCI_EXP_SLTCAP_MRL),
1121 FLAG(t, PCI_EXP_SLTCAP_ATNI),
1122 FLAG(t, PCI_EXP_SLTCAP_PWRI),
1123 FLAG(t, PCI_EXP_SLTCAP_HPC),
1124 FLAG(t, PCI_EXP_SLTCAP_HPS));
1125 printf("\t\tSlot: Number %d, PowerLimit %f\n", t >> 19,
1126 power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7,
1127 (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15));
1128 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
1129 printf("\t\tSlot: Enabled AtnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c\n",
1130 FLAG(w, PCI_EXP_SLTCTL_ATNB),
1131 FLAG(w, PCI_EXP_SLTCTL_PWRF),
1132 FLAG(w, PCI_EXP_SLTCTL_MRLS),
1133 FLAG(w, PCI_EXP_SLTCTL_PRSD),
1134 FLAG(w, PCI_EXP_SLTCTL_CMDC),
1135 FLAG(w, PCI_EXP_SLTCTL_HPIE));
1136 printf("\t\tSlot: AttnInd %s, PwrInd %s, Power%c\n",
1137 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
1138 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
1139 FLAG(w, w & PCI_EXP_SLTCTL_PWRC));
1142 static void show_express_root(struct device *d, int where)
1144 u16 w = get_conf_word(d, where + PCI_EXP_RTCTL);
1145 printf("\t\tRoot: Correctable%c Non-Fatal%c Fatal%c PME%c\n",
1146 FLAG(w, PCI_EXP_RTCTL_SECEE),
1147 FLAG(w, PCI_EXP_RTCTL_SENFEE),
1148 FLAG(w, PCI_EXP_RTCTL_SEFEE),
1149 FLAG(w, PCI_EXP_RTCTL_PMEIE));
1153 show_express(struct device *d, int where, int cap)
1155 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1162 case PCI_EXP_TYPE_ENDPOINT:
1165 case PCI_EXP_TYPE_LEG_END:
1166 printf("Legacy Endpoint");
1168 case PCI_EXP_TYPE_ROOT_PORT:
1169 slot = cap & PCI_EXP_FLAGS_SLOT;
1170 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1172 case PCI_EXP_TYPE_UPSTREAM:
1173 printf("Upstream Port");
1175 case PCI_EXP_TYPE_DOWNSTREAM:
1176 slot = cap & PCI_EXP_FLAGS_SLOT;
1177 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1179 case PCI_EXP_TYPE_PCI_BRIDGE:
1180 printf("PCI/PCI-X Bridge");
1183 printf("Unknown type");
1185 printf(" IRQ %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1192 if (type == PCI_EXP_TYPE_ROOT_PORT)
1194 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1197 show_express_dev(d, where, type);
1198 show_express_link(d, where, type);
1200 show_express_slot(d, where);
1201 if (type == PCI_EXP_TYPE_ROOT_PORT)
1202 show_express_root(d, where);
1206 show_msix(struct device *d, int where, int cap)
1210 printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
1211 FLAG(cap, PCI_MSIX_ENABLE),
1212 FLAG(cap, PCI_MSIX_MASK),
1213 (cap & PCI_MSIX_TABSIZE) + 1);
1214 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1217 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1218 printf("\t\tVector table: BAR=%d offset=%08x\n",
1219 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1220 off = get_conf_long(d, where + PCI_MSIX_PBA);
1221 printf("\t\tPBA: BAR=%d offset=%08x\n",
1222 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1226 show_slotid(int cap)
1228 int esr = cap & 0xff;
1231 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1232 esr & PCI_SID_ESR_NSLOTS,
1233 FLAG(esr, PCI_SID_ESR_FIC),
1238 show_aer(struct device *d, int where)
1240 printf("Advanced Error Reporting\n");
1244 show_vc(struct device *d, int where)
1246 printf("Virtual Channel\n");
1250 show_dsn(struct device *d, int where)
1253 if (!config_fetch(d, where + 4, 8))
1255 t1 = get_conf_long(d, where + 4);
1256 t2 = get_conf_long(d, where + 8);
1257 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
1258 t1 & 0xff, (t1 >> 8) & 0xff, (t1 >> 16) & 0xff, t1 >> 24,
1259 t2 & 0xff, (t2 >> 8) & 0xff, (t2 >> 16) & 0xff, t2 >> 24);
1263 show_pb(struct device *d, int where)
1265 printf("Power Budgeting\n");
1269 show_ext_caps(struct device *d)
1277 if (!config_fetch(d, where, 4))
1279 header = get_conf_long(d, where);
1282 id = header & 0xffff;
1283 printf("\tCapabilities: [%03x] ", where);
1286 case PCI_EXT_CAP_ID_AER:
1289 case PCI_EXT_CAP_ID_VC:
1292 case PCI_EXT_CAP_ID_DSN:
1295 case PCI_EXT_CAP_ID_PB:
1299 printf("Unknown (%d)\n", id);
1302 where = header >> 20;
1307 show_caps(struct device *d)
1309 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1311 int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
1315 printf("\tCapabilities: ");
1316 if (!config_fetch(d, where, 4))
1318 puts("<available only to root>");
1321 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1322 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1323 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1324 printf("[%02x] ", where);
1327 printf("<chain broken>\n");
1333 show_pm(d, where, cap);
1335 case PCI_CAP_ID_AGP:
1336 show_agp(d, where, cap);
1338 case PCI_CAP_ID_VPD:
1339 printf("Vital Product Data\n");
1341 case PCI_CAP_ID_SLOTID:
1344 case PCI_CAP_ID_MSI:
1345 show_msi(d, where, cap);
1347 case PCI_CAP_ID_PCIX:
1348 show_pcix(d, where);
1351 show_ht(d, where, cap);
1353 case PCI_CAP_ID_VNDR:
1356 case PCI_CAP_ID_DBG:
1359 case PCI_CAP_ID_EXP:
1360 show_express(d, where, cap);
1362 case PCI_CAP_ID_MSIX:
1363 show_msix(d, where, cap);
1366 printf("#%02x [%04x]\n", id, cap);
1375 show_htype0(struct device *d)
1378 show_rom(d, PCI_ROM_ADDRESS);
1383 show_htype1(struct device *d)
1385 u32 io_base = get_conf_byte(d, PCI_IO_BASE);
1386 u32 io_limit = get_conf_byte(d, PCI_IO_LIMIT);
1387 u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
1388 u32 mem_base = get_conf_word(d, PCI_MEMORY_BASE);
1389 u32 mem_limit = get_conf_word(d, PCI_MEMORY_LIMIT);
1390 u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
1391 u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE);
1392 u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT);
1393 u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
1394 word sec_stat = get_conf_word(d, PCI_SEC_STATUS);
1395 word brc = get_conf_word(d, PCI_BRIDGE_CONTROL);
1396 int verb = verbose > 2;
1399 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1400 get_conf_byte(d, PCI_PRIMARY_BUS),
1401 get_conf_byte(d, PCI_SECONDARY_BUS),
1402 get_conf_byte(d, PCI_SUBORDINATE_BUS),
1403 get_conf_byte(d, PCI_SEC_LATENCY_TIMER));
1405 if (io_type != (io_limit & PCI_IO_RANGE_TYPE_MASK) ||
1406 (io_type != PCI_IO_RANGE_TYPE_16 && io_type != PCI_IO_RANGE_TYPE_32))
1407 printf("\t!!! Unknown I/O range types %x/%x\n", io_base, io_limit);
1410 io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
1411 io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
1412 if (io_type == PCI_IO_RANGE_TYPE_32)
1414 io_base |= (get_conf_word(d, PCI_IO_BASE_UPPER16) << 16);
1415 io_limit |= (get_conf_word(d, PCI_IO_LIMIT_UPPER16) << 16);
1417 if (io_base <= io_limit || verb)
1418 printf("\tI/O behind bridge: %08x-%08x\n", io_base, io_limit+0xfff);
1421 if (mem_type != (mem_limit & PCI_MEMORY_RANGE_TYPE_MASK) ||
1423 printf("\t!!! Unknown memory range types %x/%x\n", mem_base, mem_limit);
1426 mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
1427 mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
1428 if (mem_base <= mem_limit || verb)
1429 printf("\tMemory behind bridge: %08x-%08x\n", mem_base, mem_limit + 0xfffff);
1432 if (pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
1433 (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64))
1434 printf("\t!!! Unknown prefetchable memory range types %x/%x\n", pref_base, pref_limit);
1437 pref_base = (pref_base & PCI_PREF_RANGE_MASK) << 16;
1438 pref_limit = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
1439 if (pref_base <= pref_limit || verb)
1441 if (pref_type == PCI_PREF_RANGE_TYPE_32)
1442 printf("\tPrefetchable memory behind bridge: %08x-%08x\n", pref_base, pref_limit + 0xfffff);
1444 printf("\tPrefetchable memory behind bridge: %08x%08x-%08x%08x\n",
1445 get_conf_long(d, PCI_PREF_BASE_UPPER32),
1447 get_conf_long(d, PCI_PREF_LIMIT_UPPER32),
1453 printf("\tSecondary status: 66MHz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c\n",
1454 FLAG(sec_stat, PCI_STATUS_66MHZ),
1455 FLAG(sec_stat, PCI_STATUS_FAST_BACK),
1456 FLAG(sec_stat, PCI_STATUS_PARITY),
1457 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1458 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1459 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1460 FLAG(sec_stat, PCI_STATUS_SIG_TARGET_ABORT),
1461 FLAG(sec_stat, PCI_STATUS_REC_TARGET_ABORT),
1462 FLAG(sec_stat, PCI_STATUS_REC_MASTER_ABORT),
1463 FLAG(sec_stat, PCI_STATUS_SIG_SYSTEM_ERROR),
1464 FLAG(sec_stat, PCI_STATUS_DETECTED_PARITY));
1466 show_rom(d, PCI_ROM_ADDRESS1);
1469 printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
1470 FLAG(brc, PCI_BRIDGE_CTL_PARITY),
1471 FLAG(brc, PCI_BRIDGE_CTL_SERR),
1472 FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
1473 FLAG(brc, PCI_BRIDGE_CTL_VGA),
1474 FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
1475 FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
1476 FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
1482 show_htype2(struct device *d)
1485 word cmd = get_conf_word(d, PCI_COMMAND);
1486 word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
1487 word exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
1488 int verb = verbose > 2;
1491 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1492 get_conf_byte(d, PCI_CB_PRIMARY_BUS),
1493 get_conf_byte(d, PCI_CB_CARD_BUS),
1494 get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
1495 get_conf_byte(d, PCI_CB_LATENCY_TIMER));
1499 u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
1500 u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
1501 if (limit > base || verb)
1502 printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
1503 (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
1504 (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
1509 u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
1510 u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
1511 if (!(base & PCI_IO_RANGE_TYPE_32))
1516 base &= PCI_CB_IO_RANGE_MASK;
1517 limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
1518 if (base <= limit || verb)
1519 printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
1520 (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
1523 if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
1524 printf("\tSecondary status: SERR\n");
1526 printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
1527 FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
1528 FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
1529 FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
1530 FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
1531 FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
1532 FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
1533 FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
1534 FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
1536 printf("\t16-bit legacy interface ports at %04x\n", exca);
1540 show_verbose(struct device *d)
1542 struct pci_dev *p = d->dev;
1543 word status = get_conf_word(d, PCI_STATUS);
1544 word cmd = get_conf_word(d, PCI_COMMAND);
1545 word class = get_conf_word(d, PCI_CLASS_DEVICE);
1546 byte bist = get_conf_byte(d, PCI_BIST);
1547 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1548 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
1549 byte cache_line = get_conf_byte(d, PCI_CACHE_LINE_SIZE);
1550 byte max_lat, min_gnt;
1551 byte int_pin = get_conf_byte(d, PCI_INTERRUPT_PIN);
1552 unsigned int irq = p->irq;
1553 word subsys_v, subsys_d;
1554 char ssnamebuf[256];
1560 case PCI_HEADER_TYPE_NORMAL:
1561 if (class == PCI_CLASS_BRIDGE_PCI)
1562 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1563 max_lat = get_conf_byte(d, PCI_MAX_LAT);
1564 min_gnt = get_conf_byte(d, PCI_MIN_GNT);
1565 subsys_v = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1566 subsys_d = get_conf_word(d, PCI_SUBSYSTEM_ID);
1568 case PCI_HEADER_TYPE_BRIDGE:
1569 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1570 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1571 irq = int_pin = min_gnt = max_lat = 0;
1572 subsys_v = subsys_d = 0;
1574 case PCI_HEADER_TYPE_CARDBUS:
1575 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1576 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1577 min_gnt = max_lat = 0;
1578 subsys_v = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1579 subsys_d = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1582 printf("\t!!! Unknown header type %02x\n", htype);
1586 if (subsys_v && subsys_v != 0xffff)
1587 printf("\tSubsystem: %s\n",
1588 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1589 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1590 p->vendor_id, p->device_id, subsys_v, subsys_d));
1594 printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c\n",
1595 FLAG(cmd, PCI_COMMAND_IO),
1596 FLAG(cmd, PCI_COMMAND_MEMORY),
1597 FLAG(cmd, PCI_COMMAND_MASTER),
1598 FLAG(cmd, PCI_COMMAND_SPECIAL),
1599 FLAG(cmd, PCI_COMMAND_INVALIDATE),
1600 FLAG(cmd, PCI_COMMAND_VGA_PALETTE),
1601 FLAG(cmd, PCI_COMMAND_PARITY),
1602 FLAG(cmd, PCI_COMMAND_WAIT),
1603 FLAG(cmd, PCI_COMMAND_SERR),
1604 FLAG(cmd, PCI_COMMAND_FAST_BACK));
1605 printf("\tStatus: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c\n",
1606 FLAG(status, PCI_STATUS_CAP_LIST),
1607 FLAG(status, PCI_STATUS_66MHZ),
1608 FLAG(status, PCI_STATUS_UDF),
1609 FLAG(status, PCI_STATUS_FAST_BACK),
1610 FLAG(status, PCI_STATUS_PARITY),
1611 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1612 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1613 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1614 FLAG(status, PCI_STATUS_SIG_TARGET_ABORT),
1615 FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
1616 FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
1617 FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
1618 FLAG(status, PCI_STATUS_DETECTED_PARITY));
1619 if (cmd & PCI_COMMAND_MASTER)
1621 printf("\tLatency: %d", latency);
1622 if (min_gnt || max_lat)
1626 printf("%dns min", min_gnt*250);
1627 if (min_gnt && max_lat)
1630 printf("%dns max", max_lat*250);
1634 printf(", Cache Line Size %02x", cache_line);
1638 printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n",
1639 (int_pin ? 'A' + int_pin - 1 : '?'), irq);
1643 printf("\tFlags: ");
1644 if (cmd & PCI_COMMAND_MASTER)
1645 printf("bus master, ");
1646 if (cmd & PCI_COMMAND_VGA_PALETTE)
1647 printf("VGA palette snoop, ");
1648 if (cmd & PCI_COMMAND_WAIT)
1649 printf("stepping, ");
1650 if (cmd & PCI_COMMAND_FAST_BACK)
1651 printf("fast Back2Back, ");
1652 if (status & PCI_STATUS_66MHZ)
1654 if (status & PCI_STATUS_UDF)
1655 printf("user-definable features, ");
1657 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1658 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1659 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??");
1660 if (cmd & PCI_COMMAND_MASTER)
1661 printf(", latency %d", latency);
1663 printf(", IRQ " PCIIRQ_FMT, irq);
1667 if (bist & PCI_BIST_CAPABLE)
1669 if (bist & PCI_BIST_START)
1670 printf("\tBIST is running\n");
1672 printf("\tBIST result: %02x\n", bist & PCI_BIST_CODE_MASK);
1677 case PCI_HEADER_TYPE_NORMAL:
1680 case PCI_HEADER_TYPE_BRIDGE:
1683 case PCI_HEADER_TYPE_CARDBUS:
1690 show_hex_dump(struct device *d)
1692 unsigned int i, cnt;
1694 cnt = d->config_cnt;
1695 if (show_hex >= 3 && config_fetch(d, cnt, 256-cnt))
1698 if (show_hex >= 4 && config_fetch(d, 256, 4096-256))
1702 for(i=0; i<cnt; i++)
1706 printf(" %02x", get_conf_byte(d, i));
1713 show_machine(struct device *d)
1715 struct pci_dev *p = d->dev;
1717 word sv_id=0, sd_id=0;
1718 char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
1720 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
1722 case PCI_HEADER_TYPE_NORMAL:
1723 sv_id = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1724 sd_id = get_conf_word(d, PCI_SUBSYSTEM_ID);
1726 case PCI_HEADER_TYPE_CARDBUS:
1727 sv_id = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1728 sd_id = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1734 printf("Device:\t");
1737 printf("Class:\t%s\n",
1738 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0));
1739 printf("Vendor:\t%s\n",
1740 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, 0, 0));
1741 printf("Device:\t%s\n",
1742 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, 0, 0));
1743 if (sv_id && sv_id != 0xffff)
1745 printf("SVendor:\t%s\n",
1746 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, sv_id, sd_id));
1747 printf("SDevice:\t%s\n",
1748 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1750 if (c = get_conf_byte(d, PCI_REVISION_ID))
1751 printf("Rev:\t%02x\n", c);
1752 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1753 printf("ProgIf:\t%02x\n", c);
1758 printf(" \"%s\" \"%s\" \"%s\"",
1759 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS,
1760 get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0),
1761 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR,
1762 p->vendor_id, p->device_id, 0, 0),
1763 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE,
1764 p->vendor_id, p->device_id, 0, 0));
1765 if (c = get_conf_byte(d, PCI_REVISION_ID))
1766 printf(" -r%02x", c);
1767 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1768 printf(" -p%02x", c);
1769 if (sv_id && sv_id != 0xffff)
1770 printf(" \"%s\" \"%s\"",
1771 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id, sv_id, sd_id),
1772 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1774 printf(" \"\" \"\"");
1780 show_device(struct device *d)
1782 if (machine_readable)
1790 if (verbose || show_hex)
1799 for(d=first_dev; d; d=d->next)
1806 struct bridge *chain; /* Single-linked list of bridges */
1807 struct bridge *next, *child; /* Tree of bridges */
1808 struct bus *first_bus; /* List of busses connected to this bridge */
1809 unsigned int domain;
1810 unsigned int primary, secondary, subordinate; /* Bus numbers */
1811 struct device *br_dev;
1815 unsigned int domain;
1816 unsigned int number;
1817 struct bus *sibling;
1818 struct device *first_dev, **last_dev;
1821 static struct bridge host_bridge = { NULL, NULL, NULL, NULL, 0, ~0, 0, ~0, NULL };
1824 find_bus(struct bridge *b, unsigned int domain, unsigned int n)
1828 for(bus=b->first_bus; bus; bus=bus->sibling)
1829 if (bus->domain == domain && bus->number == n)
1835 new_bus(struct bridge *b, unsigned int domain, unsigned int n)
1837 struct bus *bus = xmalloc(sizeof(struct bus));
1839 bus = xmalloc(sizeof(struct bus));
1840 bus->domain = domain;
1842 bus->sibling = b->first_bus;
1843 bus->first_dev = NULL;
1844 bus->last_dev = &bus->first_dev;
1850 insert_dev(struct device *d, struct bridge *b)
1852 struct pci_dev *p = d->dev;
1855 if (! (bus = find_bus(b, p->domain, p->bus)))
1858 for(c=b->child; c; c=c->next)
1859 if (c->domain == p->domain && c->secondary <= p->bus && p->bus <= c->subordinate)
1864 bus = new_bus(b, p->domain, p->bus);
1866 /* Simple insertion at the end _does_ guarantee the correct order as the
1867 * original device list was sorted by (domain, bus, devfn) lexicographically
1868 * and all devices on the new list have the same bus number.
1871 bus->last_dev = &d->next;
1878 struct device *d, *d2;
1879 struct bridge **last_br, *b;
1881 /* Build list of bridges */
1883 last_br = &host_bridge.chain;
1884 for(d=first_dev; d; d=d->next)
1886 word class = get_conf_word(d, PCI_CLASS_DEVICE);
1887 byte ht = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1888 if (class == PCI_CLASS_BRIDGE_PCI &&
1889 (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS))
1891 b = xmalloc(sizeof(struct bridge));
1892 b->domain = d->dev->domain;
1893 if (ht == PCI_HEADER_TYPE_BRIDGE)
1895 b->primary = get_conf_byte(d, PCI_CB_PRIMARY_BUS);
1896 b->secondary = get_conf_byte(d, PCI_CB_CARD_BUS);
1897 b->subordinate = get_conf_byte(d, PCI_CB_SUBORDINATE_BUS);
1901 b->primary = get_conf_byte(d, PCI_PRIMARY_BUS);
1902 b->secondary = get_conf_byte(d, PCI_SECONDARY_BUS);
1903 b->subordinate = get_conf_byte(d, PCI_SUBORDINATE_BUS);
1906 last_br = &b->chain;
1907 b->next = b->child = NULL;
1908 b->first_bus = NULL;
1914 /* Create a bridge tree */
1916 for(b=&host_bridge; b; b=b->chain)
1918 struct bridge *c, *best;
1920 for(c=&host_bridge; c; c=c->chain)
1921 if (c != b && (c == &host_bridge || b->domain == c->domain) &&
1922 b->primary >= c->secondary && b->primary <= c->subordinate &&
1923 (!best || best->subordinate - best->primary > c->subordinate - c->primary))
1927 b->next = best->child;
1932 /* Insert secondary bus for each bridge */
1934 for(b=&host_bridge; b; b=b->chain)
1935 if (!find_bus(b, b->domain, b->secondary))
1936 new_bus(b, b->domain, b->secondary);
1938 /* Create bus structs and link devices */
1940 for(d=first_dev; d;)
1943 insert_dev(d, &host_bridge);
1949 print_it(byte *line, byte *p)
1953 fputs(line, stdout);
1954 for(p=line; *p; p++)
1955 if (*p == '+' || *p == '|')
1961 static void show_tree_bridge(struct bridge *, byte *, byte *);
1964 show_tree_dev(struct device *d, byte *line, byte *p)
1966 struct pci_dev *q = d->dev;
1970 p += sprintf(p, "%02x.%x", q->dev, q->func);
1971 for(b=&host_bridge; b; b=b->chain)
1974 if (b->secondary == b->subordinate)
1975 p += sprintf(p, "-[%04x:%02x]-", b->domain, b->secondary);
1977 p += sprintf(p, "-[%04x:%02x-%02x]-", b->domain, b->secondary, b->subordinate);
1978 show_tree_bridge(b, line, p);
1982 p += sprintf(p, " %s",
1983 pci_lookup_name(pacc, namebuf, sizeof(namebuf),
1984 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1985 q->vendor_id, q->device_id, 0, 0));
1990 show_tree_bus(struct bus *b, byte *line, byte *p)
1994 else if (!b->first_dev->next)
1998 show_tree_dev(b->first_dev, line, p);
2002 struct device *d = b->first_dev;
2007 show_tree_dev(d, line, p+2);
2012 show_tree_dev(d, line, p+2);
2017 show_tree_bridge(struct bridge *b, byte *line, byte *p)
2020 if (!b->first_bus->sibling)
2022 if (b == &host_bridge)
2023 p += sprintf(p, "[%04x:%02x]-", b->domain, b->first_bus->number);
2024 show_tree_bus(b->first_bus, line, p);
2028 struct bus *u = b->first_bus;
2033 k = p + sprintf(p, "+-[%04x:%02x]-", u->domain, u->number);
2034 show_tree_bus(u, line, k);
2037 k = p + sprintf(p, "\\-[%04x:%02x]-", u->domain, u->number);
2038 show_tree_bus(u, line, k);
2048 show_tree_bridge(&host_bridge, line, line);
2051 /* Bus mapping mode */
2054 struct bus_bridge *next;
2055 byte this, dev, func, first, last, bug;
2061 struct bus_bridge *bridges, *via;
2064 static struct bus_info *bus_info;
2067 map_bridge(struct bus_info *bi, struct device *d, int np, int ns, int nl)
2069 struct bus_bridge *b = xmalloc(sizeof(struct bus_bridge));
2070 struct pci_dev *p = d->dev;
2072 b->next = bi->bridges;
2074 b->this = get_conf_byte(d, np);
2077 b->first = get_conf_byte(d, ns);
2078 b->last = get_conf_byte(d, nl);
2079 printf("## %02x.%02x:%d is a bridge from %02x to %02x-%02x\n",
2080 p->bus, p->dev, p->func, b->this, b->first, b->last);
2081 if (b->this != p->bus)
2082 printf("!!! Bridge points to invalid primary bus.\n");
2083 if (b->first > b->last)
2085 printf("!!! Bridge points to invalid bus range.\n");
2094 int verbose = pacc->debugging;
2095 struct bus_info *bi = bus_info + bus;
2099 printf("Mapping bus %02x\n", bus);
2100 for(dev = 0; dev < 32; dev++)
2101 if (filter.slot < 0 || filter.slot == dev)
2104 for(func = 0; func < func_limit; func++)
2105 if (filter.func < 0 || filter.func == func)
2107 /* XXX: Bus mapping supports only domain 0 */
2108 struct pci_dev *p = pci_get_dev(pacc, 0, bus, dev, func);
2109 u16 vendor = pci_read_word(p, PCI_VENDOR_ID);
2110 if (vendor && vendor != 0xffff)
2112 if (!func && (pci_read_byte(p, PCI_HEADER_TYPE) & 0x80))
2115 printf("Discovered device %02x:%02x.%d\n", bus, dev, func);
2117 if (d = scan_device(p))
2120 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
2122 case PCI_HEADER_TYPE_BRIDGE:
2123 map_bridge(bi, d, PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS);
2125 case PCI_HEADER_TYPE_CARDBUS:
2126 map_bridge(bi, d, PCI_CB_PRIMARY_BUS, PCI_CB_CARD_BUS, PCI_CB_SUBORDINATE_BUS);
2132 printf("But it was filtered out.\n");
2140 do_map_bridges(int bus, int min, int max)
2142 struct bus_info *bi = bus_info + bus;
2143 struct bus_bridge *b;
2146 for(b=bi->bridges; b; b=b->next)
2148 if (bus_info[b->first].guestbook)
2150 else if (b->first < min || b->last > max)
2154 bus_info[b->first].via = b;
2155 do_map_bridges(b->first, b->first, b->last);
2165 printf("\nSummary of buses:\n\n");
2166 for(i=0; i<256; i++)
2167 if (bus_info[i].exists && !bus_info[i].guestbook)
2168 do_map_bridges(i, 0, 255);
2169 for(i=0; i<256; i++)
2171 struct bus_info *bi = bus_info + i;
2172 struct bus_bridge *b = bi->via;
2176 printf("%02x: ", i);
2178 printf("Entered via %02x:%02x.%d\n", b->this, b->dev, b->func);
2180 printf("Primary host bus\n");
2182 printf("Secondary host bus (?)\n");
2184 for(b=bi->bridges; b; b=b->next)
2186 printf("\t%02x.%d Bridge to %02x-%02x", b->dev, b->func, b->first, b->last);
2190 printf(" <overlap bug>");
2193 printf(" <crossing bug>");
2204 if (pacc->method == PCI_ACCESS_PROC_BUS_PCI ||
2205 pacc->method == PCI_ACCESS_DUMP)
2206 printf("WARNING: Bus mapping can be reliable only with direct hardware access enabled.\n\n");
2207 bus_info = xmalloc(sizeof(struct bus_info) * 256);
2208 bzero(bus_info, sizeof(struct bus_info) * 256);
2209 if (filter.bus >= 0)
2210 do_map_bus(filter.bus);
2214 for(bus=0; bus<256; bus++)
2223 main(int argc, char **argv)
2228 if (argc == 2 && !strcmp(argv[1], "--version"))
2230 puts("lspci version " PCIUTILS_VERSION);
2236 pci_filter_init(pacc, &filter);
2238 while ((i = getopt(argc, argv, options)) != -1)
2242 pacc->numeric_ids = 1;
2248 pacc->buscentric = 1;
2249 buscentric_view = 1;
2252 if (msg = pci_filter_parse_slot(&filter, optarg))
2256 if (msg = pci_filter_parse_id(&filter, optarg))
2266 pacc->id_file_name = optarg;
2275 if (parse_generic_option(i, pacc, optarg))
2278 fprintf(stderr, help_msg, pacc->id_file_name);